6efc7b093d
It improves on sio(4) in the following areas: o Fully newbusified to allow for memory mapped I/O. This is a must for ia64 and sparc64, o Machine dependent code to take full advantage of machine and firm- ware specific ways to define serial consoles and/or debug ports. o Hardware abstraction layer to allow the driver to be used with various UARTs, such as the well-known ns8250 family of UARTs, the Siemens sab82532 or the Zilog Z8530. This is especially important for pc98 and sparc64 where it's common to have different UARTs, o The notion of system devices to unkludge low-level consoles and remote gdb ports and provides the mechanics necessary to support the keyboard on sparc64 (which is UART based). o The notion of a kernel interface so that a UART can be tied to something other than the well-known TTY interface. This is needed on sparc64 to present the user with a device and ioctl handling suitable for a keyboard, but also allows us to cleanly hide an UART when used as a debug port. Following is a list of features and bugs/flaws specific to the ns8250 family of UARTs as compared to their support in sio(4): o The uart(4) driver determines the FIFO size and automaticly takes advantages of larger FIFOs and/or additional features. Note that since I don't have sufficient access to 16[679]5x UARTs, hardware flow control has not been enabled. This is almost trivial to do, provided one can test. The downside of this is that broken UARTs are more likely to not work correctly with uart(4). The need for tunables or knobs may be large enough to warrant their creation. o The uart(4) driver does not share the same bumpy history as sio(4) and will therefore not provide the necessary hooks, tweaks, quirks or work-arounds to deal with once common hardware. To that extend, uart(4) supports a subset of the UARTs that sio(4) supports. The question before us is whether the subset is sufficient for current hardware. o There is no support for multiport UARTs in uart(4). The decision behind this is that uart(4) deals with one EIA RS232-C interface. Packaging of multiple interfaces in a single chip or on a single expansion board is beyond the scope of uart(4) and is now mostly left for puc(4) to deal with. Lack of hardware made it impossible to actually implement such a dependency other than is present for the dual channel SAB82532 and Z8350 SCCs. The current list of missing features is: o No configuration capabilities. A set of tunables and sysctls is being worked out. There are likely not going to be any or much compile-time knobs. Such configuration does not fit well with current hardware. o No support for the PPS API. This is partly dependent on the ability to configure uart(4) and partly dependent on having sufficient information to implement it properly. As usual, the manpage is present but lacks the attention the software has gotten.
154 lines
4.9 KiB
C
154 lines
4.9 KiB
C
/*
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* Copyright (c) 2003 Marcel Moolenaar
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_UART_DEV_NS8250_H_
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#define _DEV_UART_DEV_NS8250_H_
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/* Enhanced Feature Register. */
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#define EFR_CTS 0x80
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#define EFR_RTS 0x40
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#define EFR_SCD 0x20 /* Special Character Detect. */
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#define EFR_EFC 0x10 /* Enhanced Function Control. */
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#define EFR_SFC_MASK 0x0f /* Software Flow Control. */
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#define EFR_SFC_TX12 0x0c /* BIT: Transmit XON1+2/XOFF1+2. */
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#define EFR_SFC_TX1 0x08 /* BIT: Transmit XON1/XOFF1. */
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#define EFR_SFC_TX2 0x04 /* BIT: Transmit XON2/XOFF2. */
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#define EFR_SFC_RX1 0x02 /* BIT: Receive XON1/XOFF1. */
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#define EFR_SFC_RX2 0x01 /* BIT: Receive XON2/XOFF2. */
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#define EFR_SFC_T12R12 0x0f /* VAL: TX 1+2, RX 1+2. */
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#define EFR_SFC_T1R12 0x0b /* VAL: TX 1, RX 1+2. */
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#define EFR_SFC_T2R12 0x07 /* VAL: TX 2, RX 1+2. */
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/* FIFO Control Register. */
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#define FCR_RX_HIGH 0xc0
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#define FCR_RX_MEDH 0x80
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#define FCR_RX_MEDL 0x40
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#define FCR_RX_LOW 0x00
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#define FCR_TX_HIGH 0x30
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#define FCR_TX_MEDH 0x20
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#define FCR_TX_LOW 0x10
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#define FCR_TX_MEDL 0x00
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#define FCR_DMA 0x08
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#define FCR_XMT_RST 0x04
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#define FCR_RCV_RST 0x02
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#define FCR_ENABLE 0x01
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/* Interrupt Enable Register. */
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#define IER_CTS 0x80
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#define IER_RTS 0x40
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#define IER_XOFF 0x20
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#define IER_SLEEP 0x10
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#define IER_EMSC 0x08
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#define IER_ERLS 0x04
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#define IER_ETXRDY 0x02
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#define IER_ERXRDY 0x01
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/* Interrupt Identification Register. */
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#define IIR_FIFO_MASK 0xc0
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#define IIR_RTSCTS 0x20
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#define IIR_XOFF 0x10
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#define IIR_IMASK 0x0f
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#define IIR_RXTOUT 0x0c
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#define IIR_RLS 0x06
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#define IIR_RXRDY 0x04
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#define IIR_TXRDY 0x02
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#define IIR_MLSC 0x00
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#define IIR_NOPEND 0x01
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/* Line Control Register. */
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#define LCR_DLAB 0x80
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#define LCR_SBREAK 0x40
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#define LCR_PZERO 0x30
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#define LCR_PONE 0x20
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#define LCR_PEVEN 0x10
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#define LCR_PODD 0x00
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#define LCR_PENAB 0x08
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#define LCR_STOPB 0x04
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#define LCR_8BITS 0x03
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#define LCR_7BITS 0x02
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#define LCR_6BITS 0x01
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#define LCR_5BITS 0x00
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/* Line Status Register. */
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#define LSR_DERR 0x80
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#define LSR_TEMT 0x40 /* Transmitter Empty. */
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#define LSR_THRE 0x20 /* Transmitter Holding Register Empty. */
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#define LSR_BI 0x10
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#define LSR_FE 0x08
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#define LSR_PE 0x04
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#define LSR_OE 0x02
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#define LSR_RXRDY 0x01
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/* Modem Control Register. */
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#define MCR_CS 0x80
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#define MCR_IRE 0x40
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#define MCR_ISEL 0x20
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#define MCR_LOOPBACK 0x10
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#define MCR_IE 0x08
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#define MCR_LBDCD MCR_IE
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#define MCR_LBRI 0x04
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#define MCR_RTS 0x02
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#define MCR_DTR 0x01
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/* Modem Status Register. */
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#define MSR_DCD 0x80
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#define MSR_RI 0x40
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#define MSR_DSR 0x20
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#define MSR_CTS 0x10
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#define MSR_DDCD 0x08
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#define MSR_TERI 0x04
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#define MSR_DDSR 0x02
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#define MSR_DCTS 0x01
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/* General registers. */
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#define REG_DATA 0 /* Data Register. */
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#define REG_RBR REG_DATA /* Receiver Buffer Register (R). */
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#define REG_THR REG_DATA /* Transmitter Holding Register (W). */
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#define REG_IER 1 /* Interrupt Enable Register */
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#define REG_IIR 2 /* Interrupt Ident. Register (R). */
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#define REG_FCR 2 /* FIFO Control Register (W). */
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#define REG_LCR 3 /* Line Control Register. */
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#define REG_MCR 4 /* Modem Control Register. */
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#define REG_LSR 5 /* Line Status Register. */
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#define REG_MSR 6 /* Modem Status Register. */
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#define REG_SPR 7 /* Scratch Pad Register. */
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/* Baudrate registers (LCR[7] = 1). */
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#define REG_DLBL 0 /* Divisor Latch (LSB). */
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#define REG_DLBH 1 /* Divisor Latch (MSB). */
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#define REG_DL REG_DLBL /* Divisor Latch (16-bit I/O). */
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/* Enhanced registers (LCR = 0xBF). */
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#define REG_EFR 2 /* Enhanced Feature Register. */
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#define REG_XON1 4 /* XON character 1. */
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#define REG_XON2 5 /* XON character 2. */
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#define REG_XOFF1 6 /* XOFF character 1. */
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#define REG_XOFF2 7 /* XOFF character 2. */
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#endif /* _DEV_UART_DEV_NS8250_H_ */
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