fd3ddbd038
The nxge driver provides support for Neterion Xframe-I and Xframe-II adapters. The driver supports TCP Segmentation Offload (TSO/LSO), Jumbo frames (5 buffer mode), Header separation (2 and 3 Receive buffer modes), VLAN, and Promiscuous mode. Submitted by: Neterion Reviewed by: rwatson Approved by: re (kensmith)
759 lines
28 KiB
C
759 lines
28 KiB
C
/*-
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* Copyright (c) 2002-2007 Neterion, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* xge-osdep.h
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*
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* Platform-dependent "glue" code
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*/
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#ifndef XGE_OSDEP_H
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#define XGE_OSDEP_H
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/******************************************
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* Includes and defines
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******************************************/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <sys/protosw.h>
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#include <sys/socket.h>
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#include <sys/malloc.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/stddef.h>
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#include <sys/types.h>
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#include <sys/sockio.h>
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#include <sys/proc.h>
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#include <sys/mutex.h>
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#include <sys/types.h>
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#include <sys/endian.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/clock.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pci_private.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_var.h>
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#include <net/bpf.h>
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#include <net/if_types.h>
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#define XGE_OS_PLATFORM_64BIT
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#if BYTE_ORDER == BIG_ENDIAN
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#define XGE_OS_HOST_BIG_ENDIAN 1
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#elif BYTE_ORDER == LITTLE_ENDIAN
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#define XGE_OS_HOST_LITTLE_ENDIAN 1
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#endif
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#define XGE_HAL_USE_5B_MODE 1
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#define XGE_HAL_PROCESS_LINK_INT_IN_ISR 1
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#define OS_NETSTACK_BUF struct mbuf *
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#define XGE_LL_IP_FAST_CSUM(hdr, len) 0
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#define xge_os_ntohs ntohs
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#define xge_os_ntohl ntohl
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#define xge_os_htons htons
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#define xge_os_htonl htonl
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#ifndef __DECONST
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#define __DECONST(type, var) ((type)(uintrptr_t)(const void *)(var))
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#endif
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typedef struct busresources {
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bus_space_tag_t bus_tag; /* DMA Tag */
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bus_space_handle_t bus_handle; /* Bus handle */
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struct resource *bar_start_addr;/* BAR start address */
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} busresource_t;
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typedef struct xge_dma_alloc {
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bus_addr_t dma_phyaddr; /* Physical Address */
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caddr_t dma_viraddr; /* Virtual Address */
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bus_dma_tag_t dma_tag; /* DMA Tag */
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bus_dmamap_t dma_map; /* DMA Map */
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bus_dma_segment_t dma_segment; /* DMA Segment */
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bus_size_t dma_size; /* Size */
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int dma_nseg; /* Maximum scatter-gather segs. */
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} xdma;
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struct xge_dma_mbuf {
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bus_addr_t dma_phyaddr; /* Physical Address */
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bus_dmamap_t dma_map; /* DMA Map */
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};
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typedef struct pci_info {
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device_t device; /* Device */
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struct resource *regmap0; /* Resource for BAR0 */
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struct resource *regmap1; /* Resource for BAR1 */
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void *bar0resource; /* BAR0 tag and handle */
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void *bar1resource; /* BAR1 tag and handle */
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} pci_info_t;
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/******************************************
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* Fixed size primitive types
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******************************************/
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#define u8 uint8_t
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#define u16 uint16_t
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#define u32 uint32_t
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#define u64 uint64_t
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#define ulong_t unsigned long
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#define uint unsigned int
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#define ptrdiff_t ptrdiff_t
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typedef bus_addr_t dma_addr_t;
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typedef struct mtx spinlock_t;
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typedef pci_info_t *pci_dev_h;
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typedef busresource_t *pci_reg_h;
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typedef struct xge_dma_alloc pci_dma_h;
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typedef struct resource *pci_irq_h;
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typedef pci_info_t *pci_cfg_h;
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typedef struct xge_dma_alloc pci_dma_acc_h;
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/******************************************
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* "libc" functionality
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******************************************/
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#define xge_os_memzero(addr, size) bzero(addr, size)
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#define xge_os_memcpy(dst, src, size) bcopy(src, dst, size)
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#define xge_os_memcmp memcmp
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#define xge_os_strcpy strcpy
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#define xge_os_strlen strlen
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#define xge_os_snprintf snprintf
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#define xge_os_sprintf sprintf
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#define xge_os_printf(fmt...) { \
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printf(fmt); \
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printf("\n"); \
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}
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#define xge_os_vaprintf(fmt) { \
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sprintf(fmt, fmt, "\n"); \
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va_list va; \
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va_start(va, fmt); \
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vprintf(fmt, va); \
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va_end(va); \
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}
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#define xge_os_vasprintf(buf, fmt) { \
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va_list va; \
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va_start(va, fmt); \
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(void) vaprintf(buf, fmt, va); \
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va_end(va); \
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}
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#define xge_os_timestamp(buf) { \
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struct timeval current_time; \
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gettimeofday(¤t_time, 0); \
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sprintf(buf, "%08li.%08li: ", current_time.tv_sec, \
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current_time.tv_usec); \
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}
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#define xge_os_println xge_os_printf
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/******************************************
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* Synchronization Primitives
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******************************************/
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/* Initialize the spin lock */
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#define xge_os_spin_lock_init(lockp, ctxh) \
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if(mtx_initialized(lockp) == 0) { \
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mtx_init((lockp), "xge", MTX_NETWORK_LOCK, MTX_DEF); \
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}
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/* Initialize the spin lock (IRQ version) */
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#define xge_os_spin_lock_init_irq(lockp, ctxh) \
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if(mtx_initialized(lockp) == 0) { \
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mtx_init((lockp), "xge", MTX_NETWORK_LOCK, MTX_DEF); \
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}
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/* Destroy the lock */
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#define xge_os_spin_lock_destroy(lockp, ctxh) \
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if(mtx_initialized(lockp) != 0) { \
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mtx_destroy(lockp); \
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}
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/* Destroy the lock (IRQ version) */
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#define xge_os_spin_lock_destroy_irq(lockp, ctxh) \
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if(mtx_initialized(lockp) != 0) { \
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mtx_destroy(lockp); \
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}
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/* Acquire the lock */
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#define xge_os_spin_lock(lockp) \
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if(mtx_owned(lockp) == 0) mtx_lock(lockp)
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/* Release the lock */
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#define xge_os_spin_unlock(lockp) mtx_unlock(lockp)
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/* Acquire the lock (IRQ version) */
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#define xge_os_spin_lock_irq(lockp, flags) { \
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flags = MTX_QUIET; \
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if(mtx_owned(lockp) == 0) mtx_lock_flags(lockp, flags); \
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}
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/* Release the lock (IRQ version) */
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#define xge_os_spin_unlock_irq(lockp, flags) { \
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flags = MTX_QUIET; \
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mtx_unlock_flags(lockp, flags); \
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}
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/* Write memory barrier */
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#define xge_os_wmb()
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/* Delay (in micro seconds) */
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#define xge_os_udelay(us) DELAY(us)
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/* Delay (in milli seconds) */
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#define xge_os_mdelay(ms) DELAY(ms * 1000)
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/* Compare and exchange */
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//#define xge_os_cmpxchg(targetp, cmd, newval)
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/******************************************
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* Misc primitives
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******************************************/
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#define xge_os_unlikely(x) (x)
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#define xge_os_prefetch(x) (x=x)
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#define xge_os_prefetchw(x) (x=x)
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#define xge_os_bug(fmt...) printf(fmt...)
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#define xge_os_htohs ntohs
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#define xge_os_ntohl ntohl
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#define xge_os_htons htons
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#define xge_os_htonl htonl
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/******************************************
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* Compiler Stuffs
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******************************************/
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#define __xge_os_attr_cacheline_aligned
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#define __xge_os_cacheline_size 32
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/******************************************
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* Memory Primitives
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******************************************/
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#define XGE_OS_INVALID_DMA_ADDR ((dma_addr_t)0)
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/******************************************
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* xge_os_malloc - Allocate non DMA-able memory.
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* @pdev: Device context.
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* @size: Size to allocate.
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*
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* Allocate @size bytes of memory. This allocation can sleep, and
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* therefore, and therefore it requires process context. In other words,
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* xge_os_malloc() cannot be called from the interrupt context.
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* Use xge_os_free() to free the allocated block.
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*
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* Returns: Pointer to allocated memory, NULL - on failure.
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*
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* See also: xge_os_free().
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******************************************/
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static inline void *
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xge_os_malloc(pci_dev_h pdev, unsigned long size) {
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void *vaddr = malloc((size), M_DEVBUF, M_NOWAIT);
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xge_os_memzero(vaddr, size);
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XGE_OS_MEMORY_CHECK_MALLOC(vaddr, size, file, line);
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return (vaddr);
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}
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/******************************************
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* xge_os_free - Free non DMA-able memory.
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* @pdev: Device context.
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* @vaddr: Address of the allocated memory block.
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* @size: Some OS's require to provide size on free
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*
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* Free the memory area obtained via xge_os_malloc().
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* This call may also sleep, and therefore it cannot be used inside
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* interrupt.
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*
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* See also: xge_os_malloc().
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******************************************/
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static inline void
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xge_os_free(pci_dev_h pdev, const void *vaddr, unsigned long size) {
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XGE_OS_MEMORY_CHECK_FREE(vaddr, size);
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free(__DECONST(void *, vaddr), M_DEVBUF);
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}
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static void
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xge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) {
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if(error) return;
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*(bus_addr_t *) arg = segs->ds_addr;
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return;
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}
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/******************************************
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* xge_os_dma_malloc - Allocate DMA-able memory.
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* @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
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* @size: Size (in bytes) to allocate.
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* @dma_flags: XGE_OS_DMA_CACHELINE_ALIGNED,
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* XGE_OS_DMA_STREAMING,
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* XGE_OS_DMA_CONSISTENT
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* Note that the last two flags are mutually exclusive.
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* @p_dmah: Handle used to map the memory onto the corresponding device memory
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* space. See xge_os_dma_map(). The handle is an out-parameter
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* returned by the function.
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* @p_dma_acch: One more DMA handle used subsequently to free the
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* DMA object (via xge_os_dma_free()).
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*
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* Allocate DMA-able contiguous memory block of the specified @size.
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* This memory can be subsequently freed using xge_os_dma_free().
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* Note: can be used inside interrupt context.
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*
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* Returns: Pointer to allocated memory(DMA-able), NULL on failure.
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*
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******************************************/
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static inline void *
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xge_os_dma_malloc(pci_dev_h pdev, unsigned long size, int dma_flags,
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pci_dma_h *p_dmah, pci_dma_acc_h *p_dma_acch) {
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int retValue = bus_dma_tag_create(
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bus_get_dma_tag(pdev->device), /* Parent */
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PAGE_SIZE, /* Alignment no specific alignment */
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0, /* Bounds */
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BUS_SPACE_MAXADDR, /* Low Address */
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BUS_SPACE_MAXADDR, /* High Address */
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NULL, /* Filter */
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NULL, /* Filter arg */
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size, /* Max Size */
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1, /* n segments */
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size, /* max segment size */
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BUS_DMA_ALLOCNOW, /* Flags */
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NULL, /* lockfunction */
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NULL, /* lock arg */
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&p_dmah->dma_tag); /* DMA tag */
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if(retValue != 0) {
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xge_os_printf("bus_dma_tag_create failed\n");
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goto fail_1;
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}
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p_dmah->dma_size = size;
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retValue = bus_dmamem_alloc(p_dmah->dma_tag,
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(void **)&p_dmah->dma_viraddr, BUS_DMA_NOWAIT, &p_dmah->dma_map);
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if(retValue != 0) {
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xge_os_printf("bus_dmamem_alloc failed\n");
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goto fail_2;
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}
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return(p_dmah->dma_viraddr);
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fail_2: bus_dma_tag_destroy(p_dmah->dma_tag);
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fail_1: return(NULL);
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}
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/******************************************
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* xge_os_dma_free - Free previously allocated DMA-able memory.
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* @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
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* @vaddr: Virtual address of the DMA-able memory.
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* @p_dma_acch: DMA handle used to free the resource.
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* @p_dmah: DMA handle used for mapping. See xge_os_dma_malloc().
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*
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* Free DMA-able memory originally allocated by xge_os_dma_malloc().
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* Note: can be used inside interrupt.
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* See also: xge_os_dma_malloc().
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******************************************/
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static inline void
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xge_os_dma_free(pci_dev_h pdev, const void *vaddr, int size,
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pci_dma_acc_h *p_dma_acch, pci_dma_h *p_dmah) {
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XGE_OS_MEMORY_CHECK_FREE(p_dmah->dma_viraddr, size);
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bus_dmamem_free(p_dmah->dma_tag, p_dmah->dma_viraddr, p_dmah->dma_map);
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bus_dma_tag_destroy(p_dmah->dma_tag);
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p_dmah->dma_map = NULL;
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p_dmah->dma_tag = NULL;
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p_dmah->dma_viraddr = NULL;
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return;
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}
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/******************************************
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* IO/PCI/DMA Primitives
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******************************************/
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#define XGE_OS_DMA_DIR_TODEVICE 0
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#define XGE_OS_DMA_DIR_FROMDEVICE 1
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#define XGE_OS_DMA_DIR_BIDIRECTIONAL 2
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/******************************************
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* xge_os_pci_read8 - Read one byte from device PCI configuration.
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* @pdev: Device context. Some OSs require device context to perform
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* PIO and/or config space IO.
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* @cfgh: PCI configuration space handle.
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* @where: Offset in the PCI configuration space.
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* @val: Address of the result.
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*
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* Read byte value from the specified @regh PCI configuration space at the
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* specified offset = @where.
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* Returns: 0 - success, non-zero - failure.
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******************************************/
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#define xge_os_pci_read8(pdev, cfgh, where, val) \
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(*(val) = pci_read_config(pdev->device, where, 1))
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/******************************************
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* xge_os_pci_write8 - Write one byte into device PCI configuration.
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* @pdev: Device context. Some OSs require device context to perform
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* PIO and/or config space IO.
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* @cfgh: PCI configuration space handle.
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* @where: Offset in the PCI configuration space.
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* @val: Value to write.
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*
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* Write byte value into the specified PCI configuration space
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* Returns: 0 - success, non-zero - failure.
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******************************************/
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#define xge_os_pci_write8(pdev, cfgh, where, val) \
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pci_write_config(pdev->device, where, val, 1)
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/******************************************
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* xge_os_pci_read16 - Read 16bit word from device PCI configuration.
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* @pdev: Device context.
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* @cfgh: PCI configuration space handle.
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* @where: Offset in the PCI configuration space.
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* @val: Address of the 16bit result.
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*
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* Read 16bit value from the specified PCI configuration space at the
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* specified offset.
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* Returns: 0 - success, non-zero - failure.
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******************************************/
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#define xge_os_pci_read16(pdev, cfgh, where, val) \
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(*(val) = pci_read_config(pdev->device, where, 2))
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/******************************************
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* xge_os_pci_write16 - Write 16bit word into device PCI configuration.
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* @pdev: Device context.
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* @cfgh: PCI configuration space handle.
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* @where: Offset in the PCI configuration space.
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* @val: Value to write.
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*
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* Write 16bit value into the specified @offset in PCI
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* configuration space.
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* Returns: 0 - success, non-zero - failure.
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******************************************/
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#define xge_os_pci_write16(pdev, cfgh, where, val) \
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pci_write_config(pdev->device, where, val, 2)
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/******************************************
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* xge_os_pci_read32 - Read 32bit word from device PCI configuration.
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* @pdev: Device context.
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* @cfgh: PCI configuration space handle.
|
|
* @where: Offset in the PCI configuration space.
|
|
* @val: Address of 32bit result.
|
|
*
|
|
* Read 32bit value from the specified PCI configuration space at the
|
|
* specified offset.
|
|
* Returns: 0 - success, non-zero - failure.
|
|
******************************************/
|
|
#define xge_os_pci_read32(pdev, cfgh, where, val) \
|
|
(*(val) = pci_read_config(pdev->device, where, 4))
|
|
|
|
/******************************************
|
|
* xge_os_pci_write32 - Write 32bit word into device PCI configuration.
|
|
* @pdev: Device context.
|
|
* @cfgh: PCI configuration space handle.
|
|
* @where: Offset in the PCI configuration space.
|
|
* @val: Value to write.
|
|
*
|
|
* Write 32bit value into the specified @offset in PCI
|
|
* configuration space.
|
|
* Returns: 0 - success, non-zero - failure.
|
|
******************************************/
|
|
#define xge_os_pci_write32(pdev, cfgh, where, val) \
|
|
pci_write_config(pdev->device, where, val, 4)
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_read8 - Read 1 byte from device memory mapped space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Returns: 1 byte value read from the specified (mapped) memory space address.
|
|
******************************************/
|
|
static inline u8
|
|
xge_os_pio_mem_read8(pci_dev_h pdev, pci_reg_h regh, void *addr)
|
|
{
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
|
|
return bus_space_read_1(tag, handle, (caddr_t)(addr) - addrss);
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_write8 - Write 1 byte into device memory mapped
|
|
* space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @val: Value to write.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Write byte value into the specified (mapped) device memory space.
|
|
******************************************/
|
|
static inline void
|
|
xge_os_pio_mem_write8(pci_dev_h pdev, pci_reg_h regh, u8 val, void *addr)
|
|
{
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
|
|
bus_space_write_1(tag, handle, (caddr_t)(addr) - addrss, val);
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_read16 - Read 16bit from device memory mapped space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Returns: 16bit value read from the specified (mapped) memory space address.
|
|
******************************************/
|
|
static inline u16
|
|
xge_os_pio_mem_read16(pci_dev_h pdev, pci_reg_h regh, void *addr)
|
|
{
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
|
|
return bus_space_read_2(tag, handle, (caddr_t)(addr) - addrss);
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_write16 - Write 16bit into device memory mapped space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @val: Value to write.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Write 16bit value into the specified (mapped) device memory space.
|
|
******************************************/
|
|
static inline void
|
|
xge_os_pio_mem_write16(pci_dev_h pdev, pci_reg_h regh, u16 val, void *addr)
|
|
{
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
|
|
bus_space_write_2(tag, handle, (caddr_t)(addr) - addrss, val);
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_read32 - Read 32bit from device memory mapped space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Returns: 32bit value read from the specified (mapped) memory space address.
|
|
******************************************/
|
|
static inline u32
|
|
xge_os_pio_mem_read32(pci_dev_h pdev, pci_reg_h regh, void *addr)
|
|
{
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
|
|
return bus_space_read_4(tag, handle, (caddr_t)(addr) - addrss);
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_write32 - Write 32bit into device memory space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @val: Value to write.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Write 32bit value into the specified (mapped) device memory space.
|
|
******************************************/
|
|
static inline void
|
|
xge_os_pio_mem_write32(pci_dev_h pdev, pci_reg_h regh, u32 val, void *addr)
|
|
{
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
bus_space_write_4(tag, handle, (caddr_t)(addr) - addrss, val);
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_read64 - Read 64bit from device memory mapped space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Returns: 64bit value read from the specified (mapped) memory space address.
|
|
******************************************/
|
|
static inline u64
|
|
xge_os_pio_mem_read64(pci_dev_h pdev, pci_reg_h regh, void *addr)
|
|
{
|
|
u64 value1, value2;
|
|
|
|
bus_space_tag_t tag =
|
|
(bus_space_tag_t)(((busresource_t *)regh)->bus_tag);
|
|
bus_space_handle_t handle =
|
|
(bus_space_handle_t)(((busresource_t *)regh)->bus_handle);
|
|
caddr_t addrss = (caddr_t)(((busresource_t *)(regh))->bar_start_addr);
|
|
|
|
value1 = bus_space_read_4(tag, handle, (caddr_t)(addr) + 4 - addrss);
|
|
value1 <<= 32;
|
|
value2 = bus_space_read_4(tag, handle, (caddr_t)(addr) - addrss);
|
|
value1 |= value2;
|
|
return value1;
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_pio_mem_write64 - Write 32bit into device memory space.
|
|
* @pdev: Device context.
|
|
* @regh: PCI configuration space handle.
|
|
* @val: Value to write.
|
|
* @addr: Address in device memory space.
|
|
*
|
|
* Write 64bit value into the specified (mapped) device memory space.
|
|
******************************************/
|
|
static inline void
|
|
xge_os_pio_mem_write64(pci_dev_h pdev, pci_reg_h regh, u64 val, void *addr)
|
|
{
|
|
u32 vall = val & 0xffffffff;
|
|
xge_os_pio_mem_write32(pdev, regh, vall, addr);
|
|
xge_os_pio_mem_write32(pdev, regh, val >> 32, ((caddr_t)(addr) + 4));
|
|
}
|
|
|
|
/******************************************
|
|
* FIXME: document
|
|
******************************************/
|
|
#define xge_os_flush_bridge xge_os_pio_mem_read64
|
|
|
|
/******************************************
|
|
* xge_os_dma_map - Map DMA-able memory block to, or from, or
|
|
* to-and-from device.
|
|
* @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
|
|
* @dmah: DMA handle used to map the memory block. Obtained via
|
|
* xge_os_dma_malloc().
|
|
* @vaddr: Virtual address of the DMA-able memory.
|
|
* @size: Size (in bytes) to be mapped.
|
|
* @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.)
|
|
* @dma_flags: XGE_OS_DMA_CACHELINE_ALIGNED,
|
|
* XGE_OS_DMA_STREAMING,
|
|
* XGE_OS_DMA_CONSISTENT
|
|
* Note that the last two flags are mutually exclusive.
|
|
*
|
|
* Map a single memory block.
|
|
*
|
|
* Returns: DMA address of the memory block,
|
|
* XGE_OS_INVALID_DMA_ADDR on failure.
|
|
*
|
|
* See also: xge_os_dma_malloc(), xge_os_dma_unmap(),
|
|
* xge_os_dma_sync().
|
|
******************************************/
|
|
static inline dma_addr_t
|
|
xge_os_dma_map(pci_dev_h pdev, pci_dma_h dmah, void *vaddr, size_t size,
|
|
int dir, int dma_flags)
|
|
{
|
|
int retValue =
|
|
bus_dmamap_load(dmah.dma_tag, dmah.dma_map, dmah.dma_viraddr,
|
|
dmah.dma_size, xge_dmamap_cb, &dmah.dma_phyaddr, BUS_DMA_NOWAIT);
|
|
if(retValue != 0) {
|
|
xge_os_printf("bus_dmamap_load_ failed\n");
|
|
return XGE_OS_INVALID_DMA_ADDR;
|
|
}
|
|
dmah.dma_size = size;
|
|
return dmah.dma_phyaddr;
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_dma_unmap - Unmap DMA-able memory.
|
|
* @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
|
|
* @dmah: DMA handle used to map the memory block. Obtained via
|
|
* xge_os_dma_malloc().
|
|
* @dma_addr: DMA address of the block. Obtained via xge_os_dma_map().
|
|
* @size: Size (in bytes) to be unmapped.
|
|
* @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.)
|
|
*
|
|
* Unmap a single DMA-able memory block that was previously mapped
|
|
* using xge_os_dma_map().
|
|
* See also: xge_os_dma_malloc(), xge_os_dma_map().
|
|
******************************************/
|
|
static inline void
|
|
xge_os_dma_unmap(pci_dev_h pdev, pci_dma_h dmah, dma_addr_t dma_addr,
|
|
size_t size, int dir)
|
|
{
|
|
bus_dmamap_unload(dmah.dma_tag, dmah.dma_map);
|
|
return;
|
|
}
|
|
|
|
/******************************************
|
|
* xge_os_dma_sync - Synchronize mapped memory.
|
|
* @pdev: Device context. Used to allocate/pin/map/unmap DMA-able memory.
|
|
* @dmah: DMA handle used to map the memory block. Obtained via
|
|
* xge_os_dma_malloc().
|
|
* @dma_addr: DMA address of the block. Obtained via xge_os_dma_map().
|
|
* @dma_offset: Offset from start of the blocke. Used by Solaris only.
|
|
* @length: Size of the block.
|
|
* @dir: Direction of this operation (XGE_OS_DMA_DIR_TODEVICE, etc.)
|
|
*
|
|
* Make physical and CPU memory consistent for a single
|
|
* streaming mode DMA translation.
|
|
* This API compiles to NOP on cache-coherent platforms.
|
|
* On non cache-coherent platforms, depending on the direction
|
|
* of the "sync" operation, this API will effectively
|
|
* either invalidate CPU cache (that might contain old data),
|
|
* or flush CPU cache to update physical memory.
|
|
* See also: xge_os_dma_malloc(), xge_os_dma_map(),
|
|
* xge_os_dma_unmap().
|
|
******************************************/
|
|
static inline void
|
|
xge_os_dma_sync(pci_dev_h pdev, pci_dma_h dmah, dma_addr_t dma_addr,
|
|
u64 dma_offset, size_t length, int dir)
|
|
{
|
|
bus_dmasync_op_t syncop;
|
|
switch(dir) {
|
|
case XGE_OS_DMA_DIR_TODEVICE:
|
|
syncop = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_POSTWRITE;
|
|
break;
|
|
|
|
case XGE_OS_DMA_DIR_FROMDEVICE:
|
|
syncop = BUS_DMASYNC_PREREAD | BUS_DMASYNC_POSTREAD;
|
|
break;
|
|
|
|
case XGE_OS_DMA_DIR_BIDIRECTIONAL:
|
|
syncop = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREWRITE;
|
|
break;
|
|
}
|
|
bus_dmamap_sync(dmah.dma_tag, dmah.dma_map, syncop);
|
|
return;
|
|
}
|
|
|
|
#endif /* XGE_OSDEP_H */
|