df180be1a1
ahc_pci.c: ahd_pci.c: aic7xxx.c: aic79xx.c: aic_osm_lib.c: aic_osm_lib.h: Use common OSM routines from aic_osm_lib for bus dma operations, delay routines, accessing CCBs, byte swapping, etc. aic7xxx_pci.c: Provide a better description for the 2915/30LP on attach. aic7xxx.c: aic79xx.c: aic7770.c: aic79xx_pci.c: aic7xxx_pci.c: aic7xxx_93cx6.c: Move FBSDID behind an ifdef so that these core files will still compile under other OSes. aic79xx.h: aic79xx_pci.c: aic79xx.seq: To speed up non-packetized CDB delivery in Rev B, all CDB acks are "released" to the output sync as soon as the command phase starts. There is only one problem with this approach. If the target changes phase before all data are sent, we have left over acks that can go out on the bus in a data phase. Due to other chip contraints, this only happens if the target goes to data-in, but if the acks go out before we can test SDONE, we'll think that the transfer has completed successfully. Work around this by taking advantage of the 400ns or 800ns dead time between command phase and the REQ of the new phase. If the transfer has completed successfully, SCSIEN should fall *long* before we see a phase change. We thus treat any phasemiss that occurs before SCSIEN falls as an incomplete transfer. aic79xx.h: Add the AHD_FAST_CDB_DELIVERY feature. aic79xx_pci.c: Set AHD_FAST_CDB_DELIVERY for all Rev. B parts. aic79xx.seq: Test for PHASEMIS in the command phase for all AHD_FAST_CDB_DELIVERY controlelrs. ahd_pci.c: ahc_pci.c: aic7xxx.h: aic79xx.h: Move definition of controller BAR offsets to core header files. aic7xxx.c: aic79xx.c: In the softc free routine, leave removal of a softc from the global list of softcs to the OSM (the caller of this routine). This allows us to avoid holding the softc list_lock during device destruction where we may have to sleep waiting for our recovery thread to halt. ahc_pci.c: Use ahc_pci_test_register access to validate I/O mapped in addition to the tests already performed for memory mapped access. Remove unused ahc_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. ahd_pci.c: Remove reduntant definition of controller BAR offsets. These are also defined in aic79xx.h. Remove unused ahd_power_state_change() function. The PCI layer in both 4.X and 5.X now offer this functionality. aic7xxx.c: aic79xx.c: aic79xx.h: aic7xxx.h: aic7xxx_osm.c: aic79xx_osm.c: Move timeout handling to the driver cores. In the case of the aic79xx driver, the algorithm has been enhanced to try target resets before performing a bus reset. For the aic7xxx driver, the algorithm is unchanged. Although the drivers do not currently sleep during recovery (recovery is timeout driven), the cores do expect all processing to be performed via a recovery thread. Our timeout handlers are now little stubs that wakeup the recovery thread. aic79xx.c: aic79xx.h: aic79xx_inline.h: Change shared_data allocation to use a map_node so that the sentinel hscb can use this map node in ahd_swap_with_next_hscb. This routine now swaps the hscb_map pointer in additon to the hscb contents so that any sync operations occur on the correct map. physaddr -> busaddr Pointed out by: Jason Thorpe <thorpej@wasabisystems.com> aic79xx.c: Make more use of the in/out/w/l/q macros for accessing byte registers in the chip. Correct some issues in the ahd_flush_qoutfifo() routine. o Run the qoutfifo only once the command channel DMA engine has been halted. This closes a window where we might have missed some entries. o Change ahd_run_data_fifo() to not loop to completion. If we happen to start on the wrong FIFO and the other FIFO has a snapshot savepointers, we might deadlock. This required our delay between FIFO tests to be moved to the ahd_flush_qoutfifo() routine. o Update/add comments. o Remove spurious test for COMPLETE_DMA list being empty when completing transactions from the GSFIFO with residuals. The SCB must be put on the COMPLETE_DMA scb list unconditionally. o When halting command channel DMA activity, we must disable the DMA channel in all cases but an update of the QOUTFIFO. The latter case is required so that the sequencer will update its position in the QOUTFIFO. Previously, we left the channel enabled for all "push" DMAs. This left us vulnerable to the sequencer handling an SCB push long after that SCB was already processed manually by this routine. o Correct the polarity of tests involving ahd_scb_active_in_fifo(). This routine returns non-zero for true. Return to processing bad status completions through the qoutfifo. This reduces the time that the sequencer is kept paused when handling transactions with bad status or underruns. When waiting for the controller to quiece selections, add a delay to our loop. Otherwise we may fail to wait long enough for the sequencer to comply. On H2A4 hardware, use the slow slewrate for non-paced transfers. This mirrors what the Adaptec Windows drivers do. On the Rev B. only slow down the CRC timing for older U160 devices that might need the slower timing. We define "older" as devices that do not support packetized protocol. Wait up to 5000 * 5us for the SEEPROM to become unbusy. Write ops seem to take much longer than read ops. aic79xx.seq: For controllers with the FAINT_LED bug, turn the diagnostic led feature on during selection and reselection. This covers the non-packetized case. The LED will be disabled for non-packetized transfers once we return to the top level idle loop. Add more comments about the busy LED workaround. Extend a critical section around the entire command channel idle loop process. Previously the portion of this handler that directly manipulated the linked list of completed SCBs was not protected. This is the likely cause of the recent reports of commands being completed twice by the driver. Extend critical sections across the test for, and the longjump to, longjump routines. This prevents the firmware from trying to jump to a longjmp handler that was just cleared by the host. Improve the locations of several critical section begin and end points. Typically these changes remove instructions that did not need to be inside a critical section. Close the "busfree after selection, but before busfree interrupts can be enabled" race to just a single sequencer instruction. We now test the BSY line explicitly before clearing the busfree status and enabling the busfree interrupt. Close a race condition in the processing of HS_MAILBOX updates. We now clear the "updated" status before the copy. This ensures that we don't accidentally clear the status incorrectly when the host sneaks in an update just after our last copy, but before we clear the status. This race has never been observed. Don't re-enable SCSIEN if we lose the race to disable SCSIEN in our interrupt handler's workaround for the RevA data-valid too early issue. aic79xx_inline.h: Add comments indicating that the order in which bytes are read or written in ahd_inw and ahd_outw is important. This allows us to use these inlines when accessing registers with side-effects. aic79xx_pci.c: The 29320 and the 29320B are 7902 not 7901 based products. Correct the driver banner. aic7xxx.h: Enable the use of the auto-access pause feature on the aic7870 and aic7880. It was disabled due to an oversight. aic7xxx.reg: Move TARG_IMMEDIATE_SCB to alias LAST_MSG to avoid leaving garbage in MWI_RESIDUAL. This prevents spurious overflows whn operating target mode on controllers that require the MWI_RESIDUAL work-around. aic7xxx.seq: AHC_TMODE_WIDEODD_BUG is a bug, not a softc flag. Reference the correct softc field when testing for its presence. Set the NOT_IDENTIFIED and NO_CDB_SENT bits in SEQ_FLAGS to indicate that the nexus is invalid in await busfree. aic7xxx_93cx6.c: Add support for the C56/C66 versions of the EWEN and EWDS commands. aic7xxx.c: aic7xxx_pci.c: Move test for the validity of left over BIOS data to ahc_test_register_access(). This guarantees that any left over CHIPRST value is not clobbered by our register access test and lost to the test that was in ahc_reset.
1595 lines
34 KiB
Reg
1595 lines
34 KiB
Reg
/*
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* Aic7xxx register and scratch ram definitions.
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*
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* Copyright (c) 1994-2001 Justin T. Gibbs.
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* Copyright (c) 2000-2001 Adaptec Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* substantially similar to the "NO WARRANTY" disclaimer below
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* ("Disclaimer") and any redistribution must be conditioned upon
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* including a substantially similar Disclaimer requirement for further
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* binary redistribution.
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* 3. Neither the names of the above-listed copyright holders nor the names
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* of any contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
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* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic7xxx.reg#40 $"
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/*
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* This file is processed by the aic7xxx_asm utility for use in assembling
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* firmware for the aic7xxx family of SCSI host adapters as well as to generate
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* a C header file for use in the kernel portion of the Aic7xxx driver.
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*
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* All page numbers refer to the Adaptec AIC-7770 Data Book available from
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* Adaptec's Technical Documents Department 1-800-934-2766
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*/
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/*
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* SCSI Sequence Control (p. 3-11).
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* Each bit, when set starts a specific SCSI sequence on the bus
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*/
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register SCSISEQ {
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address 0x000
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access_mode RW
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field TEMODE 0x80
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field ENSELO 0x40
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field ENSELI 0x20
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field ENRSELI 0x10
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field ENAUTOATNO 0x08
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field ENAUTOATNI 0x04
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field ENAUTOATNP 0x02
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field SCSIRSTO 0x01
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}
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/*
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* SCSI Transfer Control 0 Register (pp. 3-13).
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* Controls the SCSI module data path.
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*/
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register SXFRCTL0 {
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address 0x001
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access_mode RW
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field DFON 0x80
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field DFPEXP 0x40
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field FAST20 0x20
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field CLRSTCNT 0x10
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field SPIOEN 0x08
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field SCAMEN 0x04
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field CLRCHN 0x02
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}
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/*
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* SCSI Transfer Control 1 Register (pp. 3-14,15).
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* Controls the SCSI module data path.
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*/
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register SXFRCTL1 {
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address 0x002
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access_mode RW
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field BITBUCKET 0x80
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field SWRAPEN 0x40
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field ENSPCHK 0x20
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mask STIMESEL 0x18
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field ENSTIMER 0x04
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field ACTNEGEN 0x02
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field STPWEN 0x01 /* Powered Termination */
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}
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/*
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* SCSI Control Signal Read Register (p. 3-15).
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* Reads the actual state of the SCSI bus pins
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*/
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register SCSISIGI {
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address 0x003
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access_mode RO
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field CDI 0x80
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field IOI 0x40
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field MSGI 0x20
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field ATNI 0x10
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field SELI 0x08
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field BSYI 0x04
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field REQI 0x02
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field ACKI 0x01
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/*
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* Possible phases in SCSISIGI
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*/
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mask PHASE_MASK CDI|IOI|MSGI
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mask P_DATAOUT 0x00
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mask P_DATAIN IOI
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mask P_DATAOUT_DT P_DATAOUT|MSGI
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mask P_DATAIN_DT P_DATAIN|MSGI
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mask P_COMMAND CDI
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mask P_MESGOUT CDI|MSGI
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mask P_STATUS CDI|IOI
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mask P_MESGIN CDI|IOI|MSGI
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}
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/*
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* SCSI Control Signal Write Register (p. 3-16).
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* Writing to this register modifies the control signals on the bus. Only
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* those signals that are allowed in the current mode (Initiator/Target) are
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* asserted.
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*/
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register SCSISIGO {
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address 0x003
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access_mode WO
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field CDO 0x80
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field IOO 0x40
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field MSGO 0x20
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field ATNO 0x10
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field SELO 0x08
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field BSYO 0x04
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field REQO 0x02
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field ACKO 0x01
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/*
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* Possible phases to write into SCSISIG0
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*/
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mask PHASE_MASK CDI|IOI|MSGI
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mask P_DATAOUT 0x00
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mask P_DATAIN IOI
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mask P_COMMAND CDI
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mask P_MESGOUT CDI|MSGI
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mask P_STATUS CDI|IOI
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mask P_MESGIN CDI|IOI|MSGI
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}
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/*
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* SCSI Rate Control (p. 3-17).
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* Contents of this register determine the Synchronous SCSI data transfer
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* rate and the maximum synchronous Req/Ack offset. An offset of 0 in the
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* SOFS (3:0) bits disables synchronous data transfers. Any offset value
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* greater than 0 enables synchronous transfers.
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*/
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register SCSIRATE {
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address 0x004
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access_mode RW
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field WIDEXFER 0x80 /* Wide transfer control */
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field ENABLE_CRC 0x40 /* CRC for D-Phases */
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field SINGLE_EDGE 0x10 /* Disable DT Transfers */
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mask SXFR 0x70 /* Sync transfer rate */
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mask SXFR_ULTRA2 0x0f /* Sync transfer rate */
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mask SOFS 0x0f /* Sync offset */
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}
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/*
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* SCSI ID (p. 3-18).
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* Contains the ID of the board and the current target on the
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* selected channel.
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*/
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register SCSIID {
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address 0x005
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access_mode RW
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mask TID 0xf0 /* Target ID mask */
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mask TWIN_TID 0x70
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field TWIN_CHNLB 0x80
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mask OID 0x0f /* Our ID mask */
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/*
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* SCSI Maximum Offset (p. 4-61 aic7890/91 Data Book)
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* The aic7890/91 allow an offset of up to 127 transfers in both wide
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* and narrow mode.
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*/
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alias SCSIOFFSET
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mask SOFS_ULTRA2 0x7f /* Sync offset U2 chips */
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}
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/*
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* SCSI Latched Data (p. 3-19).
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* Read/Write latches used to transfer data on the SCSI bus during
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* Automatic or Manual PIO mode. SCSIDATH can be used for the
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* upper byte of a 16bit wide asynchronouse data phase transfer.
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*/
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register SCSIDATL {
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address 0x006
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access_mode RW
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}
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register SCSIDATH {
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address 0x007
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access_mode RW
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}
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/*
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* SCSI Transfer Count (pp. 3-19,20)
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* These registers count down the number of bytes transferred
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* across the SCSI bus. The counter is decremented only once
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* the data has been safely transferred. SDONE in SSTAT0 is
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* set when STCNT goes to 0
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*/
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register STCNT {
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address 0x008
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size 3
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access_mode RW
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}
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/* ALT_MODE registers (Ultra2 and Ultra160 chips) */
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register SXFRCTL2 {
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address 0x013
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access_mode RW
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field AUTORSTDIS 0x10
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field CMDDMAEN 0x08
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mask ASYNC_SETUP 0x07
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}
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/* ALT_MODE register on Ultra160 chips */
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register OPTIONMODE {
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address 0x008
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access_mode RW
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field AUTORATEEN 0x80
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field AUTOACKEN 0x40
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field ATNMGMNTEN 0x20
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field BUSFREEREV 0x10
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field EXPPHASEDIS 0x08
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field SCSIDATL_IMGEN 0x04
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field AUTO_MSGOUT_DE 0x02
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field DIS_MSGIN_DUALEDGE 0x01
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mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE|DIS_MSGIN_DUALEDGE
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}
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/* ALT_MODE register on Ultra160 chips */
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register TARGCRCCNT {
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address 0x00a
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size 2
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access_mode RW
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}
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/*
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* Clear SCSI Interrupt 0 (p. 3-20)
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* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0.
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*/
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register CLRSINT0 {
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address 0x00b
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access_mode WO
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field CLRSELDO 0x40
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field CLRSELDI 0x20
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field CLRSELINGO 0x10
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field CLRSWRAP 0x08
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field CLRIOERR 0x08 /* Ultra2 Only */
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field CLRSPIORDY 0x02
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}
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/*
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* SCSI Status 0 (p. 3-21)
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* Contains one set of SCSI Interrupt codes
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* These are most likely of interest to the sequencer
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*/
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register SSTAT0 {
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address 0x00b
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access_mode RO
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field TARGET 0x80 /* Board acting as target */
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field SELDO 0x40 /* Selection Done */
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field SELDI 0x20 /* Board has been selected */
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field SELINGO 0x10 /* Selection In Progress */
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field SWRAP 0x08 /* 24bit counter wrap */
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field IOERR 0x08 /* LVD Tranceiver mode changed */
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field SDONE 0x04 /* STCNT = 0x000000 */
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field SPIORDY 0x02 /* SCSI PIO Ready */
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field DMADONE 0x01 /* DMA transfer completed */
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}
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/*
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* Clear SCSI Interrupt 1 (p. 3-23)
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* Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1.
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*/
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register CLRSINT1 {
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address 0x00c
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access_mode WO
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field CLRSELTIMEO 0x80
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field CLRATNO 0x40
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field CLRSCSIRSTI 0x20
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field CLRBUSFREE 0x08
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field CLRSCSIPERR 0x04
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field CLRPHASECHG 0x02
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field CLRREQINIT 0x01
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}
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/*
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* SCSI Status 1 (p. 3-24)
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*/
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register SSTAT1 {
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address 0x00c
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access_mode RO
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field SELTO 0x80
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field ATNTARG 0x40
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field SCSIRSTI 0x20
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field PHASEMIS 0x10
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field BUSFREE 0x08
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field SCSIPERR 0x04
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field PHASECHG 0x02
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field REQINIT 0x01
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}
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/*
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* SCSI Status 2 (pp. 3-25,26)
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*/
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register SSTAT2 {
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address 0x00d
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access_mode RO
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field OVERRUN 0x80
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field SHVALID 0x40 /* Shaddow Layer non-zero */
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field EXP_ACTIVE 0x10 /* SCSI Expander Active */
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field CRCVALERR 0x08 /* CRC doesn't match (U3 only) */
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field CRCENDERR 0x04 /* No terminal CRC packet (U3 only) */
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field CRCREQERR 0x02 /* Illegal CRC packet req (U3 only) */
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field DUAL_EDGE_ERR 0x01 /* Incorrect data phase (U3 only) */
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mask SFCNT 0x1f
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}
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|
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/*
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* SCSI Status 3 (p. 3-26)
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*/
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register SSTAT3 {
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address 0x00e
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access_mode RO
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mask SCSICNT 0xf0
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mask OFFCNT 0x0f
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mask U2OFFCNT 0x7f
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}
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/*
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* SCSI ID for the aic7890/91 chips
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*/
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register SCSIID_ULTRA2 {
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address 0x00f
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access_mode RW
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mask TID 0xf0 /* Target ID mask */
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mask OID 0x0f /* Our ID mask */
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}
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|
|
/*
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* SCSI Interrupt Mode 1 (p. 3-28)
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* Setting any bit will enable the corresponding function
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* in SIMODE0 to interrupt via the IRQ pin.
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*/
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register SIMODE0 {
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address 0x010
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access_mode RW
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field ENSELDO 0x40
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field ENSELDI 0x20
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field ENSELINGO 0x10
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field ENSWRAP 0x08
|
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field ENIOERR 0x08 /* LVD Tranceiver mode changes */
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field ENSDONE 0x04
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field ENSPIORDY 0x02
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field ENDMADONE 0x01
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}
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|
|
/*
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|
* SCSI Interrupt Mode 1 (pp. 3-28,29)
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|
* Setting any bit will enable the corresponding function
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* in SIMODE1 to interrupt via the IRQ pin.
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*/
|
|
register SIMODE1 {
|
|
address 0x011
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access_mode RW
|
|
field ENSELTIMO 0x80
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field ENATNTARG 0x40
|
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field ENSCSIRST 0x20
|
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field ENPHASEMIS 0x10
|
|
field ENBUSFREE 0x08
|
|
field ENSCSIPERR 0x04
|
|
field ENPHASECHG 0x02
|
|
field ENREQINIT 0x01
|
|
}
|
|
|
|
/*
|
|
* SCSI Data Bus (High) (p. 3-29)
|
|
* This register reads data on the SCSI Data bus directly.
|
|
*/
|
|
register SCSIBUSL {
|
|
address 0x012
|
|
access_mode RW
|
|
}
|
|
|
|
register SCSIBUSH {
|
|
address 0x013
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* SCSI/Host Address (p. 3-30)
|
|
* These registers hold the host address for the byte about to be
|
|
* transferred on the SCSI bus. They are counted up in the same
|
|
* manner as STCNT is counted down. SHADDR should always be used
|
|
* to determine the address of the last byte transferred since HADDR
|
|
* can be skewed by write ahead.
|
|
*/
|
|
register SHADDR {
|
|
address 0x014
|
|
size 4
|
|
access_mode RO
|
|
}
|
|
|
|
/*
|
|
* Selection Timeout Timer (p. 3-30)
|
|
*/
|
|
register SELTIMER {
|
|
address 0x018
|
|
access_mode RW
|
|
field STAGE6 0x20
|
|
field STAGE5 0x10
|
|
field STAGE4 0x08
|
|
field STAGE3 0x04
|
|
field STAGE2 0x02
|
|
field STAGE1 0x01
|
|
alias TARGIDIN
|
|
}
|
|
|
|
/*
|
|
* Selection/Reselection ID (p. 3-31)
|
|
* Upper four bits are the device id. The ONEBIT is set when the re/selecting
|
|
* device did not set its own ID.
|
|
*/
|
|
register SELID {
|
|
address 0x019
|
|
access_mode RW
|
|
mask SELID_MASK 0xf0
|
|
field ONEBIT 0x08
|
|
}
|
|
|
|
register SCAMCTL {
|
|
address 0x01a
|
|
access_mode RW
|
|
field ENSCAMSELO 0x80
|
|
field CLRSCAMSELID 0x40
|
|
field ALTSTIM 0x20
|
|
field DFLTTID 0x10
|
|
mask SCAMLVL 0x03
|
|
}
|
|
|
|
/*
|
|
* Target Mode Selecting in ID bitmask (aic7890/91/96/97)
|
|
*/
|
|
register TARGID {
|
|
address 0x01b
|
|
size 2
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* Serial Port I/O Cabability register (p. 4-95 aic7860 Data Book)
|
|
* Indicates if external logic has been attached to the chip to
|
|
* perform the tasks of accessing a serial eeprom, testing termination
|
|
* strength, and performing cable detection. On the aic7860, most of
|
|
* these features are handled on chip, but on the aic7855 an attached
|
|
* aic3800 does the grunt work.
|
|
*/
|
|
register SPIOCAP {
|
|
address 0x01b
|
|
access_mode RW
|
|
field SOFT1 0x80
|
|
field SOFT0 0x40
|
|
field SOFTCMDEN 0x20
|
|
field EXT_BRDCTL 0x10 /* External Board control */
|
|
field SEEPROM 0x08 /* External serial eeprom logic */
|
|
field EEPROM 0x04 /* Writable external BIOS ROM */
|
|
field ROM 0x02 /* Logic for accessing external ROM */
|
|
field SSPIOCPS 0x01 /* Termination and cable detection */
|
|
}
|
|
|
|
register BRDCTL {
|
|
address 0x01d
|
|
field BRDDAT7 0x80
|
|
field BRDDAT6 0x40
|
|
field BRDDAT5 0x20
|
|
field BRDSTB 0x10
|
|
field BRDCS 0x08
|
|
field BRDRW 0x04
|
|
field BRDCTL1 0x02
|
|
field BRDCTL0 0x01
|
|
/* 7890 Definitions */
|
|
field BRDDAT4 0x10
|
|
field BRDDAT3 0x08
|
|
field BRDDAT2 0x04
|
|
field BRDRW_ULTRA2 0x02
|
|
field BRDSTB_ULTRA2 0x01
|
|
}
|
|
|
|
/*
|
|
* Serial EEPROM Control (p. 4-92 in 7870 Databook)
|
|
* Controls the reading and writing of an external serial 1-bit
|
|
* EEPROM Device. In order to access the serial EEPROM, you must
|
|
* first set the SEEMS bit that generates a request to the memory
|
|
* port for access to the serial EEPROM device. When the memory
|
|
* port is not busy servicing another request, it reconfigures
|
|
* to allow access to the serial EEPROM. When this happens, SEERDY
|
|
* gets set high to verify that the memory port access has been
|
|
* granted.
|
|
*
|
|
* After successful arbitration for the memory port, the SEECS bit of
|
|
* the SEECTL register is connected to the chip select. The SEECK,
|
|
* SEEDO, and SEEDI are connected to the clock, data out, and data in
|
|
* lines respectively. The SEERDY bit of SEECTL is useful in that it
|
|
* gives us an 800 nsec timer. After a write to the SEECTL register,
|
|
* the SEERDY goes high 800 nsec later. The one exception to this is
|
|
* when we first request access to the memory port. The SEERDY goes
|
|
* high to signify that access has been granted and, for this case, has
|
|
* no implied timing.
|
|
*
|
|
* See 93cx6.c for detailed information on the protocol necessary to
|
|
* read the serial EEPROM.
|
|
*/
|
|
register SEECTL {
|
|
address 0x01e
|
|
field EXTARBACK 0x80
|
|
field EXTARBREQ 0x40
|
|
field SEEMS 0x20
|
|
field SEERDY 0x10
|
|
field SEECS 0x08
|
|
field SEECK 0x04
|
|
field SEEDO 0x02
|
|
field SEEDI 0x01
|
|
}
|
|
/*
|
|
* SCSI Block Control (p. 3-32)
|
|
* Controls Bus type and channel selection. In a twin channel configuration
|
|
* addresses 0x00-0x1e are gated to the appropriate channel based on this
|
|
* register. SELWIDE allows for the coexistence of 8bit and 16bit devices
|
|
* on a wide bus.
|
|
*/
|
|
register SBLKCTL {
|
|
address 0x01f
|
|
access_mode RW
|
|
field DIAGLEDEN 0x80 /* Aic78X0 only */
|
|
field DIAGLEDON 0x40 /* Aic78X0 only */
|
|
field AUTOFLUSHDIS 0x20
|
|
field SELBUSB 0x08
|
|
field ENAB40 0x08 /* LVD transceiver active */
|
|
field ENAB20 0x04 /* SE/HVD transceiver active */
|
|
field SELWIDE 0x02
|
|
field XCVR 0x01 /* External transceiver active */
|
|
}
|
|
|
|
/*
|
|
* Sequencer Control (p. 3-33)
|
|
* Error detection mode and speed configuration
|
|
*/
|
|
register SEQCTL {
|
|
address 0x060
|
|
access_mode RW
|
|
field PERRORDIS 0x80
|
|
field PAUSEDIS 0x40
|
|
field FAILDIS 0x20
|
|
field FASTMODE 0x10
|
|
field BRKADRINTEN 0x08
|
|
field STEP 0x04
|
|
field SEQRESET 0x02
|
|
field LOADRAM 0x01
|
|
}
|
|
|
|
/*
|
|
* Sequencer RAM Data (p. 3-34)
|
|
* Single byte window into the Scratch Ram area starting at the address
|
|
* specified by SEQADDR0 and SEQADDR1. To write a full word, simply write
|
|
* four bytes in succession. The SEQADDRs will increment after the most
|
|
* significant byte is written
|
|
*/
|
|
register SEQRAM {
|
|
address 0x061
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* Sequencer Address Registers (p. 3-35)
|
|
* Only the first bit of SEQADDR1 holds addressing information
|
|
*/
|
|
register SEQADDR0 {
|
|
address 0x062
|
|
access_mode RW
|
|
}
|
|
|
|
register SEQADDR1 {
|
|
address 0x063
|
|
access_mode RW
|
|
mask SEQADDR1_MASK 0x01
|
|
}
|
|
|
|
/*
|
|
* Accumulator
|
|
* We cheat by passing arguments in the Accumulator up to the kernel driver
|
|
*/
|
|
register ACCUM {
|
|
address 0x064
|
|
access_mode RW
|
|
accumulator
|
|
}
|
|
|
|
register SINDEX {
|
|
address 0x065
|
|
access_mode RW
|
|
sindex
|
|
}
|
|
|
|
register DINDEX {
|
|
address 0x066
|
|
access_mode RW
|
|
}
|
|
|
|
register ALLONES {
|
|
address 0x069
|
|
access_mode RO
|
|
allones
|
|
}
|
|
|
|
register ALLZEROS {
|
|
address 0x06a
|
|
access_mode RO
|
|
allzeros
|
|
}
|
|
|
|
register NONE {
|
|
address 0x06a
|
|
access_mode WO
|
|
none
|
|
}
|
|
|
|
register FLAGS {
|
|
address 0x06b
|
|
access_mode RO
|
|
field ZERO 0x02
|
|
field CARRY 0x01
|
|
}
|
|
|
|
register SINDIR {
|
|
address 0x06c
|
|
access_mode RO
|
|
}
|
|
|
|
register DINDIR {
|
|
address 0x06d
|
|
access_mode WO
|
|
}
|
|
|
|
register FUNCTION1 {
|
|
address 0x06e
|
|
access_mode RW
|
|
}
|
|
|
|
register STACK {
|
|
address 0x06f
|
|
access_mode RO
|
|
}
|
|
|
|
const STACK_SIZE 4
|
|
|
|
/*
|
|
* Board Control (p. 3-43)
|
|
*/
|
|
register BCTL {
|
|
address 0x084
|
|
access_mode RW
|
|
field ACE 0x08
|
|
field ENABLE 0x01
|
|
}
|
|
|
|
/*
|
|
* On the aic78X0 chips, Board Control is replaced by the DSCommand
|
|
* register (p. 4-64)
|
|
*/
|
|
register DSCOMMAND0 {
|
|
address 0x084
|
|
access_mode RW
|
|
field CACHETHEN 0x80 /* Cache Threshold enable */
|
|
field DPARCKEN 0x40 /* Data Parity Check Enable */
|
|
field MPARCKEN 0x20 /* Memory Parity Check Enable */
|
|
field EXTREQLCK 0x10 /* External Request Lock */
|
|
/* aic7890/91/96/97 only */
|
|
field INTSCBRAMSEL 0x08 /* Internal SCB RAM Select */
|
|
field RAMPS 0x04 /* External SCB RAM Present */
|
|
field USCBSIZE32 0x02 /* Use 32byte SCB Page Size */
|
|
field CIOPARCKEN 0x01 /* Internal bus parity error enable */
|
|
}
|
|
|
|
register DSCOMMAND1 {
|
|
address 0x085
|
|
access_mode RW
|
|
mask DSLATT 0xfc /* PCI latency timer (non-ultra2) */
|
|
field HADDLDSEL1 0x02 /* Host Address Load Select Bits */
|
|
field HADDLDSEL0 0x01
|
|
}
|
|
|
|
/*
|
|
* Bus On/Off Time (p. 3-44) aic7770 only
|
|
*/
|
|
register BUSTIME {
|
|
address 0x085
|
|
access_mode RW
|
|
mask BOFF 0xf0
|
|
mask BON 0x0f
|
|
}
|
|
|
|
/*
|
|
* Bus Speed (p. 3-45) aic7770 only
|
|
*/
|
|
register BUSSPD {
|
|
address 0x086
|
|
access_mode RW
|
|
mask DFTHRSH 0xc0
|
|
mask STBOFF 0x38
|
|
mask STBON 0x07
|
|
mask DFTHRSH_100 0xc0
|
|
mask DFTHRSH_75 0x80
|
|
}
|
|
|
|
/* aic7850/55/60/70/80/95 only */
|
|
register DSPCISTATUS {
|
|
address 0x086
|
|
mask DFTHRSH_100 0xc0
|
|
}
|
|
|
|
/* aic7890/91/96/97 only */
|
|
register HS_MAILBOX {
|
|
address 0x086
|
|
mask HOST_MAILBOX 0xF0
|
|
mask SEQ_MAILBOX 0x0F
|
|
mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */
|
|
}
|
|
|
|
const HOST_MAILBOX_SHIFT 4
|
|
const SEQ_MAILBOX_SHIFT 0
|
|
|
|
/*
|
|
* Host Control (p. 3-47) R/W
|
|
* Overall host control of the device.
|
|
*/
|
|
register HCNTRL {
|
|
address 0x087
|
|
access_mode RW
|
|
field POWRDN 0x40
|
|
field SWINT 0x10
|
|
field IRQMS 0x08
|
|
field PAUSE 0x04
|
|
field INTEN 0x02
|
|
field CHIPRST 0x01
|
|
field CHIPRSTACK 0x01
|
|
}
|
|
|
|
/*
|
|
* Host Address (p. 3-48)
|
|
* This register contains the address of the byte about
|
|
* to be transferred across the host bus.
|
|
*/
|
|
register HADDR {
|
|
address 0x088
|
|
size 4
|
|
access_mode RW
|
|
}
|
|
|
|
register HCNT {
|
|
address 0x08c
|
|
size 3
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* SCB Pointer (p. 3-49)
|
|
* Gate one of the SCBs into the SCBARRAY window.
|
|
*/
|
|
register SCBPTR {
|
|
address 0x090
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* Interrupt Status (p. 3-50)
|
|
* Status for system interrupts
|
|
*/
|
|
register INTSTAT {
|
|
address 0x091
|
|
access_mode RW
|
|
field BRKADRINT 0x08
|
|
field SCSIINT 0x04
|
|
field CMDCMPLT 0x02
|
|
field SEQINT 0x01
|
|
mask BAD_PHASE SEQINT /* unknown scsi bus phase */
|
|
mask SEND_REJECT 0x10|SEQINT /* sending a message reject */
|
|
mask PROTO_VIOLATION 0x20|SEQINT /* SCSI protocol violation */
|
|
mask NO_MATCH 0x30|SEQINT /* no cmd match for reconnect */
|
|
mask IGN_WIDE_RES 0x40|SEQINT /* Complex IGN Wide Res Msg */
|
|
mask PDATA_REINIT 0x50|SEQINT /*
|
|
* Returned to data phase
|
|
* that requires data
|
|
* transfer pointers to be
|
|
* recalculated from the
|
|
* transfer residual.
|
|
*/
|
|
mask HOST_MSG_LOOP 0x60|SEQINT /*
|
|
* The bus is ready for the
|
|
* host to perform another
|
|
* message transaction. This
|
|
* mechanism is used for things
|
|
* like sync/wide negotiation
|
|
* that require a kernel based
|
|
* message state engine.
|
|
*/
|
|
mask BAD_STATUS 0x70|SEQINT /* Bad status from target */
|
|
mask PERR_DETECTED 0x80|SEQINT /*
|
|
* Either the phase_lock
|
|
* or inb_next routine has
|
|
* noticed a parity error.
|
|
*/
|
|
mask DATA_OVERRUN 0x90|SEQINT /*
|
|
* Target attempted to write
|
|
* beyond the bounds of its
|
|
* command.
|
|
*/
|
|
mask MKMSG_FAILED 0xa0|SEQINT /*
|
|
* Target completed command
|
|
* without honoring our ATN
|
|
* request to issue a message.
|
|
*/
|
|
mask MISSED_BUSFREE 0xb0|SEQINT /*
|
|
* The sequencer never saw
|
|
* the bus go free after
|
|
* either a command complete
|
|
* or disconnect message.
|
|
*/
|
|
mask SCB_MISMATCH 0xc0|SEQINT /*
|
|
* Downloaded SCB's tag does
|
|
* not match the entry we
|
|
* intended to download.
|
|
*/
|
|
mask NO_FREE_SCB 0xd0|SEQINT /*
|
|
* get_free_or_disc_scb failed.
|
|
*/
|
|
mask OUT_OF_RANGE 0xe0|SEQINT
|
|
|
|
mask SEQINT_MASK 0xf0|SEQINT /* SEQINT Status Codes */
|
|
mask INT_PEND (BRKADRINT|SEQINT|SCSIINT|CMDCMPLT)
|
|
}
|
|
|
|
/*
|
|
* Hard Error (p. 3-53)
|
|
* Reporting of catastrophic errors. You usually cannot recover from
|
|
* these without a full board reset.
|
|
*/
|
|
register ERROR {
|
|
address 0x092
|
|
access_mode RO
|
|
field CIOPARERR 0x80 /* Ultra2 only */
|
|
field PCIERRSTAT 0x40 /* PCI only */
|
|
field MPARERR 0x20 /* PCI only */
|
|
field DPARERR 0x10 /* PCI only */
|
|
field SQPARERR 0x08
|
|
field ILLOPCODE 0x04
|
|
field ILLSADDR 0x02
|
|
field ILLHADDR 0x01
|
|
}
|
|
|
|
/*
|
|
* Clear Interrupt Status (p. 3-52)
|
|
*/
|
|
register CLRINT {
|
|
address 0x092
|
|
access_mode WO
|
|
field CLRPARERR 0x10 /* PCI only */
|
|
field CLRBRKADRINT 0x08
|
|
field CLRSCSIINT 0x04
|
|
field CLRCMDINT 0x02
|
|
field CLRSEQINT 0x01
|
|
}
|
|
|
|
register DFCNTRL {
|
|
address 0x093
|
|
access_mode RW
|
|
field PRELOADEN 0x80 /* aic7890 only */
|
|
field WIDEODD 0x40
|
|
field SCSIEN 0x20
|
|
field SDMAEN 0x10
|
|
field SDMAENACK 0x10
|
|
field HDMAEN 0x08
|
|
field HDMAENACK 0x08
|
|
field DIRECTION 0x04
|
|
field FIFOFLUSH 0x02
|
|
field FIFORESET 0x01
|
|
}
|
|
|
|
register DFSTATUS {
|
|
address 0x094
|
|
access_mode RO
|
|
field PRELOAD_AVAIL 0x80
|
|
field DFCACHETH 0x40
|
|
field FIFOQWDEMP 0x20
|
|
field MREQPEND 0x10
|
|
field HDONE 0x08
|
|
field DFTHRESH 0x04
|
|
field FIFOFULL 0x02
|
|
field FIFOEMP 0x01
|
|
}
|
|
|
|
register DFWADDR {
|
|
address 0x95
|
|
access_mode RW
|
|
}
|
|
|
|
register DFRADDR {
|
|
address 0x97
|
|
access_mode RW
|
|
}
|
|
|
|
register DFDAT {
|
|
address 0x099
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* SCB Auto Increment (p. 3-59)
|
|
* Byte offset into the SCB Array and an optional bit to allow auto
|
|
* incrementing of the address during download and upload operations
|
|
*/
|
|
register SCBCNT {
|
|
address 0x09a
|
|
access_mode RW
|
|
field SCBAUTO 0x80
|
|
mask SCBCNT_MASK 0x1f
|
|
}
|
|
|
|
/*
|
|
* Queue In FIFO (p. 3-60)
|
|
* Input queue for queued SCBs (commands that the seqencer has yet to start)
|
|
*/
|
|
register QINFIFO {
|
|
address 0x09b
|
|
access_mode RW
|
|
}
|
|
|
|
/*
|
|
* Queue In Count (p. 3-60)
|
|
* Number of queued SCBs
|
|
*/
|
|
register QINCNT {
|
|
address 0x09c
|
|
access_mode RO
|
|
}
|
|
|
|
/*
|
|
* Queue Out FIFO (p. 3-61)
|
|
* Queue of SCBs that have completed and await the host
|
|
*/
|
|
register QOUTFIFO {
|
|
address 0x09d
|
|
access_mode WO
|
|
}
|
|
|
|
register CRCCONTROL1 {
|
|
address 0x09d
|
|
access_mode RW
|
|
field CRCONSEEN 0x80
|
|
field CRCVALCHKEN 0x40
|
|
field CRCENDCHKEN 0x20
|
|
field CRCREQCHKEN 0x10
|
|
field TARGCRCENDEN 0x08
|
|
field TARGCRCCNTEN 0x04
|
|
}
|
|
|
|
|
|
/*
|
|
* Queue Out Count (p. 3-61)
|
|
* Number of queued SCBs in the Out FIFO
|
|
*/
|
|
register QOUTCNT {
|
|
address 0x09e
|
|
access_mode RO
|
|
}
|
|
|
|
register SCSIPHASE {
|
|
address 0x09e
|
|
access_mode RO
|
|
field STATUS_PHASE 0x20
|
|
field COMMAND_PHASE 0x10
|
|
field MSG_IN_PHASE 0x08
|
|
field MSG_OUT_PHASE 0x04
|
|
field DATA_IN_PHASE 0x02
|
|
field DATA_OUT_PHASE 0x01
|
|
mask DATA_PHASE_MASK 0x03
|
|
}
|
|
|
|
/*
|
|
* Special Function
|
|
*/
|
|
register SFUNCT {
|
|
address 0x09f
|
|
access_mode RW
|
|
field ALT_MODE 0x80
|
|
}
|
|
|
|
/*
|
|
* SCB Definition (p. 5-4)
|
|
*/
|
|
scb {
|
|
address 0x0a0
|
|
size 64
|
|
|
|
SCB_CDB_PTR {
|
|
size 4
|
|
alias SCB_RESIDUAL_DATACNT
|
|
alias SCB_CDB_STORE
|
|
}
|
|
SCB_RESIDUAL_SGPTR {
|
|
size 4
|
|
}
|
|
SCB_SCSI_STATUS {
|
|
size 1
|
|
}
|
|
SCB_TARGET_PHASES {
|
|
size 1
|
|
}
|
|
SCB_TARGET_DATA_DIR {
|
|
size 1
|
|
}
|
|
SCB_TARGET_ITAG {
|
|
size 1
|
|
}
|
|
SCB_DATAPTR {
|
|
size 4
|
|
}
|
|
SCB_DATACNT {
|
|
/*
|
|
* The last byte is really the high address bits for
|
|
* the data address.
|
|
*/
|
|
size 4
|
|
field SG_LAST_SEG 0x80 /* In the fourth byte */
|
|
mask SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */
|
|
}
|
|
SCB_SGPTR {
|
|
size 4
|
|
field SG_RESID_VALID 0x04 /* In the first byte */
|
|
field SG_FULL_RESID 0x02 /* In the first byte */
|
|
field SG_LIST_NULL 0x01 /* In the first byte */
|
|
}
|
|
SCB_CONTROL {
|
|
size 1
|
|
field TARGET_SCB 0x80
|
|
field STATUS_RCVD 0x80
|
|
field DISCENB 0x40
|
|
field TAG_ENB 0x20
|
|
field MK_MESSAGE 0x10
|
|
field ULTRAENB 0x08
|
|
field DISCONNECTED 0x04
|
|
mask SCB_TAG_TYPE 0x03
|
|
}
|
|
SCB_SCSIID {
|
|
size 1
|
|
field TWIN_CHNLB 0x80
|
|
mask TWIN_TID 0x70
|
|
mask TID 0xf0
|
|
mask OID 0x0f
|
|
}
|
|
SCB_LUN {
|
|
field SCB_XFERLEN_ODD 0x80
|
|
mask LID 0x3f
|
|
size 1
|
|
}
|
|
SCB_TAG {
|
|
size 1
|
|
}
|
|
SCB_CDB_LEN {
|
|
size 1
|
|
}
|
|
SCB_SCSIRATE {
|
|
size 1
|
|
}
|
|
SCB_SCSIOFFSET {
|
|
size 1
|
|
}
|
|
SCB_NEXT {
|
|
size 1
|
|
}
|
|
SCB_64_SPARE {
|
|
size 16
|
|
}
|
|
SCB_64_BTT {
|
|
size 16
|
|
}
|
|
}
|
|
|
|
const SCB_UPLOAD_SIZE 32
|
|
const SCB_DOWNLOAD_SIZE 32
|
|
const SCB_DOWNLOAD_SIZE_64 48
|
|
|
|
const SG_SIZEOF 0x08 /* sizeof(struct ahc_dma) */
|
|
|
|
/* --------------------- AHA-2840-only definitions -------------------- */
|
|
|
|
register SEECTL_2840 {
|
|
address 0x0c0
|
|
access_mode RW
|
|
field CS_2840 0x04
|
|
field CK_2840 0x02
|
|
field DO_2840 0x01
|
|
}
|
|
|
|
register STATUS_2840 {
|
|
address 0x0c1
|
|
access_mode RW
|
|
field EEPROM_TF 0x80
|
|
mask BIOS_SEL 0x60
|
|
mask ADSEL 0x1e
|
|
field DI_2840 0x01
|
|
}
|
|
|
|
/* --------------------- AIC-7870-only definitions -------------------- */
|
|
|
|
register CCHADDR {
|
|
address 0x0E0
|
|
size 8
|
|
}
|
|
|
|
register CCHCNT {
|
|
address 0x0E8
|
|
}
|
|
|
|
register CCSGRAM {
|
|
address 0x0E9
|
|
}
|
|
|
|
register CCSGADDR {
|
|
address 0x0EA
|
|
}
|
|
|
|
register CCSGCTL {
|
|
address 0x0EB
|
|
field CCSGDONE 0x80
|
|
field CCSGEN 0x08
|
|
field SG_FETCH_NEEDED 0x02 /* Bit used for software state */
|
|
field CCSGRESET 0x01
|
|
}
|
|
|
|
register CCSCBCNT {
|
|
address 0xEF
|
|
}
|
|
|
|
register CCSCBCTL {
|
|
address 0x0EE
|
|
field CCSCBDONE 0x80
|
|
field ARRDONE 0x40 /* SCB Array prefetch done */
|
|
field CCARREN 0x10
|
|
field CCSCBEN 0x08
|
|
field CCSCBDIR 0x04
|
|
field CCSCBRESET 0x01
|
|
}
|
|
|
|
register CCSCBADDR {
|
|
address 0x0ED
|
|
}
|
|
|
|
register CCSCBRAM {
|
|
address 0xEC
|
|
}
|
|
|
|
/*
|
|
* SCB bank address (7895/7896/97 only)
|
|
*/
|
|
register SCBBADDR {
|
|
address 0x0F0
|
|
access_mode RW
|
|
}
|
|
|
|
register CCSCBPTR {
|
|
address 0x0F1
|
|
}
|
|
|
|
register HNSCB_QOFF {
|
|
address 0x0F4
|
|
}
|
|
|
|
register SNSCB_QOFF {
|
|
address 0x0F6
|
|
}
|
|
|
|
register SDSCB_QOFF {
|
|
address 0x0F8
|
|
}
|
|
|
|
register QOFF_CTLSTA {
|
|
address 0x0FA
|
|
field SCB_AVAIL 0x40
|
|
field SNSCB_ROLLOVER 0x20
|
|
field SDSCB_ROLLOVER 0x10
|
|
mask SCB_QSIZE 0x07
|
|
mask SCB_QSIZE_256 0x06
|
|
}
|
|
|
|
register DFF_THRSH {
|
|
address 0x0FB
|
|
mask WR_DFTHRSH 0x70
|
|
mask RD_DFTHRSH 0x07
|
|
mask RD_DFTHRSH_MIN 0x00
|
|
mask RD_DFTHRSH_25 0x01
|
|
mask RD_DFTHRSH_50 0x02
|
|
mask RD_DFTHRSH_63 0x03
|
|
mask RD_DFTHRSH_75 0x04
|
|
mask RD_DFTHRSH_85 0x05
|
|
mask RD_DFTHRSH_90 0x06
|
|
mask RD_DFTHRSH_MAX 0x07
|
|
mask WR_DFTHRSH_MIN 0x00
|
|
mask WR_DFTHRSH_25 0x10
|
|
mask WR_DFTHRSH_50 0x20
|
|
mask WR_DFTHRSH_63 0x30
|
|
mask WR_DFTHRSH_75 0x40
|
|
mask WR_DFTHRSH_85 0x50
|
|
mask WR_DFTHRSH_90 0x60
|
|
mask WR_DFTHRSH_MAX 0x70
|
|
}
|
|
|
|
register SG_CACHE_PRE {
|
|
access_mode WO
|
|
address 0x0fc
|
|
mask SG_ADDR_MASK 0xf8
|
|
field LAST_SEG 0x02
|
|
field LAST_SEG_DONE 0x01
|
|
}
|
|
|
|
register SG_CACHE_SHADOW {
|
|
access_mode RO
|
|
address 0x0fc
|
|
mask SG_ADDR_MASK 0xf8
|
|
field LAST_SEG 0x02
|
|
field LAST_SEG_DONE 0x01
|
|
}
|
|
/* ---------------------- Scratch RAM Offsets ------------------------- */
|
|
/* These offsets are either to values that are initialized by the board's
|
|
* BIOS or are specified by the sequencer code.
|
|
*
|
|
* The host adapter card (at least the BIOS) uses 20-2f for SCSI
|
|
* device information, 32-33 and 5a-5f as well. As it turns out, the
|
|
* BIOS trashes 20-2f, writing the synchronous negotiation results
|
|
* on top of the BIOS values, so we re-use those for our per-target
|
|
* scratchspace (actually a value that can be copied directly into
|
|
* SCSIRATE). The kernel driver will enable synchronous negotiation
|
|
* for all targets that have a value other than 0 in the lower four
|
|
* bits of the target scratch space. This should work regardless of
|
|
* whether the bios has been installed.
|
|
*/
|
|
|
|
scratch_ram {
|
|
address 0x020
|
|
size 58
|
|
|
|
/*
|
|
* 1 byte per target starting at this address for configuration values
|
|
*/
|
|
BUSY_TARGETS {
|
|
alias TARG_SCSIRATE
|
|
size 16
|
|
}
|
|
/*
|
|
* Bit vector of targets that have ULTRA enabled as set by
|
|
* the BIOS. The Sequencer relies on a per-SCB field to
|
|
* control whether to enable Ultra transfers or not. During
|
|
* initialization, we read this field and reuse it for 2
|
|
* entries in the busy target table.
|
|
*/
|
|
ULTRA_ENB {
|
|
alias CMDSIZE_TABLE
|
|
size 2
|
|
}
|
|
/*
|
|
* Bit vector of targets that have disconnection disabled as set by
|
|
* the BIOS. The Sequencer relies in a per-SCB field to control the
|
|
* disconnect priveldge. During initialization, we read this field
|
|
* and reuse it for 2 entries in the busy target table.
|
|
*/
|
|
DISC_DSB {
|
|
size 2
|
|
}
|
|
CMDSIZE_TABLE_TAIL {
|
|
size 4
|
|
}
|
|
/*
|
|
* Partial transfer past cacheline end to be
|
|
* transferred using an extra S/G.
|
|
*/
|
|
MWI_RESIDUAL {
|
|
size 1
|
|
}
|
|
/*
|
|
* SCBID of the next SCB to be started by the controller.
|
|
*/
|
|
NEXT_QUEUED_SCB {
|
|
size 1
|
|
}
|
|
/*
|
|
* Single byte buffer used to designate the type or message
|
|
* to send to a target.
|
|
*/
|
|
MSG_OUT {
|
|
size 1
|
|
}
|
|
/* Parameters for DMA Logic */
|
|
DMAPARAMS {
|
|
size 1
|
|
field PRELOADEN 0x80
|
|
field WIDEODD 0x40
|
|
field SCSIEN 0x20
|
|
field SDMAEN 0x10
|
|
field SDMAENACK 0x10
|
|
field HDMAEN 0x08
|
|
field HDMAENACK 0x08
|
|
field DIRECTION 0x04 /* Set indicates PCI->SCSI */
|
|
field FIFOFLUSH 0x02
|
|
field FIFORESET 0x01
|
|
}
|
|
SEQ_FLAGS {
|
|
size 1
|
|
field NOT_IDENTIFIED 0x80
|
|
field NO_CDB_SENT 0x40
|
|
field TARGET_CMD_IS_TAGGED 0x40
|
|
field DPHASE 0x20
|
|
/* Target flags */
|
|
field TARG_CMD_PENDING 0x10
|
|
field CMDPHASE_PENDING 0x08
|
|
field DPHASE_PENDING 0x04
|
|
field SPHASE_PENDING 0x02
|
|
field NO_DISCONNECT 0x01
|
|
}
|
|
/*
|
|
* Temporary storage for the
|
|
* target/channel/lun of a
|
|
* reconnecting target
|
|
*/
|
|
SAVED_SCSIID {
|
|
size 1
|
|
}
|
|
SAVED_LUN {
|
|
size 1
|
|
}
|
|
/*
|
|
* The last bus phase as seen by the sequencer.
|
|
*/
|
|
LASTPHASE {
|
|
size 1
|
|
field CDI 0x80
|
|
field IOI 0x40
|
|
field MSGI 0x20
|
|
mask PHASE_MASK CDI|IOI|MSGI
|
|
mask P_DATAOUT 0x00
|
|
mask P_DATAIN IOI
|
|
mask P_COMMAND CDI
|
|
mask P_MESGOUT CDI|MSGI
|
|
mask P_STATUS CDI|IOI
|
|
mask P_MESGIN CDI|IOI|MSGI
|
|
mask P_BUSFREE 0x01
|
|
}
|
|
/*
|
|
* head of list of SCBs awaiting
|
|
* selection
|
|
*/
|
|
WAITING_SCBH {
|
|
size 1
|
|
}
|
|
/*
|
|
* head of list of SCBs that are
|
|
* disconnected. Used for SCB
|
|
* paging.
|
|
*/
|
|
DISCONNECTED_SCBH {
|
|
size 1
|
|
}
|
|
/*
|
|
* head of list of SCBs that are
|
|
* not in use. Used for SCB paging.
|
|
*/
|
|
FREE_SCBH {
|
|
size 1
|
|
}
|
|
/*
|
|
* head of list of SCBs that have
|
|
* completed but have not been
|
|
* put into the qoutfifo.
|
|
*/
|
|
COMPLETE_SCBH {
|
|
size 1
|
|
}
|
|
/*
|
|
* Address of the hardware scb array in the host.
|
|
*/
|
|
HSCB_ADDR {
|
|
size 4
|
|
}
|
|
/*
|
|
* Base address of our shared data with the kernel driver in host
|
|
* memory. This includes the qoutfifo and target mode
|
|
* incoming command queue.
|
|
*/
|
|
SHARED_DATA_ADDR {
|
|
size 4
|
|
}
|
|
KERNEL_QINPOS {
|
|
size 1
|
|
}
|
|
QINPOS {
|
|
size 1
|
|
}
|
|
QOUTPOS {
|
|
size 1
|
|
}
|
|
/*
|
|
* Kernel and sequencer offsets into the queue of
|
|
* incoming target mode command descriptors. The
|
|
* queue is full when the KERNEL_TQINPOS == TQINPOS.
|
|
*/
|
|
KERNEL_TQINPOS {
|
|
size 1
|
|
}
|
|
TQINPOS {
|
|
size 1
|
|
}
|
|
ARG_1 {
|
|
size 1
|
|
mask SEND_MSG 0x80
|
|
mask SEND_SENSE 0x40
|
|
mask SEND_REJ 0x20
|
|
mask MSGOUT_PHASEMIS 0x10
|
|
mask EXIT_MSG_LOOP 0x08
|
|
mask CONT_MSG_LOOP 0x04
|
|
mask CONT_TARG_SESSION 0x02
|
|
alias RETURN_1
|
|
}
|
|
ARG_2 {
|
|
size 1
|
|
alias RETURN_2
|
|
}
|
|
|
|
/*
|
|
* Snapshot of MSG_OUT taken after each message is sent.
|
|
*/
|
|
LAST_MSG {
|
|
size 1
|
|
alias TARG_IMMEDIATE_SCB
|
|
}
|
|
|
|
/*
|
|
* Sequences the kernel driver has okayed for us. This allows
|
|
* the driver to do things like prevent initiator or target
|
|
* operations.
|
|
*/
|
|
SCSISEQ_TEMPLATE {
|
|
size 1
|
|
field ENSELO 0x40
|
|
field ENSELI 0x20
|
|
field ENRSELI 0x10
|
|
field ENAUTOATNO 0x08
|
|
field ENAUTOATNI 0x04
|
|
field ENAUTOATNP 0x02
|
|
}
|
|
}
|
|
|
|
scratch_ram {
|
|
address 0x056
|
|
size 4
|
|
/*
|
|
* These scratch ram locations are initialized by the 274X BIOS.
|
|
* We reuse them after capturing the BIOS settings during
|
|
* initialization.
|
|
*/
|
|
|
|
/*
|
|
* The initiator specified tag for this target mode transaction.
|
|
*/
|
|
HA_274_BIOSGLOBAL {
|
|
size 1
|
|
field HA_274_EXTENDED_TRANS 0x01
|
|
alias INITIATOR_TAG
|
|
}
|
|
|
|
SEQ_FLAGS2 {
|
|
size 1
|
|
field SCB_DMA 0x01
|
|
field TARGET_MSG_PENDING 0x02
|
|
}
|
|
}
|
|
|
|
scratch_ram {
|
|
address 0x05a
|
|
size 6
|
|
/*
|
|
* These are reserved registers in the card's scratch ram on the 2742.
|
|
* The EISA configuraiton chip is mapped here. On Rev E. of the
|
|
* aic7770, the sequencer can use this area for scratch, but the
|
|
* host cannot directly access these registers. On later chips, this
|
|
* area can be read and written by both the host and the sequencer.
|
|
* Even on later chips, many of these locations are initialized by
|
|
* the BIOS.
|
|
*/
|
|
SCSICONF {
|
|
size 1
|
|
field TERM_ENB 0x80
|
|
field RESET_SCSI 0x40
|
|
field ENSPCHK 0x20
|
|
mask HSCSIID 0x07 /* our SCSI ID */
|
|
mask HWSCSIID 0x0f /* our SCSI ID if Wide Bus */
|
|
}
|
|
INTDEF {
|
|
address 0x05c
|
|
size 1
|
|
field EDGE_TRIG 0x80
|
|
mask VECTOR 0x0f
|
|
}
|
|
HOSTCONF {
|
|
address 0x05d
|
|
size 1
|
|
}
|
|
HA_274_BIOSCTRL {
|
|
address 0x05f
|
|
size 1
|
|
mask BIOSMODE 0x30
|
|
mask BIOSDISABLED 0x30
|
|
field CHANNEL_B_PRIMARY 0x08
|
|
}
|
|
}
|
|
|
|
scratch_ram {
|
|
address 0x070
|
|
size 16
|
|
|
|
/*
|
|
* Per target SCSI offset values for Ultra2 controllers.
|
|
*/
|
|
TARG_OFFSET {
|
|
size 16
|
|
}
|
|
}
|
|
|
|
const TID_SHIFT 4
|
|
const SCB_LIST_NULL 0xff
|
|
const TARGET_CMD_CMPLT 0xfe
|
|
|
|
const CCSGADDR_MAX 0x80
|
|
const CCSGRAM_MAXSEGS 16
|
|
|
|
/* WDTR Message values */
|
|
const BUS_8_BIT 0x00
|
|
const BUS_16_BIT 0x01
|
|
const BUS_32_BIT 0x02
|
|
|
|
/* Offset maximums */
|
|
const MAX_OFFSET_8BIT 0x0f
|
|
const MAX_OFFSET_16BIT 0x08
|
|
const MAX_OFFSET_ULTRA2 0x7f
|
|
const MAX_OFFSET 0x7f
|
|
const HOST_MSG 0xff
|
|
|
|
/* Target mode command processing constants */
|
|
const CMD_GROUP_CODE_SHIFT 0x05
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const STATUS_BUSY 0x08
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const STATUS_QUEUE_FULL 0x28
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const TARGET_DATA_IN 1
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/*
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* Downloaded (kernel inserted) constants
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*/
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/* Offsets into the SCBID array where different data is stored */
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const QOUTFIFO_OFFSET download
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const QINFIFO_OFFSET download
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const CACHESIZE_MASK download
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const INVERTED_CACHESIZE_MASK download
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const SG_PREFETCH_CNT download
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const SG_PREFETCH_ALIGN_MASK download
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const SG_PREFETCH_ADDR_MASK download
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