bf0477b215
- SMBus Controller
- SATA Controller
- HD Audio Controller
- Watchdog Controller
Thanks to Seth Heasley (seth.heasley@intel.com) for providing us code.
MFC after 3 days
220 lines
7.0 KiB
C
220 lines
7.0 KiB
C
/*-
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* Copyright (c) 2004 Texas A&M University
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* All rights reserved.
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*
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* Developer: Wm. Daryl Hawkins
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ICHWD_H_
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#define _ICHWD_H_
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struct ichwd_device {
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uint16_t device;
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char *desc;
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unsigned int version;
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};
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struct ichwd_softc {
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device_t device;
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device_t ich;
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int ich_version;
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int active;
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unsigned int timeout;
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int smi_rid;
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struct resource *smi_res;
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bus_space_tag_t smi_bst;
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bus_space_handle_t smi_bsh;
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int tco_rid;
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struct resource *tco_res;
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bus_space_tag_t tco_bst;
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bus_space_handle_t tco_bsh;
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int gcs_rid;
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struct resource *gcs_res;
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bus_space_tag_t gcs_bst;
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bus_space_handle_t gcs_bsh;
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eventhandler_tag ev_tag;
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};
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#define VENDORID_INTEL 0x8086
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#define DEVICEID_CPT0 0x1c40
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#define DEVICEID_CPT1 0x1c41
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#define DEVICEID_CPT2 0x1c42
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#define DEVICEID_CPT3 0x1c43
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#define DEVICEID_CPT4 0x1c44
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#define DEVICEID_CPT5 0x1c45
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#define DEVICEID_CPT6 0x1c46
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#define DEVICEID_CPT7 0x1c47
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#define DEVICEID_CPT8 0x1c48
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#define DEVICEID_CPT9 0x1c49
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#define DEVICEID_CPT10 0x1c4a
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#define DEVICEID_CPT11 0x1c4b
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#define DEVICEID_CPT12 0x1c4c
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#define DEVICEID_CPT13 0x1c4d
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#define DEVICEID_CPT14 0x1c4e
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#define DEVICEID_CPT15 0x1c4f
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#define DEVICEID_CPT16 0x1c50
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#define DEVICEID_CPT17 0x1c51
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#define DEVICEID_CPT18 0x1c52
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#define DEVICEID_CPT19 0x1c53
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#define DEVICEID_CPT20 0x1c54
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#define DEVICEID_CPT21 0x1c55
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#define DEVICEID_CPT22 0x1c56
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#define DEVICEID_CPT23 0x1c57
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#define DEVICEID_CPT24 0x1c58
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#define DEVICEID_CPT25 0x1c59
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#define DEVICEID_CPT26 0x1c5a
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#define DEVICEID_CPT27 0x1c5b
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#define DEVICEID_CPT28 0x1c5c
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#define DEVICEID_CPT29 0x1c5d
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#define DEVICEID_CPT30 0x1c5e
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#define DEVICEID_CPT31 0x1c5f
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#define DEVICEID_PATSBURG_LPC1 0x1d40
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#define DEVICEID_PATSBURG_LPC2 0x1d41
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#define DEVICEID_DH89XXCC_LPC 0x2310
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#define DEVICEID_82801AA 0x2410
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#define DEVICEID_82801AB 0x2420
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#define DEVICEID_82801BA 0x2440
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#define DEVICEID_82801BAM 0x244c
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#define DEVICEID_82801CA 0x2480
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#define DEVICEID_82801CAM 0x248c
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#define DEVICEID_82801DB 0x24c0
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#define DEVICEID_82801DBM 0x24cc
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#define DEVICEID_82801E 0x2450
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#define DEVICEID_82801EB 0x24dc
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#define DEVICEID_82801EBR 0x24d0
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#define DEVICEID_6300ESB 0x25a1
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#define DEVICEID_82801FBR 0x2640
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#define DEVICEID_ICH6M 0x2641
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#define DEVICEID_ICH6W 0x2642
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#define DEVICEID_63XXESB 0x2670
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#define DEVICEID_ICH7 0x27b8
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#define DEVICEID_ICH7DH 0x27b0
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#define DEVICEID_ICH7M 0x27b9
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#define DEVICEID_NM10 0x27bc
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#define DEVICEID_ICH7MDH 0x27bd
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#define DEVICEID_ICH8 0x2810
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#define DEVICEID_ICH8DH 0x2812
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#define DEVICEID_ICH8DO 0x2814
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#define DEVICEID_ICH8M 0x2815
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#define DEVICEID_ICH8ME 0x2811
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#define DEVICEID_ICH9 0x2918
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#define DEVICEID_ICH9DH 0x2912
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#define DEVICEID_ICH9DO 0x2914
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#define DEVICEID_ICH9M 0x2919
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#define DEVICEID_ICH9ME 0x2917
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#define DEVICEID_ICH9R 0x2916
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#define DEVICEID_ICH10 0x3a18
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#define DEVICEID_ICH10D 0x3a1a
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#define DEVICEID_ICH10DO 0x3a14
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#define DEVICEID_ICH10R 0x3a16
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#define DEVICEID_PCH 0x3b00
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#define DEVICEID_PCHM 0x3b01
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#define DEVICEID_P55 0x3b02
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#define DEVICEID_PM55 0x3b03
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#define DEVICEID_H55 0x3b06
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#define DEVICEID_QM57 0x3b07
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#define DEVICEID_H57 0x3b08
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#define DEVICEID_HM55 0x3b09
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#define DEVICEID_Q57 0x3b0a
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#define DEVICEID_HM57 0x3b0b
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#define DEVICEID_PCHMSFF 0x3b0d
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#define DEVICEID_QS57 0x3b0f
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#define DEVICEID_3400 0x3b12
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#define DEVICEID_3420 0x3b14
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#define DEVICEID_3450 0x3b16
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/* ICH LPC Interface Bridge Registers (ICH5 and older) */
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#define ICH_GEN_STA 0xd4
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#define ICH_GEN_STA_NO_REBOOT 0x02
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#define ICH_PMBASE 0x40 /* ACPI base address register */
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#define ICH_PMBASE_MASK 0x7f80 /* bits 7-15 */
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/* ICH Chipset Configuration Registers (ICH6 and newer) */
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#define ICH_RCBA 0xf0
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#define ICH_GCS_OFFSET 0x3410
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#define ICH_GCS_SIZE 0x4
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#define ICH_GCS_NO_REBOOT 0x20
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/* register names and locations (relative to PMBASE) */
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#define SMI_BASE 0x30 /* base address for SMI registers */
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#define SMI_LEN 0x08
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#define SMI_EN 0x00 /* SMI Control and Enable Register */
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#define SMI_STS 0x04 /* SMI Status Register */
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#define TCO_BASE 0x60 /* base address for TCO registers */
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#define TCO_LEN 0x20
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#define TCO_RLD 0x00 /* TCO Reload and Current Value */
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#define TCO_TMR1 0x01 /* TCO Timer Initial Value
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(ICH5 and older, 8 bits) */
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#define TCO_TMR2 0x12 /* TCO Timer Initial Value
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(ICH6 and newer, 16 bits) */
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#define TCO_DAT_IN 0x02 /* TCO Data In (DO NOT USE) */
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#define TCO_DAT_OUT 0x03 /* TCO Data Out (DO NOT USE) */
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#define TCO1_STS 0x04 /* TCO Status 1 */
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#define TCO2_STS 0x06 /* TCO Status 2 */
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#define TCO1_CNT 0x08 /* TCO Control 1 */
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#define TCO2_CNT 0x08 /* TCO Control 2 */
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/* bit definitions for SMI_EN and SMI_STS */
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#define SMI_TCO_EN 0x2000
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#define SMI_TCO_STS 0x2000
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/* timer value mask for TCO_RLD and TCO_TMR */
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#define TCO_TIMER_MASK 0x1f
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/* status bits for TCO1_STS */
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#define TCO_TIMEOUT 0x08 /* timed out */
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#define TCO_INT_STS 0x04 /* data out (DO NOT USE) */
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#define TCO_SMI_STS 0x02 /* data in (DO NOT USE) */
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/* status bits for TCO2_STS */
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#define TCO_BOOT_STS 0x04 /* failed to come out of reset */
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#define TCO_SECOND_TO_STS 0x02 /* ran down twice */
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/* control bits for TCO1_CNT */
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#define TCO_TMR_HALT 0x0800 /* clear to enable WDT */
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#define TCO_CNT_PRESERVE 0x0200 /* preserve these bits */
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/*
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* Masks for the TCO timer value field in TCO_RLD.
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* If the datasheets are to be believed, the minimum value actually varies
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* from chipset to chipset - 4 for ICH5 and 2 for all other chipsets.
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* I suspect this is a bug in the ICH5 datasheet and that the minimum is
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* uniformly 2, but I'd rather err on the side of caution.
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*/
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#define TCO_RLD_TMR_MIN 0x0004
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#define TCO_RLD1_TMR_MAX 0x003f
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#define TCO_RLD2_TMR_MAX 0x03ff
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/* approximate length in nanoseconds of one WDT tick (about 0.6 sec) */
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#define ICHWD_TICK 600000000
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#endif
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