333d0c6060
mostly meets the guidelines set by the Intel SDM: 1. We use XRSTOR and XSAVE from the same CPL using the same linear address for the store area 2. Contrary to the recommendations, we cannot zero the FPU save area for a new thread, since fork semantic requires the copy of the previous state. This advice seemingly contradicts to the advice from the item 6. 3. We do use XSAVEOPT in the context switch code only, and the area for XSAVEOPT already always contains the data saved by XSAVE. 4. We do not modify the save area between XRSTOR, when the area is loaded into FPU context, and XSAVE. We always spit the fpu context into save area and start emulation when directly writing into FPU context. 5. We do not use segmented addressing to access save area, or rather, always address it using %ds basing. 6. XSAVEOPT can be only executed in the area which was previously loaded with XRSTOR, since context switch code checks for FPU use by outgoing thread before saving, and thread which stopped emulation forcibly get context loaded with XRSTOR. 7. The PCB cannot be paged out while FPU emulation is turned off, since stack of the executing thread is never swapped out. The context switch code is patched to issue XSAVEOPT instead of XSAVE if supported. This approach eliminates one conditional in the context switch code, which would be needed otherwise. For user-visible machine context to have proper data, fpugetregs() checks for unsaved extension blocks and manually copies pristine FPU state into them, according to the description provided by CPUID leaf 0xd. MFC after: 1 month
121 lines
4.2 KiB
C
121 lines
4.2 KiB
C
/*-
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* Copyright (c) 1995 Bruce D. Evans.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the author nor the names of contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_MD_VAR_H_
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#define _MACHINE_MD_VAR_H_
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/*
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* Miscellaneous machine-dependent declarations.
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*/
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extern long Maxmem;
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extern u_int basemem;
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extern int busdma_swi_pending;
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extern u_int cpu_exthigh;
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extern u_int cpu_feature;
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extern u_int cpu_feature2;
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extern u_int amd_feature;
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extern u_int amd_feature2;
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extern u_int amd_pminfo;
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extern u_int via_feature_rng;
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extern u_int via_feature_xcrypt;
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extern u_int cpu_clflush_line_size;
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extern u_int cpu_fxsr;
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extern u_int cpu_high;
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extern u_int cpu_id;
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extern u_int cpu_max_ext_state_size;
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extern u_int cpu_mxcsr_mask;
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extern u_int cpu_procinfo;
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extern u_int cpu_procinfo2;
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extern char cpu_vendor[];
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extern u_int cpu_vendor_id;
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extern char ctx_switch_xsave[];
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extern char kstack[];
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extern char sigcode[];
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extern int szsigcode;
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extern uint64_t *vm_page_dump;
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extern int vm_page_dump_size;
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extern int workaround_erratum383;
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extern int _udatasel;
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extern int _ucodesel;
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extern int _ucode32sel;
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extern int _ufssel;
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extern int _ugssel;
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extern int use_xsave;
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extern uint64_t xsave_mask;
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typedef void alias_for_inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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struct pcb;
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struct savefpu;
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struct thread;
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struct reg;
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struct fpreg;
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struct dbreg;
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struct dumperinfo;
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void *alloc_fpusave(int flags);
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void amd64_syscall(struct thread *td, int traced);
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void busdma_swi(void);
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void cpu_setregs(void);
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void ctx_fpusave(void *);
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void doreti_iret(void) __asm(__STRING(doreti_iret));
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void doreti_iret_fault(void) __asm(__STRING(doreti_iret_fault));
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void ld_ds(void) __asm(__STRING(ld_ds));
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void ld_es(void) __asm(__STRING(ld_es));
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void ld_fs(void) __asm(__STRING(ld_fs));
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void ld_gs(void) __asm(__STRING(ld_gs));
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void ld_fsbase(void) __asm(__STRING(ld_fsbase));
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void ld_gsbase(void) __asm(__STRING(ld_gsbase));
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void ds_load_fault(void) __asm(__STRING(ds_load_fault));
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void es_load_fault(void) __asm(__STRING(es_load_fault));
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void fs_load_fault(void) __asm(__STRING(fs_load_fault));
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void gs_load_fault(void) __asm(__STRING(gs_load_fault));
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void fsbase_load_fault(void) __asm(__STRING(fsbase_load_fault));
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void gsbase_load_fault(void) __asm(__STRING(gsbase_load_fault));
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void dump_add_page(vm_paddr_t);
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void dump_drop_page(vm_paddr_t);
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void initializecpu(void);
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void initializecpucache(void);
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void fillw(int /*u_short*/ pat, void *base, size_t cnt);
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void fpstate_drop(struct thread *td);
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int is_physical_memory(vm_paddr_t addr);
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int isa_nmi(int cd);
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void pagecopy(void *from, void *to);
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void pagezero(void *addr);
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void setidt(int idx, alias_for_inthand_t *func, int typ, int dpl, int ist);
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int user_dbreg_trap(void);
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void minidumpsys(struct dumperinfo *);
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struct savefpu *get_pcb_user_save_td(struct thread *td);
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struct savefpu *get_pcb_user_save_pcb(struct pcb *pcb);
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struct pcb *get_pcb_td(struct thread *td);
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#endif /* !_MACHINE_MD_VAR_H_ */
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