331 lines
14 KiB
C
331 lines
14 KiB
C
/*
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* Copyright (c) 2017-2018 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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/****************************************************************************
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* Name: nvm_map.h
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*
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* Description: Everest NVRAM map
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*
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****************************************************************************/
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#ifndef NVM_MAP_H
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#define NVM_MAP_H
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#define CRC_MAGIC_VALUE 0xDEBB20E3
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#define CRC32_POLYNOMIAL 0xEDB88320
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#define _KB(x) (x*1024)
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#define _MB(x) (_KB(x)*1024)
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#define NVM_CRC_SIZE (sizeof(u32))
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enum nvm_sw_arbitrator {
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NVM_SW_ARB_HOST,
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NVM_SW_ARB_MCP,
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NVM_SW_ARB_UART,
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NVM_SW_ARB_RESERVED
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};
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/****************************************************************************
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* Boot Strap Region *
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****************************************************************************/
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struct legacy_bootstrap_region {
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u32 magic_value; /* a pattern not likely to occur randomly */
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#define NVM_MAGIC_VALUE 0x669955aa
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u32 sram_start_addr; /* where to locate LIM code (byte addr) */
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u32 code_len; /* boot code length (in dwords) */
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u32 code_start_addr; /* location of code on media (media byte addr) */
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u32 crc; /* 32-bit CRC */
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};
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/****************************************************************************
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* Directories Region *
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****************************************************************************/
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struct nvm_code_entry {
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u32 image_type; /* Image type */
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u32 nvm_start_addr; /* NVM address of the image */
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u32 len; /* Include CRC */
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u32 sram_start_addr; /* Where to load the image on the scratchpad */
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u32 sram_run_addr; /* Relevant in case of MIM only */
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};
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enum nvm_image_type {
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NVM_TYPE_TIM1 = 0x01,
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NVM_TYPE_TIM2 = 0x02,
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NVM_TYPE_MIM1 = 0x03,
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NVM_TYPE_MIM2 = 0x04,
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NVM_TYPE_MBA = 0x05,
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NVM_TYPE_MODULES_PN = 0x06,
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NVM_TYPE_VPD = 0x07,
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NVM_TYPE_MFW_TRACE1 = 0x08,
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NVM_TYPE_MFW_TRACE2 = 0x09,
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NVM_TYPE_NVM_CFG1 = 0x0a,
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NVM_TYPE_L2B = 0x0b,
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NVM_TYPE_DIR1 = 0x0c,
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NVM_TYPE_EAGLE_FW1 = 0x0d,
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NVM_TYPE_FALCON_FW1 = 0x0e,
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NVM_TYPE_PCIE_FW1 = 0x0f,
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NVM_TYPE_HW_SET = 0x10,
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NVM_TYPE_LIM = 0x11,
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NVM_TYPE_AVS_FW1 = 0x12,
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NVM_TYPE_DIR2 = 0x13,
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NVM_TYPE_CCM = 0x14,
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NVM_TYPE_EAGLE_FW2 = 0x15,
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NVM_TYPE_FALCON_FW2 = 0x16,
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NVM_TYPE_PCIE_FW2 = 0x17,
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NVM_TYPE_AVS_FW2 = 0x18,
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NVM_TYPE_INIT_HW = 0x19,
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NVM_TYPE_DEFAULT_CFG= 0x1a,
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NVM_TYPE_MDUMP = 0x1b,
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NVM_TYPE_NVM_META = 0x1c,
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NVM_TYPE_ISCSI_CFG = 0x1d,
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NVM_TYPE_FCOE_CFG = 0x1f,
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NVM_TYPE_ETH_PHY_FW1 = 0x20,
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NVM_TYPE_ETH_PHY_FW2 = 0x21,
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NVM_TYPE_BDN = 0x22,
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NVM_TYPE_8485X_PHY_FW = 0x23,
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NVM_TYPE_PUB_KEY = 0x24,
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NVM_TYPE_RECOVERY = 0x25,
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NVM_TYPE_PLDM = 0x26,
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NVM_TYPE_UPK1 = 0x27,
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NVM_TYPE_UPK2 = 0x28,
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NVM_TYPE_MASTER_KC = 0x29,
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NVM_TYPE_BACKUP_KC = 0x2a,
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NVM_TYPE_ROM_TEST = 0xf0,
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NVM_TYPE_MAX,
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};
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#ifdef DEFINE_IMAGE_TABLE
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struct image_map {
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char name[32];
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char option[32];
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u32 image_type;
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};
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struct image_map g_image_table[] = {
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{"TIM1", "-tim1", NVM_TYPE_TIM1},
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{"TIM2", "-tim2", NVM_TYPE_TIM2},
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{"MIM1", "-mim1", NVM_TYPE_MIM1},
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{"MIM2", "-mim2", NVM_TYPE_MIM2},
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{"MBA", "-mba", NVM_TYPE_MBA},
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{"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN},
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{"VPD", "-vpd", NVM_TYPE_VPD},
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{"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1},
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{"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2},
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{"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1},
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{"L2B", "-l2b", NVM_TYPE_L2B},
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{"DIR1", "-dir1", NVM_TYPE_DIR1},
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{"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1},
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{"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1},
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{"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1},
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{"HW_SET", "-hw_set", NVM_TYPE_HW_SET},
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{"LIM", "-lim", NVM_TYPE_LIM},
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{"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1},
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{"DIR2", "-dir2", NVM_TYPE_DIR2},
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{"CCM", "-ccm", NVM_TYPE_CCM},
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{"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2},
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{"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2},
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{"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2},
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{"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2},
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{"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW},
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{"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG},
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{"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP},
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{"META", "-meta", NVM_TYPE_NVM_META},
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{"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG},
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{"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG},
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{"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1},
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{"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2},
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{"BDN", "-bdn", NVM_TYPE_BDN},
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{"PK", "-pk", NVM_TYPE_PUB_KEY},
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{"RECOVERY", "-recovery",NVM_TYPE_RECOVERY},
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{"PLDM", "-pldm", NVM_TYPE_PLDM},
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{"UPK1", "-upk1", NVM_TYPE_UPK1},
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{"UPK2", "-upk2", NVM_TYPE_UPK2},
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{"ROMTEST", "-romtest" ,NVM_TYPE_ROM_TEST},
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{"MASTER_KC", "-kc" ,NVM_TYPE_MASTER_KC},
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{"BACKUP_KC", "" ,NVM_TYPE_BACKUP_KC}
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};
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#define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map))
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#endif /* #ifdef DEFINE_IMAGE_TABLE */
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#define MAX_NVM_DIR_ENTRIES 150
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/* Note: The has given 150 possible entries since anyway each file captures at least one page. */
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struct nvm_dir_meta {
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u32 dir_id;
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u32 nvm_dir_addr;
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u32 num_images;
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u32 next_mfw_to_run;
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};
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struct nvm_dir {
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s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */
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#define NVM_DIR_NEXT_MFW_MASK 0x00000001
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#define NVM_DIR_SEQ_MASK 0xfffffffe
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#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
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#define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \
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do { \
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_seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \
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} while (0)
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#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
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u32 num_images;
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u32 rsrv;
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struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */
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};
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#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE)
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struct nvm_vpd_image {
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u32 format_revision;
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#define VPD_IMAGE_VERSION 1
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/* This array length depends on the number of VPD fields */
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u8 vpd_data[1];
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};
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/****************************************************************************
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* NVRAM FULL MAP *
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****************************************************************************/
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#define DIR_ID_1 (0)
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#define DIR_ID_2 (1)
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#define MAX_DIR_IDS (2)
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#define MFW_BUNDLE_1 (0)
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#define MFW_BUNDLE_2 (1)
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#define MAX_MFW_BUNDLES (2)
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#define FLASH_PAGE_SIZE 0x1000
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#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */
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#define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200)) /* 1.2Mb - E4*/
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#define NG_ASIC_MIM_MAX_SIZE (_MB(2)) /* 2Mb - E5 */
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#define FPGA_MIM_MAX_SIZE (0x3E000) /* 250Kb */
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/* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page.
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* The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it.
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*/
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#define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE)
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#define LIM_OFFSET (NVM_OFFSET(lim_image))
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#define NVM_RSV_SIZE (44)
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#define GET_MIM_MAX_SIZE(is_asic, is_e4) ((!is_asic) ? FPGA_MIM_MAX_SIZE : ((is_e4) ? LEGACY_ASIC_MIM_MAX_SIZE : NG_ASIC_MIM_MAX_SIZE))
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#define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ?GET_MIM_MAX_SIZE(is_asic, is_e4) : 0))
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#define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4) (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(is_asic, is_e4)*2)
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#define EMUL_NVM_FIXED_AREA_SIZE() (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(0, 0))
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#define E5_MASTER_KEY_CHAIN_ADDR 0x1000
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#define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000)
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union nvm_dir_union {
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struct nvm_dir dir;
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u8 page[FLASH_PAGE_SIZE];
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};
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/* E4 Address E5 Address
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* +-------------------+ 0x000000 * +-------------------+ 0x000000
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* | Bootstrap: | * | |
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* | magic_number | * | |
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* | sram_start_addr | * | |
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* | code_len | * | |
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* | code_start_addr | * | |
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* | crc | * | |
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* +-------------------+ 0x000014 * | |
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* | rsrv | * | rsrv |
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* +-------------------+ 0x000040 * +-------------------+ 0x001000
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* | LIM | * | Master Key Chain |
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* +-------------------+ 0x002000 * +-------------------+ 0x002000
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* | Dir1 | * | Dir1 |
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* +-------------------+ 0x003000 * +-------------------+ 0x003000
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* | Dir2 | * | Dir2 |
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* +-------------------+ 0x004000 * +-------------------+ 0x004000
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* | MIM1 | * | MIM1 |
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* +-------------------+ 0x130000 * +-------------------+ 0x130000
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* | MIM2 | * | MIM2 |
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* +-------------------+ 0x25C000 * +-------------------+ 0x25C000
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* | Rest Images: | * | Rest Images: |
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* | TIM1/2 | * | TIM1/2 |
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* | MFW_TRACE1/2 | * | MFW_TRACE1/2 |
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* | Eagle/Falcon FW | * | Eagle/Falcon FW |
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* | PCIE/AVS FW | * | PCIE/AVS FW |
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* | MBA/CCM/L2B | * | MBA/CCM/L2B |
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* | VPD | * | VPD |
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* | optic_modules | * +-------------------+ Flash end - 0x1000
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* | ... | * | Backup Key Chain |
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* +-------------------+ 0x400000 * +-------------------+ Flash end
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*/
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struct nvm_image {
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/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
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/* NVM Offset (size) */
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struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */
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u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */
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u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */
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union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */
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/* MIM1_IMAGE 0x004000 (0x12c000) */
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/* MIM2_IMAGE 0x130000 (0x12c000) */
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/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/
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}; /* 0x134 */
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#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f))))
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struct hw_set_info {
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u32 reg_type;
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#define GRC_REG_TYPE 1
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#define PHY_REG_TYPE 2
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#define PCI_REG_TYPE 4
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u32 bank_num;
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u32 pf_num;
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u32 operation;
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#define READ_OP 1
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#define WRITE_OP 2
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#define RMW_SET_OP 3
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#define RMW_CLR_OP 4
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u32 reg_addr;
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u32 reg_data;
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u32 reset_type;
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#define POR_RESET_TYPE (1 << 0)
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#define HARD_RESET_TYPE (1 << 1)
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#define CORE_RESET_TYPE (1 << 2)
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#define MCP_RESET_TYPE (1 << 3)
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#define PERSET_ASSERT (1 << 4)
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#define PERSET_DEASSERT (1 << 5)
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};
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struct hw_set_image {
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u32 format_version;
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#define HW_SET_IMAGE_VERSION 1
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u32 no_hw_sets;
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/* This array length depends on the no_hw_sets */
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struct hw_set_info hw_sets[1];
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};
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#endif //NVM_MAP_H
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