bfc46c3238
is attached, by establishing a temporary mapping of the registers when necessary. This is a temporary measure to keep progress moving; in the long run we need better control over the order in which devices attach (better than "the order they appear in the fdt dts source").
89 lines
3.2 KiB
C
89 lines
3.2 KiB
C
/*-
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* Copyright (c) 2014 Steven Lawrance <stl@koffein.net>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef FSL_OCOTPREG_H
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#define FSL_OCOTPREG_H
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#define FSL_OCOTP_CTRL 0x000
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#define FSL_OCOTP_CTRL_SET 0x004
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#define FSL_OCOTP_CTRL_CLR 0x008
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#define FSL_OCOTP_CTRL_TOG 0x00C
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#define FSL_OCOTP_TIMING 0x010
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#define FSL_OCOTP_DATA 0x020
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#define FSL_OCOTP_READ_CTRL 0x030
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#define FSL_OCOTP_READ_FUSE_DATA 0x040
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#define FSL_OCOTP_SW_STICKY 0x050
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#define FSL_OCOTP_SCS 0x060
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#define FSL_OCOTP_SCS_SET 0x064
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#define FSL_OCOTP_SCS_CLR 0x068
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#define FSL_OCOTP_SCS_TOG 0x06C
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#define FSL_OCOTP_VERSION 0x090
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#define FSL_OCOTP_LOCK 0x400
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#define FSL_OCOTP_CFG0 0x410
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#define FSL_OCOTP_CFG1 0x420
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#define FSL_OCOTP_CFG2 0x430
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#define FSL_OCOTP_CFG3 0x440
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#define FSL_OCOTP_CFG3_SPEED_SHIFT 16
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#define FSL_OCOTP_CFG3_SPEED_MASK \
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(0x03 << FSL_OCOTP_CFG3_SPEED_SHIFT)
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#define FSL_OCOTP_CFG3_SPEED_792MHZ 0
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#define FSL_OCOTP_CFG3_SPEED_852MHZ 1
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#define FSL_OCOTP_CFG3_SPEED_996MHZ 2
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#define FSL_OCOTP_CFG3_SPEED_1200MHZ 3
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#define FSL_OCOTP_CFG4 0x450
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#define FSL_OCOTP_CFG5 0x460
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#define FSL_OCOTP_CFG6 0x470
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#define FSL_OCOTP_MEM0 0x480
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#define FSL_OCOTP_MEM1 0x490
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#define FSL_OCOTP_MEM2 0x4A0
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#define FSL_OCOTP_MEM3 0x4B0
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#define FSL_OCOTP_ANA0 0x4D0
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#define FSL_OCOTP_ANA1 0x4E0
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#define FSL_OCOTP_ANA2 0x4F0
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#define FSL_OCOTP_SRK0 0x580
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#define FSL_OCOTP_SRK1 0x590
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#define FSL_OCOTP_SRK2 0x5A0
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#define FSL_OCOTP_SRK3 0x5B0
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#define FSL_OCOTP_SRK4 0x5C0
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#define FSL_OCOTP_SRK5 0x5D0
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#define FSL_OCOTP_SRK6 0x5E0
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#define FSL_OCOTP_SRK7 0x5F0
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#define FSL_OCOTP_HSJC_RESP0 0x600
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#define FSL_OCOTP_HSJC_RESP1 0x610
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#define FSL_OCOTP_MAC0 0x620
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#define FSL_OCOTP_MAC1 0x630
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#define FSL_OCOTP_GP1 0x660
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#define FSL_OCOTP_GP2 0x670
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#define FSL_OCOTP_MISC_CONF 0x6D0
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#define FSL_OCOTP_FIELD_RETURN 0x6E0
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#define FSL_OCOTP_SRK_REVOKE 0x6F0
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#define FSL_OCOTP_LAST_REG FSL_OCOTP_SRK_REVOKE
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#endif
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