1563 lines
40 KiB
C
1563 lines
40 KiB
C
/*-
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* Copyright (c) 1999 Jason L. Wright (jason@thought.net)
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* Copyright (c) 2004 Pyun YongHyeon
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* Effort sponsored in part by the Defense Advanced Research Projects
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* Agency (DARPA) and Air Force Research Laboratory, Air Force
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* Materiel Command, USAF, under agreement number F30602-01-2-0537.
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*
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* from: OpenBSD: cs4231.c,v 1.21 2003/07/03 20:36:07 jason Exp
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*/
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/*
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* Driver for CS4231 based audio found in some sun4m systems (cs4231)
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* based on ideas from the S/Linux project and the NetBSD project.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/resource.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/openfirm.h>
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#include <machine/bus.h>
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#include <machine/ofw_machdep.h>
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#ifdef HAVE_KERNEL_OPTION_HEADERS
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#include "opt_snd.h"
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#endif
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/sbus/apcdmareg.h>
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#include <dev/sound/sbus/cs4231.h>
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#include <sparc64/sbus/sbusvar.h>
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#include <sparc64/ebus/ebusreg.h>
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#include "mixer_if.h"
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/*
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* The driver supports CS4231A audio chips found on Sbus/Ebus based
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* UltraSPARCs. Though, CS4231A says it supports full-duplex mode, I
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* doubt it due to the lack of independent sampling frequency register
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* for playback/capture.
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* Since I couldn't find any documentation for APCDMA programming
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* information, I guessed the usage of APCDMA from that of OpenBSD's
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* driver. The EBDMA information of PCIO can be obtained from
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* http://solutions.sun.com/embedded/databook/web/microprocessors/pcio.html
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* And CS4231A datasheet can also be obtained from
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* ftp://ftp.alsa-project.org/pub/manuals/cirrus/4231a.pdf
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*
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* Audio capture(recording) was not tested at all and may have bugs.
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* Sorry, I don't have microphone. Don't try to use full-duplex mode.
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* It wouldn't work.
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*/
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#define CS_TIMEOUT 90000
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#define CS4231_MIN_BUF_SZ (16*1024)
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#define CS4231_DEFAULT_BUF_SZ (32*1024)
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#define CS4231_MAX_BUF_SZ (64*1024)
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#define CS4231_MAX_BLK_SZ (8*1024)
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#define CS4231_MAX_APC_DMA_SZ (8*1024)
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#undef CS4231_DEBUG
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#ifdef CS4231_DEBUG
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#define DPRINTF(x) printf x
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#else
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#define DPRINTF(x)
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#endif
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#define CS4231_AUTO_CALIBRATION
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struct cs4231_softc;
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struct cs4231_channel {
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struct cs4231_softc *parent;
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struct pcm_channel *channel;
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struct snd_dbuf *buffer;
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u_int32_t format;
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u_int32_t speed;
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u_int32_t nextaddr;
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u_int32_t togo;
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int dir;
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int locked;
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};
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#define CS4231_RES_MEM_MAX 4
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#define CS4231_RES_IRQ_MAX 2
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struct cs4231_softc {
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struct device *sc_dev;
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int sc_rid[CS4231_RES_MEM_MAX];
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struct resource *sc_res[CS4231_RES_MEM_MAX];
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bus_space_handle_t sc_regh[CS4231_RES_MEM_MAX];
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bus_space_tag_t sc_regt[CS4231_RES_MEM_MAX];
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int sc_irqrid[CS4231_RES_IRQ_MAX];
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struct resource *sc_irqres[CS4231_RES_IRQ_MAX];
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void *sc_ih[CS4231_RES_IRQ_MAX];
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bus_dma_tag_t sc_dmat[CS4231_RES_IRQ_MAX];
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int sc_burst;
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u_int32_t sc_bufsz;
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struct cs4231_channel sc_pch;
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struct cs4231_channel sc_rch;
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int sc_enabled;
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int sc_nmres;
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int sc_nires;
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int sc_codecv;
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int sc_chipvid;
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int sc_flags;
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#define CS4231_SBUS 0x01
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#define CS4231_EBUS 0x02
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struct mtx *sc_lock;
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};
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struct mix_table {
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u_int32_t reg:8;
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u_int32_t bits:8;
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u_int32_t mute:8;
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u_int32_t shift:4;
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u_int32_t neg:1;
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u_int32_t avail:1;
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u_int32_t recdev:1;
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};
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static int cs4231_bus_probe(device_t);
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static int cs4231_sbus_attach(device_t);
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static int cs4231_ebus_attach(device_t);
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static int cs4231_attach_common(struct cs4231_softc *);
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static int cs4231_bus_detach(device_t);
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static int cs4231_bus_suspend(device_t);
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static int cs4231_bus_resume(device_t);
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static void cs4231_getversion(struct cs4231_softc *);
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static void cs4231_free_resource(struct cs4231_softc *);
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static void cs4231_ebdma_reset(struct cs4231_softc *);
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static void cs4231_power_reset(struct cs4231_softc *, int);
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static int cs4231_enable(struct cs4231_softc *, int);
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static void cs4231_disable(struct cs4231_softc *);
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static void cs4231_write(struct cs4231_softc *, u_int8_t, u_int8_t);
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static u_int8_t cs4231_read(struct cs4231_softc *, u_int8_t);
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static void cs4231_sbus_intr(void *);
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static void cs4231_ebus_pintr(void *arg);
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static void cs4231_ebus_cintr(void *arg);
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static int cs4231_mixer_init(struct snd_mixer *);
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static void cs4231_mixer_set_value(struct cs4231_softc *,
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const struct mix_table *, u_int8_t);
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static int cs4231_mixer_set(struct snd_mixer *, u_int32_t, u_int32_t,
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u_int32_t);
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static u_int32_t cs4231_mixer_setrecsrc(struct snd_mixer *, u_int32_t);
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static void *cs4231_chan_init(kobj_t, void *, struct snd_dbuf *,
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struct pcm_channel *, int);
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static int cs4231_chan_setformat(kobj_t, void *, u_int32_t);
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static u_int32_t cs4231_chan_setspeed(kobj_t, void *, u_int32_t);
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static void cs4231_chan_fs(struct cs4231_softc *, int, u_int8_t);
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static u_int32_t cs4231_chan_setblocksize(kobj_t, void *, u_int32_t);
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static int cs4231_chan_trigger(kobj_t, void *, int);
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static u_int32_t cs4231_chan_getptr(kobj_t, void *);
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static struct pcmchan_caps *
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cs4231_chan_getcaps(kobj_t, void *);
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static void cs4231_trigger(struct cs4231_channel *);
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static void cs4231_apcdma_trigger(struct cs4231_softc *,
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struct cs4231_channel *);
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static void cs4231_ebdma_trigger(struct cs4231_softc *,
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struct cs4231_channel *);
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static void cs4231_halt(struct cs4231_channel *);
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#define CS4231_LOCK(sc) snd_mtxlock(sc->sc_lock)
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#define CS4231_UNLOCK(sc) snd_mtxunlock(sc->sc_lock)
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#define CS4231_LOCK_ASSERT(sc) snd_mtxassert(sc->sc_lock)
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#define CS_WRITE(sc,r,v) \
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bus_space_write_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2, (v))
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#define CS_READ(sc,r) \
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bus_space_read_1((sc)->sc_regt[0], (sc)->sc_regh[0], (r) << 2)
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#define APC_WRITE(sc,r,v) \
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bus_space_write_4(sc->sc_regt[0], sc->sc_regh[0], r, v)
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#define APC_READ(sc,r) \
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bus_space_read_4(sc->sc_regt[0], sc->sc_regh[0], r)
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#define EBDMA_P_WRITE(sc,r,v) \
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bus_space_write_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r), (v))
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#define EBDMA_P_READ(sc,r) \
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bus_space_read_4((sc)->sc_regt[1], (sc)->sc_regh[1], (r))
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#define EBDMA_C_WRITE(sc,r,v) \
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bus_space_write_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r), (v))
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#define EBDMA_C_READ(sc,r) \
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bus_space_read_4((sc)->sc_regt[2], (sc)->sc_regh[2], (r))
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#define AUXIO_CODEC 0x00
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#define AUXIO_WRITE(sc,r,v) \
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bus_space_write_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r), (v))
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#define AUXIO_READ(sc,r) \
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bus_space_read_4((sc)->sc_regt[3], (sc)->sc_regh[3], (r))
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#define CODEC_WARM_RESET 0
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#define CODEC_COLD_RESET 1
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/* SBus */
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static device_method_t cs4231_sbus_methods[] = {
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DEVMETHOD(device_probe, cs4231_bus_probe),
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DEVMETHOD(device_attach, cs4231_sbus_attach),
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DEVMETHOD(device_detach, cs4231_bus_detach),
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DEVMETHOD(device_suspend, cs4231_bus_suspend),
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DEVMETHOD(device_resume, cs4231_bus_resume),
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{0, 0}
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};
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static driver_t cs4231_sbus_driver = {
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"pcm",
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cs4231_sbus_methods,
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PCM_SOFTC_SIZE
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};
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DRIVER_MODULE(snd_audiocs, sbus, cs4231_sbus_driver, pcm_devclass, 0, 0);
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/* EBus */
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static device_method_t cs4231_ebus_methods[] = {
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DEVMETHOD(device_probe, cs4231_bus_probe),
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DEVMETHOD(device_attach, cs4231_ebus_attach),
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DEVMETHOD(device_detach, cs4231_bus_detach),
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DEVMETHOD(device_suspend, cs4231_bus_suspend),
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DEVMETHOD(device_resume, cs4231_bus_resume),
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{0, 0}
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};
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static driver_t cs4231_ebus_driver = {
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"pcm",
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cs4231_ebus_methods,
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PCM_SOFTC_SIZE
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};
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DRIVER_MODULE(snd_audiocs, ebus, cs4231_ebus_driver, pcm_devclass, 0, 0);
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MODULE_DEPEND(snd_audiocs, sound, SOUND_MINVER, SOUND_PREFVER, SOUND_MAXVER);
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MODULE_VERSION(snd_audiocs, 1);
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static u_int32_t cs4231_fmt[] = {
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SND_FORMAT(AFMT_U8, 1, 0),
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SND_FORMAT(AFMT_U8, 2, 0),
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SND_FORMAT(AFMT_MU_LAW, 1, 0),
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SND_FORMAT(AFMT_MU_LAW, 2, 0),
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SND_FORMAT(AFMT_A_LAW, 1, 0),
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SND_FORMAT(AFMT_A_LAW, 2, 0),
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SND_FORMAT(AFMT_IMA_ADPCM, 1, 0),
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SND_FORMAT(AFMT_IMA_ADPCM, 2, 0),
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SND_FORMAT(AFMT_S16_LE, 1, 0),
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SND_FORMAT(AFMT_S16_LE, 2, 0),
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SND_FORMAT(AFMT_S16_BE, 1, 0),
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SND_FORMAT(AFMT_S16_BE, 2, 0),
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0
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};
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static struct pcmchan_caps cs4231_caps = {5510, 48000, cs4231_fmt, 0};
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/*
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* sound(4) channel interface
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*/
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static kobj_method_t cs4231_chan_methods[] = {
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KOBJMETHOD(channel_init, cs4231_chan_init),
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KOBJMETHOD(channel_setformat, cs4231_chan_setformat),
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KOBJMETHOD(channel_setspeed, cs4231_chan_setspeed),
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KOBJMETHOD(channel_setblocksize, cs4231_chan_setblocksize),
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KOBJMETHOD(channel_trigger, cs4231_chan_trigger),
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KOBJMETHOD(channel_getptr, cs4231_chan_getptr),
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KOBJMETHOD(channel_getcaps, cs4231_chan_getcaps),
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KOBJMETHOD_END
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};
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CHANNEL_DECLARE(cs4231_chan);
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/*
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* sound(4) mixer interface
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*/
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static kobj_method_t cs4231_mixer_methods[] = {
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KOBJMETHOD(mixer_init, cs4231_mixer_init),
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KOBJMETHOD(mixer_set, cs4231_mixer_set),
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KOBJMETHOD(mixer_setrecsrc, cs4231_mixer_setrecsrc),
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KOBJMETHOD_END
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};
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MIXER_DECLARE(cs4231_mixer);
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static int
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cs4231_bus_probe(device_t dev)
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{
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const char *compat, *name;
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compat = ofw_bus_get_compat(dev);
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name = ofw_bus_get_name(dev);
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if (strcmp("SUNW,CS4231", name) == 0 ||
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(compat != NULL && strcmp("SUNW,CS4231", compat) == 0)) {
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device_set_desc(dev, "Sun Audiocs");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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cs4231_sbus_attach(device_t dev)
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{
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struct cs4231_softc *sc;
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int burst;
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sc = malloc(sizeof(*sc), M_DEVBUF, M_WAITOK | M_ZERO);
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sc->sc_dev = dev;
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/*
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* XXX
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* No public documentation exists on programming burst size of APCDMA.
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*/
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burst = sbus_get_burstsz(sc->sc_dev);
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if ((burst & SBUS_BURST_64))
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sc->sc_burst = 64;
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else if ((burst & SBUS_BURST_32))
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sc->sc_burst = 32;
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else if ((burst & SBUS_BURST_16))
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sc->sc_burst = 16;
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else
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sc->sc_burst = 0;
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sc->sc_flags = CS4231_SBUS;
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sc->sc_nmres = 1;
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sc->sc_nires = 1;
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return cs4231_attach_common(sc);
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}
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static int
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cs4231_ebus_attach(device_t dev)
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{
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struct cs4231_softc *sc;
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sc = malloc(sizeof(struct cs4231_softc), M_DEVBUF, M_NOWAIT | M_ZERO);
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if (sc == NULL) {
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device_printf(dev, "cannot allocate softc\n");
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return (ENOMEM);
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}
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sc->sc_dev = dev;
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sc->sc_burst = EBDCSR_BURST_1;
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sc->sc_nmres = CS4231_RES_MEM_MAX;
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sc->sc_nires = CS4231_RES_IRQ_MAX;
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sc->sc_flags = CS4231_EBUS;
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return cs4231_attach_common(sc);
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}
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static int
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cs4231_attach_common(struct cs4231_softc *sc)
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{
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char status[SND_STATUSLEN];
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driver_intr_t *ihandler;
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int i;
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sc->sc_lock = snd_mtxcreate(device_get_nameunit(sc->sc_dev),
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"snd_cs4231 softc");
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for (i = 0; i < sc->sc_nmres; i++) {
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sc->sc_rid[i] = i;
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if ((sc->sc_res[i] = bus_alloc_resource_any(sc->sc_dev,
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SYS_RES_MEMORY, &sc->sc_rid[i], RF_ACTIVE)) == NULL) {
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device_printf(sc->sc_dev,
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"cannot map register %d\n", i);
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goto fail;
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}
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sc->sc_regt[i] = rman_get_bustag(sc->sc_res[i]);
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sc->sc_regh[i] = rman_get_bushandle(sc->sc_res[i]);
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}
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for (i = 0; i < sc->sc_nires; i++) {
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sc->sc_irqrid[i] = i;
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if ((sc->sc_irqres[i] = bus_alloc_resource_any(sc->sc_dev,
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SYS_RES_IRQ, &sc->sc_irqrid[i], RF_SHAREABLE | RF_ACTIVE))
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== NULL) {
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if ((sc->sc_flags & CS4231_SBUS) != 0)
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device_printf(sc->sc_dev,
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"cannot allocate interrupt\n");
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else
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device_printf(sc->sc_dev, "cannot allocate %s "
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"interrupt\n", i == 0 ? "capture" :
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"playback");
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goto fail;
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}
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}
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ihandler = cs4231_sbus_intr;
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for (i = 0; i < sc->sc_nires; i++) {
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if ((sc->sc_flags & CS4231_EBUS) != 0) {
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if (i == 0)
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ihandler = cs4231_ebus_cintr;
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else
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ihandler = cs4231_ebus_pintr;
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}
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if (snd_setup_intr(sc->sc_dev, sc->sc_irqres[i], INTR_MPSAFE,
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ihandler, sc, &sc->sc_ih[i])) {
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if ((sc->sc_flags & CS4231_SBUS) != 0)
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device_printf(sc->sc_dev,
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"cannot set up interrupt\n");
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else
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device_printf(sc->sc_dev, "cannot set up %s "
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" interrupt\n", i == 0 ? "capture" :
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"playback");
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goto fail;
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}
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}
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sc->sc_bufsz = pcm_getbuffersize(sc->sc_dev, CS4231_MIN_BUF_SZ,
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CS4231_DEFAULT_BUF_SZ, CS4231_MAX_BUF_SZ);
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for (i = 0; i < sc->sc_nires; i++) {
|
|
if (bus_dma_tag_create(
|
|
bus_get_dma_tag(sc->sc_dev),/* parent */
|
|
64, 0, /* alignment, boundary */
|
|
BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
|
|
BUS_SPACE_MAXADDR, /* highaddr */
|
|
NULL, NULL, /* filtfunc, filtfuncarg */
|
|
sc->sc_bufsz, /* maxsize */
|
|
1, /* nsegments */
|
|
sc->sc_bufsz, /* maxsegsz */
|
|
BUS_DMA_ALLOCNOW, /* flags */
|
|
NULL, /* lockfunc */
|
|
NULL, /* lockfuncarg */
|
|
&sc->sc_dmat[i])) {
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0)
|
|
device_printf(sc->sc_dev,
|
|
"cannot allocate DMA tag\n");
|
|
else
|
|
device_printf(sc->sc_dev, "cannot allocate %s "
|
|
"DMA tag\n", i == 0 ? "capture" :
|
|
"playback");
|
|
goto fail;
|
|
}
|
|
}
|
|
cs4231_enable(sc, CODEC_WARM_RESET);
|
|
cs4231_getversion(sc);
|
|
if (mixer_init(sc->sc_dev, &cs4231_mixer_class, sc) != 0)
|
|
goto fail;
|
|
if (pcm_register(sc->sc_dev, sc, 1, 1)) {
|
|
device_printf(sc->sc_dev, "cannot register to pcm\n");
|
|
goto fail;
|
|
}
|
|
if (pcm_addchan(sc->sc_dev, PCMDIR_REC, &cs4231_chan_class, sc) != 0)
|
|
goto chan_fail;
|
|
if (pcm_addchan(sc->sc_dev, PCMDIR_PLAY, &cs4231_chan_class, sc) != 0)
|
|
goto chan_fail;
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0)
|
|
snprintf(status, SND_STATUSLEN, "at mem 0x%lx irq %ld bufsz %u",
|
|
rman_get_start(sc->sc_res[0]),
|
|
rman_get_start(sc->sc_irqres[0]), sc->sc_bufsz);
|
|
else
|
|
snprintf(status, SND_STATUSLEN, "at io 0x%lx 0x%lx 0x%lx 0x%lx "
|
|
"irq %ld %ld bufsz %u", rman_get_start(sc->sc_res[0]),
|
|
rman_get_start(sc->sc_res[1]),
|
|
rman_get_start(sc->sc_res[2]),
|
|
rman_get_start(sc->sc_res[3]),
|
|
rman_get_start(sc->sc_irqres[0]),
|
|
rman_get_start(sc->sc_irqres[1]), sc->sc_bufsz);
|
|
pcm_setstatus(sc->sc_dev, status);
|
|
return (0);
|
|
|
|
chan_fail:
|
|
pcm_unregister(sc->sc_dev);
|
|
fail:
|
|
cs4231_free_resource(sc);
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
cs4231_bus_detach(device_t dev)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *pch, *rch;
|
|
int error;
|
|
|
|
sc = pcm_getdevinfo(dev);
|
|
CS4231_LOCK(sc);
|
|
pch = &sc->sc_pch;
|
|
rch = &sc->sc_pch;
|
|
if (pch->locked || rch->locked) {
|
|
CS4231_UNLOCK(sc);
|
|
return (EBUSY);
|
|
}
|
|
/*
|
|
* Since EBDMA requires valid DMA buffer to drain its FIFO, we need
|
|
* real DMA buffer for draining.
|
|
*/
|
|
if ((sc->sc_flags & CS4231_EBUS) != 0)
|
|
cs4231_ebdma_reset(sc);
|
|
CS4231_UNLOCK(sc);
|
|
error = pcm_unregister(dev);
|
|
if (error)
|
|
return (error);
|
|
cs4231_free_resource(sc);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
cs4231_bus_suspend(device_t dev)
|
|
{
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
cs4231_bus_resume(device_t dev)
|
|
{
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static void
|
|
cs4231_getversion(struct cs4231_softc *sc)
|
|
{
|
|
u_int8_t v;
|
|
|
|
v = cs4231_read(sc, CS_MISC_INFO);
|
|
sc->sc_codecv = v & CS_CODEC_ID_MASK;
|
|
v = cs4231_read(sc, CS_VERSION_ID);
|
|
v &= (CS_VERSION_NUMBER | CS_VERSION_CHIPID);
|
|
sc->sc_chipvid = v;
|
|
switch(v) {
|
|
case 0x80:
|
|
device_printf(sc->sc_dev, "<CS4231 Codec Id. %d>\n",
|
|
sc->sc_codecv);
|
|
break;
|
|
case 0xa0:
|
|
device_printf(sc->sc_dev, "<CS4231A Codec Id. %d>\n",
|
|
sc->sc_codecv);
|
|
break;
|
|
case 0x82:
|
|
device_printf(sc->sc_dev, "<CS4232 Codec Id. %d>\n",
|
|
sc->sc_codecv);
|
|
break;
|
|
default:
|
|
device_printf(sc->sc_dev,
|
|
"<Unknown 0x%x Codec Id. %d\n", v, sc->sc_codecv);
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void
|
|
cs4231_ebdma_reset(struct cs4231_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
/* playback */
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR,
|
|
EBDMA_P_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN));
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
|
|
for (i = CS_TIMEOUT;
|
|
i && EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--)
|
|
DELAY(1);
|
|
if (i == 0)
|
|
device_printf(sc->sc_dev,
|
|
"timeout waiting for playback DMA reset\n");
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
|
|
/* capture */
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR,
|
|
EBDMA_C_READ(sc, EBDMA_DCSR) & ~(EBDCSR_INTEN | EBDCSR_NEXTEN));
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
|
|
for (i = CS_TIMEOUT;
|
|
i && EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_DRAIN; i--)
|
|
DELAY(1);
|
|
if (i == 0)
|
|
device_printf(sc->sc_dev,
|
|
"timeout waiting for capture DMA reset\n");
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
|
|
}
|
|
|
|
static void
|
|
cs4231_power_reset(struct cs4231_softc *sc, int how)
|
|
{
|
|
u_int32_t v;
|
|
int i;
|
|
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0) {
|
|
APC_WRITE(sc, APC_CSR, APC_CSR_RESET);
|
|
DELAY(10);
|
|
APC_WRITE(sc, APC_CSR, 0);
|
|
DELAY(10);
|
|
APC_WRITE(sc,
|
|
APC_CSR, APC_READ(sc, APC_CSR) | APC_CSR_CODEC_RESET);
|
|
DELAY(20);
|
|
APC_WRITE(sc,
|
|
APC_CSR, APC_READ(sc, APC_CSR) & (~APC_CSR_CODEC_RESET));
|
|
} else {
|
|
v = AUXIO_READ(sc, AUXIO_CODEC);
|
|
if (how == CODEC_WARM_RESET && v != 0) {
|
|
AUXIO_WRITE(sc, AUXIO_CODEC, 0);
|
|
DELAY(20);
|
|
} else if (how == CODEC_COLD_RESET){
|
|
AUXIO_WRITE(sc, AUXIO_CODEC, 1);
|
|
DELAY(20);
|
|
AUXIO_WRITE(sc, AUXIO_CODEC, 0);
|
|
DELAY(20);
|
|
}
|
|
cs4231_ebdma_reset(sc);
|
|
}
|
|
|
|
for (i = CS_TIMEOUT;
|
|
i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
|
|
DELAY(10);
|
|
if (i == 0)
|
|
device_printf(sc->sc_dev, "timeout waiting for reset\n");
|
|
|
|
/* turn on cs4231 mode */
|
|
cs4231_write(sc, CS_MISC_INFO,
|
|
cs4231_read(sc, CS_MISC_INFO) | CS_MODE2);
|
|
/* enable interrupts & clear CSR */
|
|
cs4231_write(sc, CS_PIN_CONTROL,
|
|
cs4231_read(sc, CS_PIN_CONTROL) | INTERRUPT_ENABLE);
|
|
CS_WRITE(sc, CS4231_STATUS, 0);
|
|
/* enable DAC output */
|
|
cs4231_write(sc, CS_LEFT_OUTPUT_CONTROL,
|
|
cs4231_read(sc, CS_LEFT_OUTPUT_CONTROL) & ~OUTPUT_MUTE);
|
|
cs4231_write(sc, CS_RIGHT_OUTPUT_CONTROL,
|
|
cs4231_read(sc, CS_RIGHT_OUTPUT_CONTROL) & ~OUTPUT_MUTE);
|
|
/* mute AUX1 since it generates noises */
|
|
cs4231_write(sc, CS_LEFT_AUX1_CONTROL,
|
|
cs4231_read(sc, CS_LEFT_AUX1_CONTROL) | AUX_INPUT_MUTE);
|
|
cs4231_write(sc, CS_RIGHT_AUX1_CONTROL,
|
|
cs4231_read(sc, CS_RIGHT_AUX1_CONTROL) | AUX_INPUT_MUTE);
|
|
/* protect buffer underrun and set output level to 0dB */
|
|
cs4231_write(sc, CS_ALT_FEATURE1,
|
|
cs4231_read(sc, CS_ALT_FEATURE1) | CS_DAC_ZERO | CS_OUTPUT_LVL);
|
|
/* enable high pass filter, dual xtal was disabled due to noises */
|
|
cs4231_write(sc, CS_ALT_FEATURE2,
|
|
cs4231_read(sc, CS_ALT_FEATURE2) | CS_HPF_ENABLE);
|
|
}
|
|
|
|
static int
|
|
cs4231_enable(struct cs4231_softc *sc, int how)
|
|
{
|
|
cs4231_power_reset(sc, how);
|
|
sc->sc_enabled = 1;
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
cs4231_disable(struct cs4231_softc *sc)
|
|
{
|
|
u_int8_t v;
|
|
|
|
CS4231_LOCK_ASSERT(sc);
|
|
|
|
if (sc->sc_enabled == 0)
|
|
return;
|
|
sc->sc_enabled = 0;
|
|
CS4231_UNLOCK(sc);
|
|
cs4231_halt(&sc->sc_pch);
|
|
cs4231_halt(&sc->sc_rch);
|
|
CS4231_LOCK(sc);
|
|
v = cs4231_read(sc, CS_PIN_CONTROL) & ~INTERRUPT_ENABLE;
|
|
cs4231_write(sc, CS_PIN_CONTROL, v);
|
|
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0) {
|
|
APC_WRITE(sc, APC_CSR, APC_CSR_RESET);
|
|
DELAY(10);
|
|
APC_WRITE(sc, APC_CSR, 0);
|
|
DELAY(10);
|
|
} else
|
|
cs4231_ebdma_reset(sc);
|
|
}
|
|
|
|
static void
|
|
cs4231_free_resource(struct cs4231_softc *sc)
|
|
{
|
|
int i;
|
|
|
|
CS4231_LOCK(sc);
|
|
cs4231_disable(sc);
|
|
CS4231_UNLOCK(sc);
|
|
for (i = 0; i < sc->sc_nires; i++) {
|
|
if (sc->sc_irqres[i]) {
|
|
if (sc->sc_ih[i]) {
|
|
bus_teardown_intr(sc->sc_dev, sc->sc_irqres[i],
|
|
sc->sc_ih[i]);
|
|
sc->sc_ih[i] = NULL;
|
|
}
|
|
bus_release_resource(sc->sc_dev, SYS_RES_IRQ,
|
|
sc->sc_irqrid[i], sc->sc_irqres[i]);
|
|
sc->sc_irqres[i] = NULL;
|
|
}
|
|
}
|
|
for (i = 0; i < sc->sc_nires; i++) {
|
|
if (sc->sc_dmat[i])
|
|
bus_dma_tag_destroy(sc->sc_dmat[i]);
|
|
}
|
|
for (i = 0; i < sc->sc_nmres; i++) {
|
|
if (sc->sc_res[i])
|
|
bus_release_resource(sc->sc_dev, SYS_RES_MEMORY,
|
|
sc->sc_rid[i], sc->sc_res[i]);
|
|
}
|
|
snd_mtxfree(sc->sc_lock);
|
|
free(sc, M_DEVBUF);
|
|
}
|
|
|
|
static void
|
|
cs4231_write(struct cs4231_softc *sc, u_int8_t r, u_int8_t v)
|
|
{
|
|
CS_WRITE(sc, CS4231_IADDR, r);
|
|
CS_WRITE(sc, CS4231_IDATA, v);
|
|
}
|
|
|
|
static u_int8_t
|
|
cs4231_read(struct cs4231_softc *sc, u_int8_t r)
|
|
{
|
|
CS_WRITE(sc, CS4231_IADDR, r);
|
|
return (CS_READ(sc, CS4231_IDATA));
|
|
}
|
|
|
|
static void
|
|
cs4231_sbus_intr(void *arg)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *pch, *rch;
|
|
u_int32_t csr;
|
|
u_int8_t status;
|
|
|
|
sc = arg;
|
|
CS4231_LOCK(sc);
|
|
|
|
csr = APC_READ(sc, APC_CSR);
|
|
if ((csr & APC_CSR_GI) == 0) {
|
|
CS4231_UNLOCK(sc);
|
|
return;
|
|
}
|
|
APC_WRITE(sc, APC_CSR, csr);
|
|
|
|
if ((csr & APC_CSR_EIE) && (csr & APC_CSR_EI)) {
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
device_printf(sc->sc_dev,
|
|
"apc error interrupt : stat = 0x%x\n", status);
|
|
}
|
|
|
|
pch = rch = NULL;
|
|
if ((csr & APC_CSR_PMIE) && (csr & APC_CSR_PMI)) {
|
|
u_long nextaddr, saddr;
|
|
u_int32_t togo;
|
|
|
|
pch = &sc->sc_pch;
|
|
togo = pch->togo;
|
|
saddr = sndbuf_getbufaddr(pch->buffer);
|
|
nextaddr = pch->nextaddr + togo;
|
|
if (nextaddr >= saddr + sndbuf_getsize(pch->buffer))
|
|
nextaddr = saddr;
|
|
APC_WRITE(sc, APC_PNVA, nextaddr);
|
|
APC_WRITE(sc, APC_PNC, togo);
|
|
pch->nextaddr = nextaddr;
|
|
}
|
|
|
|
if ((csr & APC_CSR_CIE) && (csr & APC_CSR_CI) && (csr & APC_CSR_CD)) {
|
|
u_long nextaddr, saddr;
|
|
u_int32_t togo;
|
|
|
|
rch = &sc->sc_rch;
|
|
togo = rch->togo;
|
|
saddr = sndbuf_getbufaddr(rch->buffer);
|
|
nextaddr = rch->nextaddr + togo;
|
|
if (nextaddr >= saddr + sndbuf_getsize(rch->buffer))
|
|
nextaddr = saddr;
|
|
APC_WRITE(sc, APC_CNVA, nextaddr);
|
|
APC_WRITE(sc, APC_CNC, togo);
|
|
rch->nextaddr = nextaddr;
|
|
}
|
|
CS4231_UNLOCK(sc);
|
|
if (pch)
|
|
chn_intr(pch->channel);
|
|
if (rch)
|
|
chn_intr(rch->channel);
|
|
}
|
|
|
|
/* playback interrupt handler */
|
|
static void
|
|
cs4231_ebus_pintr(void *arg)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
u_int32_t csr;
|
|
u_int8_t status;
|
|
|
|
sc = arg;
|
|
CS4231_LOCK(sc);
|
|
|
|
csr = EBDMA_P_READ(sc, EBDMA_DCSR);
|
|
if ((csr & EBDCSR_INT) == 0) {
|
|
CS4231_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
if ((csr & EBDCSR_ERR)) {
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
device_printf(sc->sc_dev,
|
|
"ebdma error interrupt : stat = 0x%x\n", status);
|
|
}
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC);
|
|
|
|
ch = NULL;
|
|
if (csr & EBDCSR_TC) {
|
|
u_long nextaddr, saddr;
|
|
u_int32_t togo;
|
|
|
|
ch = &sc->sc_pch;
|
|
togo = ch->togo;
|
|
saddr = sndbuf_getbufaddr(ch->buffer);
|
|
nextaddr = ch->nextaddr + togo;
|
|
if (nextaddr >= saddr + sndbuf_getsize(ch->buffer))
|
|
nextaddr = saddr;
|
|
/*
|
|
* EBDMA_DCNT is loaded automatically
|
|
* EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
|
|
*/
|
|
EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
ch->nextaddr = nextaddr;
|
|
}
|
|
CS4231_UNLOCK(sc);
|
|
if (ch)
|
|
chn_intr(ch->channel);
|
|
}
|
|
|
|
/* capture interrupt handler */
|
|
static void
|
|
cs4231_ebus_cintr(void *arg)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
u_int32_t csr;
|
|
u_int8_t status;
|
|
|
|
sc = arg;
|
|
CS4231_LOCK(sc);
|
|
|
|
csr = EBDMA_C_READ(sc, EBDMA_DCSR);
|
|
if ((csr & EBDCSR_INT) == 0) {
|
|
CS4231_UNLOCK(sc);
|
|
return;
|
|
}
|
|
if ((csr & EBDCSR_ERR)) {
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
device_printf(sc->sc_dev,
|
|
"dma error interrupt : stat = 0x%x\n", status);
|
|
}
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR, csr | EBDCSR_TC);
|
|
|
|
ch = NULL;
|
|
if (csr & EBDCSR_TC) {
|
|
u_long nextaddr, saddr;
|
|
u_int32_t togo;
|
|
|
|
ch = &sc->sc_rch;
|
|
togo = ch->togo;
|
|
saddr = sndbuf_getbufaddr(ch->buffer);
|
|
nextaddr = ch->nextaddr + togo;
|
|
if (nextaddr >= saddr + sndbuf_getblksz(ch->buffer))
|
|
nextaddr = saddr;
|
|
/*
|
|
* EBDMA_DCNT is loaded automatically
|
|
* EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
|
|
*/
|
|
EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
ch->nextaddr = nextaddr;
|
|
}
|
|
CS4231_UNLOCK(sc);
|
|
if (ch)
|
|
chn_intr(ch->channel);
|
|
}
|
|
|
|
static const struct mix_table cs4231_mix_table[SOUND_MIXER_NRDEVICES][2] = {
|
|
[SOUND_MIXER_PCM] = {
|
|
{ CS_LEFT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 },
|
|
{ CS_RIGHT_OUTPUT_CONTROL, 6, OUTPUT_MUTE, 0, 1, 1, 0 }
|
|
},
|
|
[SOUND_MIXER_SPEAKER] = {
|
|
{ CS_MONO_IO_CONTROL, 4, MONO_OUTPUT_MUTE, 0, 1, 1, 0 },
|
|
{ CS_REG_NONE, 0, 0, 0, 0, 1, 0 }
|
|
},
|
|
[SOUND_MIXER_LINE] = {
|
|
{ CS_LEFT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 },
|
|
{ CS_RIGHT_LINE_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }
|
|
},
|
|
/*
|
|
* AUX1 : removed intentionally since it generates noises
|
|
* AUX2 : Ultra1/Ultra2 has no internal CD-ROM audio in
|
|
*/
|
|
[SOUND_MIXER_CD] = {
|
|
{ CS_LEFT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 },
|
|
{ CS_RIGHT_AUX2_CONTROL, 5, LINE_INPUT_MUTE, 0, 1, 1, 1 }
|
|
},
|
|
[SOUND_MIXER_MIC] = {
|
|
{ CS_LEFT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 },
|
|
{ CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 0, 1, 1 }
|
|
},
|
|
[SOUND_MIXER_IGAIN] = {
|
|
{ CS_LEFT_INPUT_CONTROL, 4, 0, 0, 1, 0 },
|
|
{ CS_RIGHT_INPUT_CONTROL, 4, 0, 0, 1, 0 }
|
|
}
|
|
};
|
|
|
|
static int
|
|
cs4231_mixer_init(struct snd_mixer *m)
|
|
{
|
|
u_int32_t v;
|
|
int i;
|
|
|
|
v = 0;
|
|
for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
|
|
if (cs4231_mix_table[i][0].avail != 0)
|
|
v |= (1 << i);
|
|
mix_setdevs(m, v);
|
|
v = 0;
|
|
for (i = 0; i < SOUND_MIXER_NRDEVICES; i++)
|
|
if (cs4231_mix_table[i][0].recdev != 0)
|
|
v |= (1 << i);
|
|
mix_setrecdevs(m, v);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
cs4231_mixer_set_value(struct cs4231_softc *sc, const struct mix_table *mt,
|
|
u_int8_t v)
|
|
{
|
|
u_int8_t mask, reg;
|
|
u_int8_t old, shift, val;
|
|
|
|
if (mt->avail == 0 || mt->reg == CS_REG_NONE)
|
|
return;
|
|
reg = mt->reg;
|
|
if (mt->neg != 0)
|
|
val = 100 - v;
|
|
else
|
|
val = v;
|
|
mask = (1 << mt->bits) - 1;
|
|
val = ((val * mask) + 50) / 100;
|
|
shift = mt->shift;
|
|
val <<= shift;
|
|
if (v == 0)
|
|
val |= mt->mute;
|
|
old = cs4231_read(sc, reg);
|
|
old &= ~(mt->mute | (mask << shift));
|
|
val |= old;
|
|
if (reg == CS_LEFT_INPUT_CONTROL || reg == CS_RIGHT_INPUT_CONTROL) {
|
|
if ((val & (mask << shift)) != 0)
|
|
val |= ADC_INPUT_GAIN_ENABLE;
|
|
else
|
|
val &= ~ADC_INPUT_GAIN_ENABLE;
|
|
}
|
|
cs4231_write(sc, reg, val);
|
|
}
|
|
|
|
static int
|
|
cs4231_mixer_set(struct snd_mixer *m, u_int32_t dev, u_int32_t left,
|
|
u_int32_t right)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
|
|
sc = mix_getdevinfo(m);
|
|
CS4231_LOCK(sc);
|
|
cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][0], left);
|
|
cs4231_mixer_set_value(sc, &cs4231_mix_table[dev][1], right);
|
|
CS4231_UNLOCK(sc);
|
|
|
|
return (left | (right << 8));
|
|
}
|
|
|
|
static u_int32_t
|
|
cs4231_mixer_setrecsrc(struct snd_mixer *m, u_int32_t src)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
u_int8_t v;
|
|
|
|
sc = mix_getdevinfo(m);
|
|
switch (src) {
|
|
case SOUND_MASK_LINE:
|
|
v = CS_IN_LINE;
|
|
break;
|
|
|
|
case SOUND_MASK_CD:
|
|
v = CS_IN_DAC;
|
|
break;
|
|
|
|
case SOUND_MASK_MIC:
|
|
default:
|
|
v = CS_IN_MIC;
|
|
src = SOUND_MASK_MIC;
|
|
break;
|
|
}
|
|
CS4231_LOCK(sc);
|
|
cs4231_write(sc, CS_LEFT_INPUT_CONTROL,
|
|
(cs4231_read(sc, CS_LEFT_INPUT_CONTROL) & CS_IN_MASK) | v);
|
|
cs4231_write(sc, CS_RIGHT_INPUT_CONTROL,
|
|
(cs4231_read(sc, CS_RIGHT_INPUT_CONTROL) & CS_IN_MASK) | v);
|
|
CS4231_UNLOCK(sc);
|
|
|
|
return (src);
|
|
}
|
|
|
|
static void *
|
|
cs4231_chan_init(kobj_t obj, void *dev, struct snd_dbuf *b,
|
|
struct pcm_channel *c, int dir)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
bus_dma_tag_t dmat;
|
|
|
|
sc = dev;
|
|
ch = (dir == PCMDIR_PLAY) ? &sc->sc_pch : &sc->sc_rch;
|
|
ch->parent = sc;
|
|
ch->channel = c;
|
|
ch->dir = dir;
|
|
ch->buffer = b;
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0)
|
|
dmat = sc->sc_dmat[0];
|
|
else {
|
|
if (dir == PCMDIR_PLAY)
|
|
dmat = sc->sc_dmat[1];
|
|
else
|
|
dmat = sc->sc_dmat[0];
|
|
}
|
|
if (sndbuf_alloc(ch->buffer, dmat, 0, sc->sc_bufsz) != 0)
|
|
return (NULL);
|
|
DPRINTF(("%s channel addr: 0x%lx\n", dir == PCMDIR_PLAY ? "playback" :
|
|
"capture", sndbuf_getbufaddr(ch->buffer)));
|
|
|
|
return (ch);
|
|
}
|
|
|
|
static int
|
|
cs4231_chan_setformat(kobj_t obj, void *data, u_int32_t format)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
u_int32_t encoding;
|
|
u_int8_t fs, v;
|
|
|
|
ch = data;
|
|
sc = ch->parent;
|
|
|
|
CS4231_LOCK(sc);
|
|
if (ch->format == format) {
|
|
CS4231_UNLOCK(sc);
|
|
return (0);
|
|
}
|
|
|
|
encoding = AFMT_ENCODING(format);
|
|
fs = 0;
|
|
switch (encoding) {
|
|
case AFMT_U8:
|
|
fs = CS_AFMT_U8;
|
|
break;
|
|
case AFMT_MU_LAW:
|
|
fs = CS_AFMT_MU_LAW;
|
|
break;
|
|
case AFMT_S16_LE:
|
|
fs = CS_AFMT_S16_LE;
|
|
break;
|
|
case AFMT_A_LAW:
|
|
fs = CS_AFMT_A_LAW;
|
|
break;
|
|
case AFMT_IMA_ADPCM:
|
|
fs = CS_AFMT_IMA_ADPCM;
|
|
break;
|
|
case AFMT_S16_BE:
|
|
fs = CS_AFMT_S16_BE;
|
|
break;
|
|
default:
|
|
fs = CS_AFMT_U8;
|
|
format = AFMT_U8;
|
|
break;
|
|
}
|
|
|
|
if (AFMT_CHANNEL(format) > 1)
|
|
fs |= CS_AFMT_STEREO;
|
|
|
|
DPRINTF(("FORMAT: %s : 0x%x\n", ch->dir == PCMDIR_PLAY ? "playback" :
|
|
"capture", format));
|
|
v = cs4231_read(sc, CS_CLOCK_DATA_FORMAT);
|
|
v &= CS_CLOCK_DATA_FORMAT_MASK;
|
|
fs |= v;
|
|
cs4231_chan_fs(sc, ch->dir, fs);
|
|
ch->format = format;
|
|
CS4231_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static u_int32_t
|
|
cs4231_chan_setspeed(kobj_t obj, void *data, u_int32_t speed)
|
|
{
|
|
typedef struct {
|
|
u_int32_t speed;
|
|
u_int8_t bits;
|
|
} speed_struct;
|
|
|
|
const static speed_struct speed_table[] = {
|
|
{5510, (0 << 1) | CLOCK_XTAL2},
|
|
{5510, (0 << 1) | CLOCK_XTAL2},
|
|
{6620, (7 << 1) | CLOCK_XTAL2},
|
|
{8000, (0 << 1) | CLOCK_XTAL1},
|
|
{9600, (7 << 1) | CLOCK_XTAL1},
|
|
{11025, (1 << 1) | CLOCK_XTAL2},
|
|
{16000, (1 << 1) | CLOCK_XTAL1},
|
|
{18900, (2 << 1) | CLOCK_XTAL2},
|
|
{22050, (3 << 1) | CLOCK_XTAL2},
|
|
{27420, (2 << 1) | CLOCK_XTAL1},
|
|
{32000, (3 << 1) | CLOCK_XTAL1},
|
|
{33075, (6 << 1) | CLOCK_XTAL2},
|
|
{33075, (4 << 1) | CLOCK_XTAL2},
|
|
{44100, (5 << 1) | CLOCK_XTAL2},
|
|
{48000, (6 << 1) | CLOCK_XTAL1},
|
|
};
|
|
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
int i, n, sel;
|
|
u_int8_t fs;
|
|
|
|
ch = data;
|
|
sc = ch->parent;
|
|
CS4231_LOCK(sc);
|
|
if (ch->speed == speed) {
|
|
CS4231_UNLOCK(sc);
|
|
return (speed);
|
|
}
|
|
n = sizeof(speed_table) / sizeof(speed_struct);
|
|
|
|
for (i = 1, sel =0; i < n - 1; i++)
|
|
if (abs(speed - speed_table[i].speed) <
|
|
abs(speed - speed_table[sel].speed))
|
|
sel = i;
|
|
DPRINTF(("SPEED: %s : %dHz -> %dHz\n", ch->dir == PCMDIR_PLAY ?
|
|
"playback" : "capture", speed, speed_table[sel].speed));
|
|
speed = speed_table[sel].speed;
|
|
|
|
fs = cs4231_read(sc, CS_CLOCK_DATA_FORMAT);
|
|
fs &= ~CS_CLOCK_DATA_FORMAT_MASK;
|
|
fs |= speed_table[sel].bits;
|
|
cs4231_chan_fs(sc, ch->dir, fs);
|
|
ch->speed = speed;
|
|
CS4231_UNLOCK(sc);
|
|
|
|
return (speed);
|
|
}
|
|
|
|
static void
|
|
cs4231_chan_fs(struct cs4231_softc *sc, int dir, u_int8_t fs)
|
|
{
|
|
int i, doreset;
|
|
#ifdef CS4231_AUTO_CALIBRATION
|
|
u_int8_t v;
|
|
#endif
|
|
|
|
CS4231_LOCK_ASSERT(sc);
|
|
|
|
/* set autocalibration */
|
|
doreset = 0;
|
|
#ifdef CS4231_AUTO_CALIBRATION
|
|
v = cs4231_read(sc, CS_INTERFACE_CONFIG) | AUTO_CAL_ENABLE;
|
|
CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE);
|
|
CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_INTERFACE_CONFIG);
|
|
CS_WRITE(sc, CS4231_IDATA, v);
|
|
#endif
|
|
|
|
/*
|
|
* We always need to write CS_CLOCK_DATA_FORMAT register since
|
|
* the clock frequency is shared with playback/capture.
|
|
*/
|
|
CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_CLOCK_DATA_FORMAT);
|
|
CS_WRITE(sc, CS4231_IDATA, fs);
|
|
CS_READ(sc, CS4231_IDATA);
|
|
CS_READ(sc, CS4231_IDATA);
|
|
for (i = CS_TIMEOUT;
|
|
i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
|
|
DELAY(10);
|
|
if (i == 0) {
|
|
device_printf(sc->sc_dev, "timeout setting playback speed\n");
|
|
doreset++;
|
|
}
|
|
|
|
/*
|
|
* capture channel
|
|
* cs4231 doesn't allow separate fs setup for playback/capture.
|
|
* I believe this will break full-duplex operation.
|
|
*/
|
|
if (dir == PCMDIR_REC) {
|
|
CS_WRITE(sc, CS4231_IADDR, MODE_CHANGE_ENABLE | CS_REC_FORMAT);
|
|
CS_WRITE(sc, CS4231_IDATA, fs);
|
|
CS_READ(sc, CS4231_IDATA);
|
|
CS_READ(sc, CS4231_IDATA);
|
|
for (i = CS_TIMEOUT;
|
|
i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
|
|
DELAY(10);
|
|
if (i == 0) {
|
|
device_printf(sc->sc_dev,
|
|
"timeout setting capture format\n");
|
|
doreset++;
|
|
}
|
|
}
|
|
|
|
CS_WRITE(sc, CS4231_IADDR, 0);
|
|
for (i = CS_TIMEOUT;
|
|
i && CS_READ(sc, CS4231_IADDR) == CS_IN_INIT; i--)
|
|
DELAY(10);
|
|
if (i == 0) {
|
|
device_printf(sc->sc_dev, "timeout waiting for !MCE\n");
|
|
doreset++;
|
|
}
|
|
|
|
#ifdef CS4231_AUTO_CALIBRATION
|
|
CS_WRITE(sc, CS4231_IADDR, CS_TEST_AND_INIT);
|
|
for (i = CS_TIMEOUT;
|
|
i && CS_READ(sc, CS4231_IDATA) & AUTO_CAL_IN_PROG; i--)
|
|
DELAY(10);
|
|
if (i == 0) {
|
|
device_printf(sc->sc_dev,
|
|
"timeout waiting for autocalibration\n");
|
|
doreset++;
|
|
}
|
|
#endif
|
|
if (doreset) {
|
|
/*
|
|
* Maybe the last resort to avoid a dreadful message like
|
|
* "pcm0:play:0: play interrupt timeout, channel dead" would
|
|
* be hardware reset.
|
|
*/
|
|
device_printf(sc->sc_dev, "trying to hardware reset\n");
|
|
cs4231_disable(sc);
|
|
cs4231_enable(sc, CODEC_COLD_RESET);
|
|
CS4231_UNLOCK(sc); /* XXX */
|
|
if (mixer_reinit(sc->sc_dev) != 0)
|
|
device_printf(sc->sc_dev,
|
|
"unable to reinitialize the mixer\n");
|
|
CS4231_LOCK(sc);
|
|
}
|
|
}
|
|
|
|
static u_int32_t
|
|
cs4231_chan_setblocksize(kobj_t obj, void *data, u_int32_t blocksize)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
int nblks, error;
|
|
|
|
ch = data;
|
|
sc = ch->parent;
|
|
|
|
if (blocksize > CS4231_MAX_BLK_SZ)
|
|
blocksize = CS4231_MAX_BLK_SZ;
|
|
nblks = sc->sc_bufsz / blocksize;
|
|
error = sndbuf_resize(ch->buffer, nblks, blocksize);
|
|
if (error != 0)
|
|
device_printf(sc->sc_dev,
|
|
"unable to block size, blksz = %d, error = %d\n",
|
|
blocksize, error);
|
|
|
|
return (blocksize);
|
|
}
|
|
|
|
static int
|
|
cs4231_chan_trigger(kobj_t obj, void *data, int go)
|
|
{
|
|
struct cs4231_channel *ch;
|
|
|
|
ch = data;
|
|
switch (go) {
|
|
case PCMTRIG_EMLDMAWR:
|
|
case PCMTRIG_EMLDMARD:
|
|
break;
|
|
case PCMTRIG_START:
|
|
cs4231_trigger(ch);
|
|
break;
|
|
case PCMTRIG_ABORT:
|
|
case PCMTRIG_STOP:
|
|
cs4231_halt(ch);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static u_int32_t
|
|
cs4231_chan_getptr(kobj_t obj, void *data)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
struct cs4231_channel *ch;
|
|
u_int32_t cur, ptr, sz;
|
|
|
|
ch = data;
|
|
sc = ch->parent;
|
|
|
|
CS4231_LOCK(sc);
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0)
|
|
cur = (ch->dir == PCMDIR_PLAY) ? APC_READ(sc, APC_PVA) :
|
|
APC_READ(sc, APC_CVA);
|
|
else
|
|
cur = (ch->dir == PCMDIR_PLAY) ? EBDMA_P_READ(sc, EBDMA_DADDR) :
|
|
EBDMA_C_READ(sc, EBDMA_DADDR);
|
|
sz = sndbuf_getsize(ch->buffer);
|
|
ptr = cur - sndbuf_getbufaddr(ch->buffer) + sz;
|
|
CS4231_UNLOCK(sc);
|
|
|
|
ptr %= sz;
|
|
return (ptr);
|
|
}
|
|
|
|
static struct pcmchan_caps *
|
|
cs4231_chan_getcaps(kobj_t obj, void *data)
|
|
{
|
|
|
|
return (&cs4231_caps);
|
|
}
|
|
|
|
static void
|
|
cs4231_trigger(struct cs4231_channel *ch)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
|
|
sc = ch->parent;
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0)
|
|
cs4231_apcdma_trigger(sc, ch);
|
|
else
|
|
cs4231_ebdma_trigger(sc, ch);
|
|
}
|
|
|
|
static void
|
|
cs4231_apcdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch)
|
|
{
|
|
u_int32_t csr, togo;
|
|
u_int32_t nextaddr;
|
|
|
|
CS4231_LOCK(sc);
|
|
if (ch->locked) {
|
|
device_printf(sc->sc_dev, "%s channel already triggered\n",
|
|
ch->dir == PCMDIR_PLAY ? "playback" : "capture");
|
|
CS4231_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
nextaddr = sndbuf_getbufaddr(ch->buffer);
|
|
togo = sndbuf_getsize(ch->buffer) / 2;
|
|
if (togo > CS4231_MAX_APC_DMA_SZ)
|
|
togo = CS4231_MAX_APC_DMA_SZ;
|
|
ch->togo = togo;
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
DPRINTF(("TRG: PNVA = 0x%x, togo = 0x%x\n", nextaddr, togo));
|
|
|
|
cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
|
|
csr = APC_READ(sc, APC_CSR);
|
|
APC_WRITE(sc, APC_PNVA, nextaddr);
|
|
APC_WRITE(sc, APC_PNC, togo);
|
|
|
|
if ((csr & APC_CSR_PDMA_GO) == 0 ||
|
|
(csr & APC_CSR_PPAUSE) != 0) {
|
|
APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) &
|
|
~(APC_CSR_PIE | APC_CSR_PPAUSE));
|
|
APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) |
|
|
APC_CSR_GIE | APC_CSR_PIE | APC_CSR_EIE |
|
|
APC_CSR_EI | APC_CSR_PMIE | APC_CSR_PDMA_GO);
|
|
cs4231_write(sc, CS_INTERFACE_CONFIG,
|
|
cs4231_read(sc, CS_INTERFACE_CONFIG) |
|
|
PLAYBACK_ENABLE);
|
|
}
|
|
/* load next address */
|
|
if (APC_READ(sc, APC_CSR) & APC_CSR_PD) {
|
|
nextaddr += togo;
|
|
APC_WRITE(sc, APC_PNVA, nextaddr);
|
|
APC_WRITE(sc, APC_PNC, togo);
|
|
}
|
|
} else {
|
|
DPRINTF(("TRG: CNVA = 0x%x, togo = 0x%x\n", nextaddr, togo));
|
|
|
|
cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
|
|
APC_WRITE(sc, APC_CNVA, nextaddr);
|
|
APC_WRITE(sc, APC_CNC, togo);
|
|
csr = APC_READ(sc, APC_CSR);
|
|
if ((csr & APC_CSR_CDMA_GO) == 0 ||
|
|
(csr & APC_CSR_CPAUSE) != 0) {
|
|
csr &= APC_CSR_CPAUSE;
|
|
csr |= APC_CSR_GIE | APC_CSR_CMIE | APC_CSR_CIE |
|
|
APC_CSR_EI | APC_CSR_CDMA_GO;
|
|
APC_WRITE(sc, APC_CSR, csr);
|
|
cs4231_write(sc, CS_INTERFACE_CONFIG,
|
|
cs4231_read(sc, CS_INTERFACE_CONFIG) |
|
|
CAPTURE_ENABLE);
|
|
}
|
|
/* load next address */
|
|
if (APC_READ(sc, APC_CSR) & APC_CSR_CD) {
|
|
nextaddr += togo;
|
|
APC_WRITE(sc, APC_CNVA, nextaddr);
|
|
APC_WRITE(sc, APC_CNC, togo);
|
|
}
|
|
}
|
|
ch->nextaddr = nextaddr;
|
|
ch->locked = 1;
|
|
CS4231_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
cs4231_ebdma_trigger(struct cs4231_softc *sc, struct cs4231_channel *ch)
|
|
{
|
|
u_int32_t csr, togo;
|
|
u_int32_t nextaddr;
|
|
|
|
CS4231_LOCK(sc);
|
|
if (ch->locked) {
|
|
device_printf(sc->sc_dev, "%s channel already triggered\n",
|
|
ch->dir == PCMDIR_PLAY ? "playback" : "capture");
|
|
CS4231_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
nextaddr = sndbuf_getbufaddr(ch->buffer);
|
|
togo = sndbuf_getsize(ch->buffer) / 2;
|
|
if (togo % 64 == 0)
|
|
sc->sc_burst = EBDCSR_BURST_16;
|
|
else if (togo % 32 == 0)
|
|
sc->sc_burst = EBDCSR_BURST_8;
|
|
else if (togo % 16 == 0)
|
|
sc->sc_burst = EBDCSR_BURST_4;
|
|
else
|
|
sc->sc_burst = EBDCSR_BURST_1;
|
|
ch->togo = togo;
|
|
DPRINTF(("TRG: DNAR = 0x%x, togo = 0x%x\n", nextaddr, togo));
|
|
if (ch->dir == PCMDIR_PLAY) {
|
|
cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
|
|
csr = EBDMA_P_READ(sc, EBDMA_DCSR);
|
|
|
|
if (csr & EBDCSR_DMAEN) {
|
|
EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
|
|
EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
} else {
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
|
|
EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
|
|
EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR, sc->sc_burst |
|
|
EBDCSR_DMAEN | EBDCSR_INTEN | EBDCSR_CNTEN |
|
|
EBDCSR_NEXTEN);
|
|
cs4231_write(sc, CS_INTERFACE_CONFIG,
|
|
cs4231_read(sc, CS_INTERFACE_CONFIG) |
|
|
PLAYBACK_ENABLE);
|
|
}
|
|
/* load next address */
|
|
if (EBDMA_P_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) {
|
|
nextaddr += togo;
|
|
EBDMA_P_WRITE(sc, EBDMA_DCNT, togo);
|
|
EBDMA_P_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
}
|
|
} else {
|
|
cs4231_read(sc, CS_TEST_AND_INIT); /* clear pending error */
|
|
csr = EBDMA_C_READ(sc, EBDMA_DCSR);
|
|
|
|
if (csr & EBDCSR_DMAEN) {
|
|
EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
|
|
EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
} else {
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR, EBDCSR_RESET);
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst);
|
|
EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
|
|
EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR, sc->sc_burst |
|
|
EBDCSR_WRITE | EBDCSR_DMAEN | EBDCSR_INTEN |
|
|
EBDCSR_CNTEN | EBDCSR_NEXTEN);
|
|
cs4231_write(sc, CS_INTERFACE_CONFIG,
|
|
cs4231_read(sc, CS_INTERFACE_CONFIG) |
|
|
CAPTURE_ENABLE);
|
|
}
|
|
/* load next address */
|
|
if (EBDMA_C_READ(sc, EBDMA_DCSR) & EBDCSR_A_LOADED) {
|
|
nextaddr += togo;
|
|
EBDMA_C_WRITE(sc, EBDMA_DCNT, togo);
|
|
EBDMA_C_WRITE(sc, EBDMA_DADDR, nextaddr);
|
|
}
|
|
}
|
|
ch->nextaddr = nextaddr;
|
|
ch->locked = 1;
|
|
CS4231_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
cs4231_halt(struct cs4231_channel *ch)
|
|
{
|
|
struct cs4231_softc *sc;
|
|
u_int8_t status;
|
|
int i;
|
|
|
|
sc = ch->parent;
|
|
CS4231_LOCK(sc);
|
|
if (ch->locked == 0) {
|
|
CS4231_UNLOCK(sc);
|
|
return;
|
|
}
|
|
|
|
if (ch->dir == PCMDIR_PLAY ) {
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0) {
|
|
/* XXX Kills some capture bits */
|
|
APC_WRITE(sc, APC_CSR, APC_READ(sc, APC_CSR) &
|
|
~(APC_CSR_EI | APC_CSR_GIE | APC_CSR_PIE |
|
|
APC_CSR_EIE | APC_CSR_PDMA_GO | APC_CSR_PMIE));
|
|
} else {
|
|
EBDMA_P_WRITE(sc, EBDMA_DCSR,
|
|
EBDMA_P_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN);
|
|
}
|
|
/* Waiting for playback FIFO to empty */
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
for (i = CS_TIMEOUT;
|
|
i && (status & PLAYBACK_UNDERRUN) == 0; i--) {
|
|
DELAY(5);
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
}
|
|
if (i == 0)
|
|
device_printf(sc->sc_dev, "timeout waiting for "
|
|
"playback FIFO drain\n");
|
|
cs4231_write(sc, CS_INTERFACE_CONFIG,
|
|
cs4231_read(sc, CS_INTERFACE_CONFIG) & (~PLAYBACK_ENABLE));
|
|
} else {
|
|
if ((sc->sc_flags & CS4231_SBUS) != 0) {
|
|
/* XXX Kills some playback bits */
|
|
APC_WRITE(sc, APC_CSR, APC_CSR_CAPTURE_PAUSE);
|
|
} else {
|
|
EBDMA_C_WRITE(sc, EBDMA_DCSR,
|
|
EBDMA_C_READ(sc, EBDMA_DCSR) & ~EBDCSR_DMAEN);
|
|
}
|
|
/* Waiting for capture FIFO to empty */
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
for (i = CS_TIMEOUT;
|
|
i && (status & CAPTURE_OVERRUN) == 0; i--) {
|
|
DELAY(5);
|
|
status = cs4231_read(sc, CS_TEST_AND_INIT);
|
|
}
|
|
if (i == 0)
|
|
device_printf(sc->sc_dev, "timeout waiting for "
|
|
"capture FIFO drain\n");
|
|
cs4231_write(sc, CS_INTERFACE_CONFIG,
|
|
cs4231_read(sc, CS_INTERFACE_CONFIG) & (~CAPTURE_ENABLE));
|
|
}
|
|
ch->locked = 0;
|
|
CS4231_UNLOCK(sc);
|
|
}
|