6d0737d0cb
the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also already includes all the code to support the `Oberon' Uranus to PCIe bridges found in the Fujitsu-Siemens based Mx000 machines but due to lack of access to such a system for testing, probing of these bridges is currently disabled. Unfortunately, the event queue mechanism of these bridges for MSIs/ MSI-Xs matches our current MD and MI interrupt frameworks like square pegs fit into round holes so for now we are generous and use one event queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge (we use one event queue for the PCIe error messages). This seems tolerable as long as most devices just use one MSI/MSI-X anyway. Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should allow us to decouple the 1:1 mapping at the cost of no longer being able to bind MSIs/MSI-Xs to specific CPUs as we currently have no reliable way to quiesce a device during the transition of its MSIs/ MSI-Xs to another event queue. This would still require the problem of interrupt storms generated by devices which have no one-shot behavior or can't/don't mask interrupts while the filter/handler is executed (like the older PCIe NICs supported by bge(4)) to be solved though. Committed from: 26C3
99 lines
3.0 KiB
C
99 lines
3.0 KiB
C
/*-
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* Copyright (c) 2009 by Marius Strobl <marius@FreeBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _SPARC64_PCI_FIREVAR_H_
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#define _SPARC64_PCI_FIREVAR_H_
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struct fire_softc {
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struct iommu_state sc_is;
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struct bus_dma_methods sc_dma_methods;
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struct mtx sc_msi_mtx;
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struct mtx sc_pcib_mtx;
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struct resource *sc_mem_res[FIRE_NREG];
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struct resource *sc_irq_res[FIRE_NINTR];
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void *sc_ihand[FIRE_NINTR];
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struct rman sc_pci_mem_rman;
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struct rman sc_pci_io_rman;
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bus_space_handle_t sc_pci_bh[FIRE_NRANGE];
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bus_space_tag_t sc_pci_cfgt;
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bus_space_tag_t sc_pci_iot;
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bus_space_tag_t sc_pci_memt;
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bus_dma_tag_t sc_pci_dmat;
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device_t sc_dev;
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uint64_t *sc_msiq;
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u_char *sc_msi_bitmap;
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uint32_t *sc_msi_msiq_table;
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u_char *sc_msiq_bitmap;
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uint64_t sc_msi_addr32;
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uint64_t sc_msi_addr64;
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uint32_t sc_msi_count;
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uint32_t sc_msi_first;
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uint32_t sc_msi_data_mask;
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uint32_t sc_msix_data_width;
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uint32_t sc_msiq_count;
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uint32_t sc_msiq_size;
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uint32_t sc_msiq_first;
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uint32_t sc_msiq_ino_first;
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phandle_t sc_node;
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u_int sc_mode;
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#define FIRE_MODE_FIRE 0
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#define FIRE_MODE_OBERON 1
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u_int sc_flags;
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#define FIRE_MSIX (1 << 0)
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uint32_t sc_ign;
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uint32_t sc_stats_ilu_err;
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uint32_t sc_stats_jbc_ce_async;
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uint32_t sc_stats_jbc_unsol_int;
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uint32_t sc_stats_jbc_unsol_rd;
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uint32_t sc_stats_mmu_err;
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uint32_t sc_stats_tlu_ce;
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uint32_t sc_stats_tlu_oe_non_fatal;
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uint32_t sc_stats_tlu_oe_rx_err;
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uint32_t sc_stats_tlu_oe_tx_err;
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uint32_t sc_stats_ubc_dmardue;
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uint8_t sc_pci_secbus;
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uint8_t sc_pci_subbus;
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struct ofw_bus_iinfo sc_pci_iinfo;
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};
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#endif /* !_SPARC64_PCI_FIREVAR_H_ */
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