bf6955f98a
Bluespec Extensible RISC Implementation (BERI) processor. BERI is a 64-bit MIPS ISA soft CPU core that can be synthesised to Altera and Xilinx FPGAs, and is being used for CPU and OS research at several institutions. Sponsored by: DARPA, AFRL
87 lines
2.6 KiB
Plaintext
87 lines
2.6 KiB
Plaintext
# Copyright (c) 2001, 2008, Juniper Networks, Inc.
|
|
# All rights reserved.
|
|
#
|
|
# Redistribution and use in source and binary forms, with or without
|
|
# modification, are permitted provided that the following conditions
|
|
# are met:
|
|
# 1. Redistributions of source code must retain the above copyright
|
|
# notice, this list of conditions and the following disclaimer.
|
|
# 2. Redistributions in binary form must reproduce the above copyright
|
|
# notice, this list of conditions and the following disclaimer in the
|
|
# documentation and/or other materials provided with the distribution.
|
|
# 3. Neither the name of the Juniper Networks, Inc. nor the names of its
|
|
# contributors may be used to endorse or promote products derived from
|
|
# this software without specific prior written permission.
|
|
#
|
|
# THIS SOFTWARE IS PROVIDED BY JUNIPER NETWORKS AND CONTRIBUTORS ``AS IS'' AND
|
|
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
|
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
|
# ARE DISCLAIMED. IN NO EVENT SHALL JUNIPER NETWORKS OR CONTRIBUTORS BE LIABLE
|
|
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
|
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
|
|
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
|
|
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
|
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
|
|
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
|
# SUCH DAMAGE.
|
|
#
|
|
# JNPR: options.mips,v 1.2 2006/09/15 12:52:34
|
|
# $FreeBSD$
|
|
|
|
CPU_MIPS4KC opt_global.h
|
|
CPU_MIPS32 opt_global.h
|
|
CPU_MIPS64 opt_global.h
|
|
CPU_SENTRY5 opt_global.h
|
|
CPU_HAVEFPU opt_global.h
|
|
CPU_SB1 opt_global.h
|
|
CPU_CNMIPS opt_global.h
|
|
CPU_RMI opt_global.h
|
|
CPU_NLM opt_global.h
|
|
CPU_BERI opt_global.h
|
|
|
|
COMPAT_FREEBSD32 opt_compat.h
|
|
|
|
YAMON opt_global.h
|
|
CFE opt_global.h
|
|
CFE_CONSOLE opt_global.h
|
|
CFE_ENV opt_global.h
|
|
CFE_ENV_SIZE opt_global.h
|
|
|
|
GFB_DEBUG opt_gfb.h
|
|
GFB_NO_FONT_LOADING opt_gfb.h
|
|
GFB_NO_MODE_CHANGE opt_gfb.h
|
|
|
|
NOFPU opt_global.h
|
|
|
|
TICK_USE_YAMON_FREQ opt_global.h
|
|
TICK_USE_MALTA_RTC opt_global.h
|
|
|
|
#
|
|
# The highest memory address that can be used by the kernel in units of KB.
|
|
#
|
|
MAXMEM opt_global.h
|
|
|
|
#
|
|
# Options that control the Cavium Simple Executive.
|
|
#
|
|
OCTEON_VENDOR_LANNER opt_cvmx.h
|
|
OCTEON_BOARD_CAPK_0100ND opt_cvmx.h
|
|
|
|
#
|
|
# Options that control the Atheros SoC peripherals
|
|
#
|
|
ARGE_DEBUG opt_arge.h
|
|
ARGE_MDIO opt_arge.h
|
|
|
|
#
|
|
# Options that control the Ralink RT305xF Etherenet MAC.
|
|
#
|
|
IF_RT_DEBUG opt_if_rt.h
|
|
IF_RT_PHY_SUPPORT opt_if_rt.h
|
|
IF_RT_RING_DATA_COUNT opt_if_rt.h
|
|
|
|
#
|
|
# Options that affect the pmap.
|
|
#
|
|
PV_STATS opt_pmap.h
|