faf2f0725c
No functional changes to the code are applied. Submitted by: Kornel Duleba <mindal@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield
508 lines
12 KiB
C
508 lines
12 KiB
C
/*-
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* Copyright (c) 2018 Stormshield.
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* Copyright (c) 2018 Semihalf.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "tpm20.h"
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/*
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* TIS register space as defined in
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* TCG_PC_Client_Platform_TPM_Profile_PTP_2.0_r1.03_v22
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*/
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#define TPM_ACCESS 0x0
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#define TPM_INT_ENABLE 0x8
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#define TPM_INT_VECTOR 0xc
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#define TPM_INT_STS 0x10
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#define TPM_INTF_CAPS 0x14
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#define TPM_STS 0x18
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#define TPM_DATA_FIFO 0x24
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#define TPM_INTF_ID 0x30
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#define TPM_XDATA_FIFO 0x80
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#define TPM_DID_VID 0xF00
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#define TPM_RID 0xF04
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#define TPM_ACCESS_LOC_REQ BIT(1)
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#define TPM_ACCESS_LOC_Seize BIT(3)
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#define TPM_ACCESS_LOC_ACTIVE BIT(5)
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#define TPM_ACCESS_LOC_RELINQUISH BIT(5)
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#define TPM_ACCESS_VALID BIT(7)
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#define TPM_INT_ENABLE_GLOBAL_ENABLE BIT(31)
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#define TPM_INT_ENABLE_CMD_RDY BIT(7)
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#define TPM_INT_ENABLE_LOC_CHANGE BIT(2)
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#define TPM_INT_ENABLE_STS_VALID BIT(1)
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#define TPM_INT_ENABLE_DATA_AVAIL BIT(0)
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#define TPM_INT_STS_CMD_RDY BIT(7)
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#define TPM_INT_STS_LOC_CHANGE BIT(2)
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#define TPM_INT_STS_VALID BIT(1)
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#define TPM_INT_STS_DATA_AVAIL BIT(0)
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#define TPM_INTF_CAPS_VERSION 0x70000000
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#define TPM_INTF_CAPS_TPM20 0x30000000
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#define TPM_STS_VALID BIT(7)
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#define TPM_STS_CMD_RDY BIT(6)
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#define TPM_STS_CMD_START BIT(5)
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#define TPM_STS_DATA_AVAIL BIT(4)
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#define TPM_STS_DATA_EXPECTED BIT(3)
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#define TPM_STS_BURST_MASK 0xFFFF00
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#define TPM_STS_BURST_OFFSET 0x8
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static int tpmtis_transmit(struct tpm_sc *sc, size_t length);
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static int tpmtis_acpi_probe(device_t dev);
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static int tpmtis_attach(device_t dev);
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static int tpmtis_detach(device_t dev);
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static void tpmtis_intr_handler(void *arg);
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static ACPI_STATUS tpmtis_get_SIRQ_channel(ACPI_RESOURCE *res, void *arg);
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static bool tpmtis_setup_intr(struct tpm_sc *sc);
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static bool tpmtis_read_bytes(struct tpm_sc *sc, size_t count, uint8_t *buf);
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static bool tpmtis_write_bytes(struct tpm_sc *sc, size_t count, uint8_t *buf);
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static bool tpmtis_request_locality(struct tpm_sc *sc, int locality);
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static void tpmtis_relinquish_locality(struct tpm_sc *sc);
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static bool tpmtis_go_ready(struct tpm_sc *sc);
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static bool tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off,
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uint32_t mask, uint32_t val, int32_t timeout);
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static uint16_t tpmtis_wait_for_burst(struct tpm_sc *sc);
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char *tpmtis_ids[] = {"MSFT0101", NULL};
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static int
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tpmtis_acpi_probe(device_t dev)
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{
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int err;
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ACPI_TABLE_TPM23 *tbl;
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ACPI_STATUS status;
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err = ACPI_ID_PROBE(device_get_parent(dev), dev, tpmtis_ids, NULL);
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if (err > 0)
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return (err);
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/*Find TPM2 Header*/
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status = AcpiGetTable(ACPI_SIG_TPM2, 1, (ACPI_TABLE_HEADER **) &tbl);
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if(ACPI_FAILURE(status) ||
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tbl->StartMethod != TPM2_START_METHOD_TIS)
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err = ENXIO;
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device_set_desc(dev, "Trusted Platform Module 2.0, FIFO mode");
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return (err);
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}
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static int
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tpmtis_attach(device_t dev)
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{
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struct tpm_sc *sc;
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int result;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->mem_rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
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RF_ACTIVE);
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if (sc->mem_res == NULL)
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return (ENXIO);
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sc->irq_rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->irq_res != NULL) {
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, tpmtis_intr_handler, sc, &sc->intr_cookie))
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sc->interrupts = false;
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else
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sc->interrupts = tpmtis_setup_intr(sc);
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} else {
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sc->interrupts = false;
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}
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sc->intr_type = -1;
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sc->transmit = tpmtis_transmit;
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result = tpm20_init(sc);
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if (result != 0)
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tpmtis_detach(dev);
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return (result);
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}
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static int
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tpmtis_detach(device_t dev)
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{
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struct tpm_sc *sc;
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sc = device_get_softc(dev);
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tpm20_release(sc);
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if (sc->intr_cookie != NULL)
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bus_teardown_intr(dev, sc->irq_res, sc->intr_cookie);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ,
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sc->irq_rid, sc->irq_res);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY,
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sc->mem_rid, sc->mem_res);
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return (0);
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}
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static ACPI_STATUS
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tpmtis_get_SIRQ_channel(ACPI_RESOURCE *res, void *arg)
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{
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struct tpm_sc *sc;
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uint8_t channel;
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sc = (struct tpm_sc *)arg;
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switch (res->Type) {
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case ACPI_RESOURCE_TYPE_IRQ:
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channel = res->Data.Irq.Interrupts[0];
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break;
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case ACPI_RESOURCE_TYPE_EXTENDED_IRQ:
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channel = res->Data.ExtendedIrq.Interrupts[0];
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break;
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default:
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return (AE_OK);
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}
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WR1(sc, TPM_INT_VECTOR, channel);
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return (AE_OK);
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}
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static bool
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tpmtis_setup_intr(struct tpm_sc *sc)
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{
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ACPI_STATUS status;
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ACPI_HANDLE handle;
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uint32_t irq_mask;
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handle = acpi_get_handle(sc->dev);
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if(!tpmtis_request_locality(sc, 0))
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return (false);
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irq_mask = RD4(sc, TPM_INT_ENABLE);
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irq_mask |= TPM_INT_ENABLE_GLOBAL_ENABLE |
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TPM_INT_ENABLE_DATA_AVAIL |
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TPM_INT_ENABLE_LOC_CHANGE |
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TPM_INT_ENABLE_CMD_RDY |
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TPM_INT_ENABLE_STS_VALID;
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WR4(sc, TPM_INT_ENABLE, irq_mask);
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status = AcpiWalkResources(handle, "_CRS",
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tpmtis_get_SIRQ_channel, (void *)sc);
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tpmtis_relinquish_locality(sc);
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return (ACPI_SUCCESS(status));
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}
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static void
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tpmtis_intr_handler(void *arg)
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{
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struct tpm_sc *sc;
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uint32_t status;
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sc = (struct tpm_sc *)arg;
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status = RD4(sc, TPM_INT_STS);
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WR4(sc, TPM_INT_STS, status);
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if (sc->intr_type != -1 && sc->intr_type & status)
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wakeup(sc);
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}
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static bool
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tpm_wait_for_u32(struct tpm_sc *sc, bus_size_t off, uint32_t mask, uint32_t val,
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int32_t timeout)
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{
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/* Check for condition */
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if ((RD4(sc, off) & mask) == val)
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return (true);
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/* If interrupts are enabled sleep for timeout duration */
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if(sc->interrupts && sc->intr_type != -1) {
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tsleep(sc, PWAIT, "TPM WITH INTERRUPTS", timeout / tick);
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sc->intr_type = -1;
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return ((RD4(sc, off) & mask) == val);
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}
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/* If we don't have interrupts poll the device every tick */
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while (timeout > 0) {
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if ((RD4(sc, off) & mask) == val)
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return (true);
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pause("TPM POLLING", 1);
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timeout -= tick;
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}
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return (false);
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}
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static uint16_t
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tpmtis_wait_for_burst(struct tpm_sc *sc)
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{
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int timeout;
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uint16_t burst_count;
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timeout = TPM_TIMEOUT_A;
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while (timeout-- > 0) {
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burst_count = (RD4(sc, TPM_STS) & TPM_STS_BURST_MASK) >>
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TPM_STS_BURST_OFFSET;
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if (burst_count > 0)
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break;
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DELAY(1);
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}
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return (burst_count);
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}
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static bool
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tpmtis_read_bytes(struct tpm_sc *sc, size_t count, uint8_t *buf)
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{
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uint16_t burst_count;
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while (count > 0) {
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burst_count = tpmtis_wait_for_burst(sc);
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if (burst_count == 0)
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return (false);
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burst_count = MIN(burst_count, count);
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count -= burst_count;
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while (burst_count-- > 0)
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*buf++ = RD1(sc, TPM_DATA_FIFO);
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}
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return (true);
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}
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static bool
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tpmtis_write_bytes(struct tpm_sc *sc, size_t count, uint8_t *buf)
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{
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uint16_t burst_count;
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while (count > 0) {
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burst_count = tpmtis_wait_for_burst(sc);
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if (burst_count == 0)
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return (false);
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burst_count = MIN(burst_count, count);
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count -= burst_count;
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while (burst_count-- > 0)
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WR1(sc, TPM_DATA_FIFO, *buf++);
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}
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return (true);
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}
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static bool
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tpmtis_request_locality(struct tpm_sc *sc, int locality)
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{
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uint8_t mask;
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int timeout;
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/* Currently we only support Locality 0 */
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if (locality != 0)
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return (false);
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mask = TPM_ACCESS_LOC_ACTIVE | TPM_ACCESS_VALID;
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timeout = TPM_TIMEOUT_A;
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sc->intr_type = TPM_INT_STS_LOC_CHANGE;
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WR1(sc, TPM_ACCESS, TPM_ACCESS_LOC_REQ);
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bus_barrier(sc->mem_res, TPM_ACCESS, 1, BUS_SPACE_BARRIER_WRITE);
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if(sc->interrupts) {
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tsleep(sc, PWAIT, "TPMLOCREQUEST with INTR", timeout / tick);
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return ((RD1(sc, TPM_ACCESS) & mask) == mask);
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} else {
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while(timeout > 0) {
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if ((RD1(sc, TPM_ACCESS) & mask) == mask)
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return (true);
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pause("TPMLOCREQUEST POLLING", 1);
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timeout -= tick;
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}
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}
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return (false);
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}
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static void
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tpmtis_relinquish_locality(struct tpm_sc *sc)
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{
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/*
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* Interrupts can only be cleared when a locality is active.
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* Clear them now in case interrupt handler didn't make it in time.
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*/
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if(sc->interrupts)
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AND4(sc, TPM_INT_STS, RD4(sc, TPM_INT_STS));
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OR1(sc, TPM_ACCESS, TPM_ACCESS_LOC_RELINQUISH);
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}
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static bool
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tpmtis_go_ready(struct tpm_sc *sc)
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{
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uint32_t mask;
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mask = TPM_STS_CMD_RDY;
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sc->intr_type = TPM_INT_STS_CMD_RDY;
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OR4(sc, TPM_STS, TPM_STS_CMD_RDY);
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bus_barrier(sc->mem_res, TPM_STS, 4, BUS_SPACE_BARRIER_WRITE);
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if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_B))
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return (false);
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AND4(sc, TPM_STS, ~TPM_STS_CMD_RDY);
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return (true);
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}
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static int
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tpmtis_transmit(struct tpm_sc *sc, size_t length)
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{
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size_t bytes_available;
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uint32_t mask, curr_cmd;
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int timeout;
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sx_assert(&sc->dev_lock, SA_XLOCKED);
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if (!tpmtis_request_locality(sc, 0)) {
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device_printf(sc->dev,
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"Failed to obtain locality\n");
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return (EIO);
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}
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if (!tpmtis_go_ready(sc)) {
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device_printf(sc->dev,
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"Failed to switch to ready state\n");
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return (EIO);
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}
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if (!tpmtis_write_bytes(sc, length, sc->buf)) {
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device_printf(sc->dev,
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"Failed to write cmd to device\n");
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return (EIO);
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}
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mask = TPM_STS_VALID;
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sc->intr_type = TPM_INT_STS_VALID;
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if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C)) {
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device_printf(sc->dev,
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"Timeout while waiting for valid bit\n");
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return (EIO);
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}
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if (RD4(sc, TPM_STS) & TPM_STS_DATA_EXPECTED) {
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device_printf(sc->dev,
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"Device expects more data even though we already"
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" sent everything we had\n");
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return (EIO);
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}
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/*
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* Calculate timeout for current command.
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* Command code is passed in bytes 6-10.
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*/
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curr_cmd = be32toh(*(uint32_t *) (&sc->buf[6]));
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timeout = tpm20_get_timeout(curr_cmd);
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WR4(sc, TPM_STS, TPM_STS_CMD_START);
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bus_barrier(sc->mem_res, TPM_STS, 4, BUS_SPACE_BARRIER_WRITE);
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mask = TPM_STS_DATA_AVAIL | TPM_STS_VALID;
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sc->intr_type = TPM_INT_STS_DATA_AVAIL;
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if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, timeout)) {
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device_printf(sc->dev,
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"Timeout while waiting for device to process cmd\n");
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/*
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* Switching to ready state also cancels processing
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* current command
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*/
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if (!tpmtis_go_ready(sc))
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return (EIO);
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/*
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* After canceling a command we should get a response,
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* check if there is one.
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*/
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sc->intr_type = TPM_INT_STS_DATA_AVAIL;
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if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C))
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return (EIO);
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}
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/* Read response header. Length is passed in bytes 2 - 6. */
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if(!tpmtis_read_bytes(sc, TPM_HEADER_SIZE, sc->buf)) {
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device_printf(sc->dev,
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"Failed to read response header\n");
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return (EIO);
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}
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bytes_available = be32toh(*(uint32_t *) (&sc->buf[2]));
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if (bytes_available > TPM_BUFSIZE || bytes_available < TPM_HEADER_SIZE) {
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device_printf(sc->dev,
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"Incorrect response size: %zu\n",
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bytes_available);
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return (EIO);
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}
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if(!tpmtis_read_bytes(sc, bytes_available - TPM_HEADER_SIZE,
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&sc->buf[TPM_HEADER_SIZE])) {
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device_printf(sc->dev,
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"Failed to read response\n");
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return (EIO);
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}
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tpmtis_relinquish_locality(sc);
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sc->pending_data_length = bytes_available;
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return (0);
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}
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/* ACPI Driver */
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static device_method_t tpmtis_methods[] = {
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DEVMETHOD(device_probe, tpmtis_acpi_probe),
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DEVMETHOD(device_attach, tpmtis_attach),
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DEVMETHOD(device_detach, tpmtis_detach),
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DEVMETHOD(device_shutdown, tpm20_shutdown),
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DEVMETHOD(device_suspend, tpm20_suspend),
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{0, 0}
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};
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static driver_t tpmtis_driver = {
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"tpmtis", tpmtis_methods, sizeof(struct tpm_sc),
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};
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devclass_t tpmtis_devclass;
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DRIVER_MODULE(tpmtis, acpi, tpmtis_driver, tpmtis_devclass, 0, 0);
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