d74ac6819b
disablement assumptions in kern_fork.c by adding another API call, cpu_critical_fork_exit(). Cleanup the td_savecrit field by moving it from MI to MD. Temporarily move cpu_critical*() from <arch>/include/cpufunc.h to <arch>/<arch>/critical.c (stage-2 will clean this up). Implement interrupt deferral for i386 that allows interrupts to remain enabled inside critical sections. This also fixes an IPI interlock bug, and requires uses of icu_lock to be enclosed in a true interrupt disablement. This is the stage-1 commit. Stage-2 will occur after stage-1 has stabilized, and will move cpu_critical*() into its own header file(s) + other things. This commit may break non-i386 architectures in trivial ways. This should be temporary. Reviewed by: core Approved by: core
250 lines
8.4 KiB
C
250 lines
8.4 KiB
C
/*-
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* Copyright (c) 1991 The Regents of the University of California.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _I386_ISA_INTR_MACHDEP_H_
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#define _I386_ISA_INTR_MACHDEP_H_
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/*
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* Low level interrupt code.
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*/
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#ifdef _KERNEL
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#if defined(SMP) || defined(APIC_IO)
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/*
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* XXX FIXME: rethink location for all IPI vectors.
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*/
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/*
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APIC TPR priority vector levels:
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0xff (255) +-------------+
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| | 15 (IPIs: Xspuriousint)
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0xf0 (240) +-------------+
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| | 14
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0xe0 (224) +-------------+
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| | 13
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0xd0 (208) +-------------+
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| | 12
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0xc0 (192) +-------------+
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| | 11
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0xb0 (176) +-------------+
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| | 10 (IPIs: Xcpustop)
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0xa0 (160) +-------------+
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| | 9 (IPIs: Xinvltlb)
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0x90 (144) +-------------+
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| | 8 (linux/BSD syscall, IGNORE FAST HW INTS)
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0x80 (128) +-------------+
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| | 7 (FAST_INTR 16-23)
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0x70 (112) +-------------+
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| | 6 (FAST_INTR 0-15)
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0x60 (96) +-------------+
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| | 5 (IGNORE HW INTS)
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0x50 (80) +-------------+
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| | 4 (2nd IO APIC)
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0x40 (64) +------+------+
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| | | 3 (upper APIC hardware INTs: PCI)
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0x30 (48) +------+------+
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| | 2 (start of hardware INTs: ISA)
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0x20 (32) +-------------+
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| | 1 (exceptions, traps, etc.)
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0x10 (16) +-------------+
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| | 0 (exceptions, traps, etc.)
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0x00 (0) +-------------+
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*/
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/* IDT vector base for regular (aka. slow) and fast interrupts */
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#define TPR_SLOW_INTS 0x20
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#define TPR_FAST_INTS 0x60
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/* blocking values for local APIC Task Priority Register */
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#define TPR_BLOCK_HWI 0x4f /* hardware INTs */
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#define TPR_IGNORE_HWI 0x5f /* ignore INTs */
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#define TPR_BLOCK_FHWI 0x7f /* hardware FAST INTs */
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#define TPR_IGNORE_FHWI 0x8f /* ignore FAST INTs */
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#define TPR_BLOCK_XINVLTLB 0x9f /* */
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#define TPR_BLOCK_XCPUSTOP 0xaf /* */
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#define TPR_BLOCK_ALL 0xff /* all INTs */
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#ifdef TEST_TEST1
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/* put a 'fake' HWI in top of APIC prio 0x3x, 32 + 31 = 63 = 0x3f */
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#define XTEST1_OFFSET (ICU_OFFSET + 31)
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#endif /** TEST_TEST1 */
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/* TLB shootdowns */
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#define XINVLTLB_OFFSET (ICU_OFFSET + 112)
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/* inter-cpu clock handling */
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#define XHARDCLOCK_OFFSET (ICU_OFFSET + 113)
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#define XSTATCLOCK_OFFSET (ICU_OFFSET + 114)
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/* inter-CPU rendezvous */
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#define XRENDEZVOUS_OFFSET (ICU_OFFSET + 115)
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/* IPI to generate an additional software trap at the target CPU */
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#define XCPUAST_OFFSET (ICU_OFFSET + 48)
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/* IPI to signal CPUs to stop and wait for another CPU to restart them */
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#define XCPUSTOP_OFFSET (ICU_OFFSET + 128)
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/*
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* Note: this vector MUST be xxxx1111, 32 + 223 = 255 = 0xff:
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*/
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#define XSPURIOUSINT_OFFSET (ICU_OFFSET + 223)
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#endif /* SMP || APIC_IO */
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#ifdef LOCORE
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/*
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* Protects the IO APIC, 8259 PIC, imen, and apic_imen
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*/
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#define ICU_LOCK MTX_LOCK_SPIN(icu_lock, 0)
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#define ICU_UNLOCK MTX_UNLOCK_SPIN(icu_lock)
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#else /* LOCORE */
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/*
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* Type of the first (asm) part of an interrupt handler.
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*/
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typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
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typedef void unpendhand_t __P((void));
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#define IDTVEC(name) __CONCAT(X,name)
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extern u_long *intr_countp[]; /* pointers into intrcnt[] */
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extern driver_intr_t *intr_handler[]; /* C entry points of intr handlers */
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extern struct ithd *ithds[];
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extern void *intr_unit[]; /* cookies to pass to intr handlers */
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extern struct mtx icu_lock;
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inthand_t
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IDTVEC(fastintr0), IDTVEC(fastintr1),
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IDTVEC(fastintr2), IDTVEC(fastintr3),
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IDTVEC(fastintr4), IDTVEC(fastintr5),
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IDTVEC(fastintr6), IDTVEC(fastintr7),
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IDTVEC(fastintr8), IDTVEC(fastintr9),
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IDTVEC(fastintr10), IDTVEC(fastintr11),
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IDTVEC(fastintr12), IDTVEC(fastintr13),
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IDTVEC(fastintr14), IDTVEC(fastintr15);
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inthand_t
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IDTVEC(intr0), IDTVEC(intr1), IDTVEC(intr2), IDTVEC(intr3),
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IDTVEC(intr4), IDTVEC(intr5), IDTVEC(intr6), IDTVEC(intr7),
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IDTVEC(intr8), IDTVEC(intr9), IDTVEC(intr10), IDTVEC(intr11),
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IDTVEC(intr12), IDTVEC(intr13), IDTVEC(intr14), IDTVEC(intr15);
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unpendhand_t
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IDTVEC(fastunpend0), IDTVEC(fastunpend1), IDTVEC(fastunpend2),
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IDTVEC(fastunpend3), IDTVEC(fastunpend4), IDTVEC(fastunpend5),
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IDTVEC(fastunpend6), IDTVEC(fastunpend7), IDTVEC(fastunpend8),
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IDTVEC(fastunpend9), IDTVEC(fastunpend10), IDTVEC(fastunpend11),
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IDTVEC(fastunpend12), IDTVEC(fastunpend13), IDTVEC(fastunpend14),
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IDTVEC(fastunpend15), IDTVEC(fastunpend16), IDTVEC(fastunpend17),
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IDTVEC(fastunpend18), IDTVEC(fastunpend19), IDTVEC(fastunpend20),
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IDTVEC(fastunpend21), IDTVEC(fastunpend22), IDTVEC(fastunpend23),
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IDTVEC(fastunpend24), IDTVEC(fastunpend25), IDTVEC(fastunpend26),
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IDTVEC(fastunpend27), IDTVEC(fastunpend28), IDTVEC(fastunpend29),
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IDTVEC(fastunpend30), IDTVEC(fastunpend31);
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#if defined(SMP) || defined(APIC_IO)
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inthand_t
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IDTVEC(fastintr16), IDTVEC(fastintr17),
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IDTVEC(fastintr18), IDTVEC(fastintr19),
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IDTVEC(fastintr20), IDTVEC(fastintr21),
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IDTVEC(fastintr22), IDTVEC(fastintr23),
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IDTVEC(fastintr24), IDTVEC(fastintr25),
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IDTVEC(fastintr26), IDTVEC(fastintr27),
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IDTVEC(fastintr28), IDTVEC(fastintr29),
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IDTVEC(fastintr30), IDTVEC(fastintr31);
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inthand_t
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IDTVEC(intr16), IDTVEC(intr17), IDTVEC(intr18), IDTVEC(intr19),
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IDTVEC(intr20), IDTVEC(intr21), IDTVEC(intr22), IDTVEC(intr23),
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IDTVEC(intr24), IDTVEC(intr25), IDTVEC(intr26), IDTVEC(intr27),
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IDTVEC(intr28), IDTVEC(intr29), IDTVEC(intr30), IDTVEC(intr31);
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inthand_t
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Xinvltlb, /* TLB shootdowns */
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Xhardclock, /* Forward hardclock() */
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Xstatclock, /* Forward statclock() */
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Xcpuast, /* Additional software trap on other cpu */
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Xcpustop, /* CPU stops & waits for another CPU to restart it */
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Xspuriousint, /* handle APIC "spurious INTs" */
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Xrendezvous; /* handle CPU rendezvous */
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#ifdef TEST_TEST1
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inthand_t
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Xtest1; /* 'fake' HWI at top of APIC prio 0x3x, 32+31 = 0x3f */
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#endif /** TEST_TEST1 */
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#endif /* SMP || APIC_IO */
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#ifdef PC98
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#define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
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#define ICU_SLAVEID 7
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#else
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#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
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#define ICU_SLAVEID 2
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#endif
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#ifdef APIC_IO
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/*
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* This is to accommodate "mixed-mode" programming for
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* motherboards that don't connect the 8254 to the IO APIC.
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*/
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#define AUTO_EOI_1 1
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#endif
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#define NR_INTRNAMES (1 + ICU_LEN + 2 * ICU_LEN)
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void isa_defaultirq(void);
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int isa_nmi(int cd);
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int icu_setup(int intr, driver_intr_t *func, void *arg, int flags);
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int icu_unset(int intr, driver_intr_t *handler);
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void icu_reinit(void);
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/*
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* WARNING: These are internal functions and not to be used by device drivers!
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* They are subject to change without notice.
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*/
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int inthand_add(const char *name, int irq, driver_intr_t handler, void *arg,
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enum intr_type flags, void **cookiep);
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int inthand_remove(void *cookie);
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void sched_ithd(void *dummy);
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void call_fast_unpend(int irq);
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#endif /* LOCORE */
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#endif /* _KERNEL */
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#endif /* !_I386_ISA_INTR_MACHDEP_H_ */
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