c7ecc129d7
ISDN4BSD is the work of our brand-new comitter: Hellmuth Michaelis, who has done a tremendous amount of work to bring us this far. There are still some outstanding issues and files to bring into the tree, and for now it will be needed to pick up all the extra docs from the isdn4bsd release. It is probably also a very good idea to subscribe to the isdn@freebsd.org mailing list before you try this out. These files correspond to release "beta Version 0.70.00 / December 1998" from Hellmuth.
680 lines
17 KiB
C
680 lines
17 KiB
C
/*
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* Copyright (c) 1997, 1998 Hellmuth Michaelis. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*---------------------------------------------------------------------------
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*
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* i4b_isac.c - i4b siemens isdn chipset driver ISAC handler
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* ---------------------------------------------------------
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*
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* $Id: i4b_isac.c,v 1.28 1998/12/05 18:04:41 hm Exp $
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*
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* last edit-date: [Sat Dec 5 18:23:59 1998]
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*
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*---------------------------------------------------------------------------*/
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#ifdef __FreeBSD__
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#include "isic.h"
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#else
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#define NISIC 1 /* non-FreeBSD handles this via config(8) */
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#endif
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#if NISIC > 0
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#ifdef __FreeBSD__
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#include "opt_i4b.h"
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#endif
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#include <sys/param.h>
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#if defined(__FreeBSD__) && __FreeBSD__ >= 3
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#include <sys/ioccom.h>
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#else
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#include <sys/ioctl.h>
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#endif
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/mbuf.h>
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#include <machine/stdarg.h>
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#ifdef __FreeBSD__
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#include <machine/clock.h>
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#include <i386/isa/isa_device.h>
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#else
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#include <machine/bus.h>
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#include <sys/device.h>
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#endif
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#include <sys/socket.h>
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#include <net/if.h>
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#ifdef __FreeBSD__
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#include <machine/i4b_debug.h>
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#include <machine/i4b_ioctl.h>
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#include <machine/i4b_trace.h>
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#else
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#include <i4b/i4b_debug.h>
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#include <i4b/i4b_ioctl.h>
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#include <i4b/i4b_trace.h>
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#endif
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#include <i4b/layer1/i4b_l1.h>
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#include <i4b/layer1/i4b_isac.h>
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#include <i4b/layer1/i4b_hscx.h>
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#include <i4b/include/i4b_global.h>
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#include <i4b/include/i4b_l1l2.h>
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#include <i4b/include/i4b_mbuf.h>
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static u_char isic_isac_exir_hdlr(register struct isic_softc *sc, u_char exir);
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static void isic_isac_ind_hdlr(register struct isic_softc *sc, int ind);
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/*---------------------------------------------------------------------------*
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* ISAC interrupt service routine
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*---------------------------------------------------------------------------*/
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void
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isic_isac_irq(struct isic_softc *sc, int ista)
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{
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register u_char c = 0;
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DBGL1(L1_F_MSG, "isic_isac_irq", ("unit %d: ista = 0x%02x\n", sc->sc_unit, ista));
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if(ista & ISAC_ISTA_EXI) /* extended interrupt */
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{
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c |= isic_isac_exir_hdlr(sc, ISAC_READ(I_EXIR));
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}
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if(ista & ISAC_ISTA_RME) /* receive message end */
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{
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register int rest;
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u_char rsta;
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/* get rx status register */
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rsta = ISAC_READ(I_RSTA);
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if((rsta & ISAC_RSTA_MASK) != 0x20)
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{
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int error = 0;
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if(!(rsta & ISAC_RSTA_CRC)) /* CRC error */
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{
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error++;
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DBGL1(L1_I_ERR, "isic_isac_irq", ("unit %d: CRC error\n", sc->sc_unit));
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}
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if(rsta & ISAC_RSTA_RDO) /* ReceiveDataOverflow */
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{
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error++;
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DBGL1(L1_I_ERR, "isic_isac_irq", ("unit %d: Data Overrun error\n", sc->sc_unit));
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}
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if(rsta & ISAC_RSTA_RAB) /* ReceiveABorted */
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{
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error++;
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DBGL1(L1_I_ERR, "isic_isac_irq", ("unit %d: Receive Aborted error\n", sc->sc_unit));
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}
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if(error == 0)
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DBGL1(L1_I_ERR, "isic_isac_irq", ("unit %d: RME unknown error, RSTA = 0x%02x!\n", sc->sc_unit, rsta));
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i4b_Dfreembuf(sc->sc_ibuf);
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c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
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sc->sc_ibuf = NULL;
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sc->sc_ib = NULL;
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sc->sc_ilen = 0;
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ISAC_WRITE(I_CMDR, ISAC_CMDR_RMC|ISAC_CMDR_RRES);
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ISACCMDRWRDELAY();
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return;
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}
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rest = (ISAC_READ(I_RBCL) & (ISAC_FIFO_LEN-1));
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if(rest == 0)
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rest = ISAC_FIFO_LEN;
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if(sc->sc_ibuf == NULL)
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{
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if((sc->sc_ibuf = i4b_Dgetmbuf(rest)) != NULL)
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sc->sc_ib = sc->sc_ibuf->m_data;
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else
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panic("isic_isac_irq: RME, i4b_Dgetmbuf returns NULL!\n");
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sc->sc_ilen = 0;
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}
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if(sc->sc_ilen <= (MAX_DFRAME_LEN - rest))
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{
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ISAC_RDFIFO(sc->sc_ib, rest);
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sc->sc_ilen += rest;
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sc->sc_ibuf->m_pkthdr.len =
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sc->sc_ibuf->m_len = sc->sc_ilen;
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if(sc->sc_trace & TRACE_D_RX)
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{
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i4b_trace_hdr_t hdr;
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hdr.unit = sc->sc_unit;
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hdr.type = TRC_CH_D;
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hdr.dir = FROM_NT;
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hdr.count = ++sc->sc_trace_dcount;
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MICROTIME(hdr.time);
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MPH_Trace_Ind(&hdr, sc->sc_ibuf->m_len, sc->sc_ibuf->m_data);
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}
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c |= ISAC_CMDR_RMC;
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if(sc->sc_enabled)
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PH_Data_Ind(sc->sc_unit, sc->sc_ibuf);
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else
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i4b_Dfreembuf(sc->sc_ibuf);
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}
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else
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{
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DBGL1(L1_I_ERR, "isic_isac_irq", ("RME, input buffer overflow!\n"));
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i4b_Dfreembuf(sc->sc_ibuf);
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c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
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}
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sc->sc_ibuf = NULL;
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sc->sc_ib = NULL;
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sc->sc_ilen = 0;
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}
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if(ista & ISAC_ISTA_RPF) /* receive fifo full */
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{
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if(sc->sc_ibuf == NULL)
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{
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if((sc->sc_ibuf = i4b_Dgetmbuf(MAX_DFRAME_LEN)) != NULL)
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sc->sc_ib= sc->sc_ibuf->m_data;
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else
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panic("isic_isac_irq: RPF, i4b_Dgetmbuf returns NULL!\n");
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sc->sc_ilen = 0;
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}
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if(sc->sc_ilen <= (MAX_DFRAME_LEN - ISAC_FIFO_LEN))
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{
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ISAC_RDFIFO(sc->sc_ib, ISAC_FIFO_LEN);
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sc->sc_ilen += ISAC_FIFO_LEN;
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sc->sc_ib += ISAC_FIFO_LEN;
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c |= ISAC_CMDR_RMC;
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}
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else
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{
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DBGL1(L1_I_ERR, "isic_isac_irq", ("RPF, input buffer overflow!\n"));
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i4b_Dfreembuf(sc->sc_ibuf);
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sc->sc_ibuf = NULL;
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sc->sc_ib = NULL;
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sc->sc_ilen = 0;
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c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
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}
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}
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if(ista & ISAC_ISTA_XPR) /* transmit fifo empty (XPR bit set) */
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{
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if((sc->sc_obuf2 != NULL) && (sc->sc_obuf == NULL))
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{
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sc->sc_freeflag = sc->sc_freeflag2;
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sc->sc_obuf = sc->sc_obuf2;
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sc->sc_op = sc->sc_obuf->m_data;
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sc->sc_ol = sc->sc_obuf->m_len;
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sc->sc_obuf2 = NULL;
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#ifdef NOTDEF
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printf("ob2=%x, op=%x, ol=%d, f=%d #",
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sc->sc_obuf,
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sc->sc_op,
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sc->sc_ol,
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sc->sc_state);
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#endif
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}
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else
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{
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#ifdef NOTDEF
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printf("ob=%x, op=%x, ol=%d, f=%d #",
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sc->sc_obuf,
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sc->sc_op,
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sc->sc_ol,
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sc->sc_state);
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#endif
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}
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if(sc->sc_obuf)
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{
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ISAC_WRFIFO(sc->sc_op, min(sc->sc_ol, ISAC_FIFO_LEN));
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if(sc->sc_ol > ISAC_FIFO_LEN) /* length > 32 ? */
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{
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sc->sc_op += ISAC_FIFO_LEN; /* bufferptr+32 */
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sc->sc_ol -= ISAC_FIFO_LEN; /* length - 32 */
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c |= ISAC_CMDR_XTF; /* set XTF bit */
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}
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else
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{
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if(sc->sc_freeflag)
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{
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i4b_Dfreembuf(sc->sc_obuf);
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sc->sc_freeflag = 0;
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}
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sc->sc_obuf = NULL;
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sc->sc_op = NULL;
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sc->sc_ol = 0;
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c |= ISAC_CMDR_XTF | ISAC_CMDR_XME;
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}
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}
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else
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{
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sc->sc_state &= ~ISAC_TX_ACTIVE;
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}
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}
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if(ista & ISAC_ISTA_CISQ) /* channel status change CISQ */
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{
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register u_char ci;
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/* get command/indication rx register*/
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ci = ISAC_READ(I_CIRR);
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/* if S/Q IRQ, read SQC reg to clr SQC IRQ */
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if(ci & ISAC_CIRR_SQC)
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(void) ISAC_READ(I_SQRR);
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/* C/I code change IRQ (flag already cleared by CIRR read) */
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if(ci & ISAC_CIRR_CIC0)
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isic_isac_ind_hdlr(sc, (ci >> 2) & 0xf);
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}
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if(c)
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{
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ISAC_WRITE(I_CMDR, c);
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ISACCMDRWRDELAY();
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}
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}
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/*---------------------------------------------------------------------------*
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* ISAC L1 Extended IRQ handler
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*---------------------------------------------------------------------------*/
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static u_char
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isic_isac_exir_hdlr(register struct isic_softc *sc, u_char exir)
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{
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u_char c = 0;
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if(exir & ISAC_EXIR_XMR)
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{
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Tx Message Repeat\n"));
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c |= ISAC_CMDR_XRES;
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}
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if(exir & ISAC_EXIR_XDU)
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{
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Tx Data Underrun\n"));
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c |= ISAC_CMDR_XRES;
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}
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if(exir & ISAC_EXIR_PCE)
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{
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Protocol Error\n"));
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}
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if(exir & ISAC_EXIR_RFO)
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{
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Rx Frame Overflow\n"));
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c |= ISAC_CMDR_RMC|ISAC_CMDR_RRES;
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}
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if(exir & ISAC_EXIR_SOV)
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{
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Sync Xfer Overflow\n"));
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}
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if(exir & ISAC_EXIR_MOS)
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{
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DBGL1(L1_I_ERR, "L1 isic_isac_exir_hdlr", ("EXIRQ Monitor Status\n"));
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}
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if(exir & ISAC_EXIR_SAW)
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{
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/* cannot happen, STCR:TSF is set to 0 */
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Subscriber Awake\n"));
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}
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if(exir & ISAC_EXIR_WOV)
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{
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/* cannot happen, STCR:TSF is set to 0 */
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DBGL1(L1_I_ERR, "isic_isac_exir_hdlr", ("EXIRQ Watchdog Timer Overflow\n"));
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}
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return(c);
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}
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/*---------------------------------------------------------------------------*
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* ISAC L1 Indication handler
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*---------------------------------------------------------------------------*/
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static void
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isic_isac_ind_hdlr(register struct isic_softc *sc, int ind)
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{
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register int event;
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switch(ind)
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{
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case ISAC_CIRR_IAI8:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx AI8 in state %s\n", isic_printstate(sc)));
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if(sc->sc_bustyp == BUS_TYPE_IOM2)
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isic_isac_l1_cmd(sc, CMD_AR8);
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event = EV_INFO48;
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MPH_Status_Ind(sc->sc_unit, STI_L1STAT, LAYER_ACTIVE);
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break;
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case ISAC_CIRR_IAI10:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx AI10 in state %s\n", isic_printstate(sc)));
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if(sc->sc_bustyp == BUS_TYPE_IOM2)
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isic_isac_l1_cmd(sc, CMD_AR10);
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event = EV_INFO410;
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MPH_Status_Ind(sc->sc_unit, STI_L1STAT, LAYER_ACTIVE);
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break;
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case ISAC_CIRR_IRSY:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx RSY in state %s\n", isic_printstate(sc)));
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event = EV_RSY;
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break;
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case ISAC_CIRR_IPU:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx PU in state %s\n", isic_printstate(sc)));
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event = EV_PU;
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break;
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case ISAC_CIRR_IDR:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx DR in state %s\n", isic_printstate(sc)));
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isic_isac_l1_cmd(sc, CMD_DIU);
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event = EV_DR;
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break;
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case ISAC_CIRR_IDID:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx DID in state %s\n", isic_printstate(sc)));
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event = EV_INFO0;
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MPH_Status_Ind(sc->sc_unit, STI_L1STAT, LAYER_IDLE);
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break;
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case ISAC_CIRR_IDIS:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx DIS in state %s\n", isic_printstate(sc)));
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event = EV_DIS;
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break;
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case ISAC_CIRR_IEI:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx EI in state %s\n", isic_printstate(sc)));
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isic_isac_l1_cmd(sc, CMD_DIU);
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event = EV_EI;
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break;
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case ISAC_CIRR_IARD:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx ARD in state %s\n", isic_printstate(sc)));
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event = EV_INFO2;
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break;
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case ISAC_CIRR_ITI:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx TI in state %s\n", isic_printstate(sc)));
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event = EV_INFO0;
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break;
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case ISAC_CIRR_IATI:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx ATI in state %s\n", isic_printstate(sc)));
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event = EV_INFO0;
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break;
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case ISAC_CIRR_ISD:
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DBGL1(L1_I_CICO, "isic_isac_ind_hdlr", ("rx SD in state %s\n", isic_printstate(sc)));
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event = EV_INFO0;
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break;
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default:
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DBGL1(L1_I_ERR, "isic_isac_ind_hdlr", ("UNKNOWN Indication 0x%x in state %s\n", ind, isic_printstate(sc)));
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event = EV_INFO0;
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break;
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}
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isic_next_state(sc, event);
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}
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/*---------------------------------------------------------------------------*
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* execute a layer 1 command
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*---------------------------------------------------------------------------*/
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void
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isic_isac_l1_cmd(struct isic_softc *sc, int command)
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{
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u_char cmd;
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#ifdef I4B_SMP_WORKAROUND
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/* XXXXXXXXXXXXXXXXXXX */
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/*
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* patch from Wolfgang Helbig:
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*
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* Here is a patch that makes i4b work on an SMP:
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* The card (TELES 16.3) didn't interrupt on an SMP machine.
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* This is a gross workaround, but anyway it works *and* provides
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* some information as how to finally fix this problem.
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*/
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HSCX_WRITE(0, H_MASK, 0xff);
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HSCX_WRITE(1, H_MASK, 0xff);
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ISAC_WRITE(I_MASK, 0xff);
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DELAY(100);
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HSCX_WRITE(0, H_MASK, HSCX_A_IMASK);
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HSCX_WRITE(1, H_MASK, HSCX_B_IMASK);
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ISAC_WRITE(I_MASK, ISAC_IMASK);
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/* XXXXXXXXXXXXXXXXXXX */
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#endif /* I4B_SMP_WORKAROUND */
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if(command < 0 || command > CMD_ILL)
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{
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DBGL1(L1_I_ERR, "isic_isac_l1_cmd", ("illegal cmd 0x%x in state %s\n", command, isic_printstate(sc)));
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return;
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}
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if(sc->sc_bustyp == BUS_TYPE_IOM2)
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cmd = ISAC_CIX0_LOW;
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else
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cmd = 0;
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switch(command)
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{
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case CMD_TIM:
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DBGL1(L1_I_CICO, "isic_isac_l1_cmd", ("tx TIM in state %s\n", isic_printstate(sc)));
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cmd |= (ISAC_CIXR_CTIM << 2);
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break;
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case CMD_RS:
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DBGL1(L1_I_CICO, "isic_isac_l1_cmd", ("tx RS in state %s\n", isic_printstate(sc)));
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cmd |= (ISAC_CIXR_CRS << 2);
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break;
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case CMD_AR8:
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DBGL1(L1_I_CICO, "isic_isac_l1_cmd", ("tx AR8 in state %s\n", isic_printstate(sc)));
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cmd |= (ISAC_CIXR_CAR8 << 2);
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break;
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case CMD_AR10:
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DBGL1(L1_I_CICO, "isic_isac_l1_cmd", ("tx AR10 in state %s\n", isic_printstate(sc)));
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cmd |= (ISAC_CIXR_CAR10 << 2);
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break;
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case CMD_DIU:
|
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DBGL1(L1_I_CICO, "isic_isac_l1_cmd", ("tx DIU in state %s\n", isic_printstate(sc)));
|
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cmd |= (ISAC_CIXR_CDIU << 2);
|
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break;
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}
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ISAC_WRITE(I_CIXR, cmd);
|
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}
|
|
|
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/*---------------------------------------------------------------------------*
|
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* L1 ISAC initialization
|
|
*---------------------------------------------------------------------------*/
|
|
int
|
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isic_isac_init(struct isic_softc *sc)
|
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{
|
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ISAC_IMASK = 0xff; /* disable all irqs */
|
|
|
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ISAC_WRITE(I_MASK, ISAC_IMASK);
|
|
|
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if(sc->sc_bustyp != BUS_TYPE_IOM2)
|
|
{
|
|
DBGL1(L1_I_SETUP, "isic_isac_setup", ("configuring for IOM-1 mode\n"));
|
|
|
|
/* ADF2: Select mode IOM-1 */
|
|
ISAC_WRITE(I_ADF2, 0x00);
|
|
|
|
/* SPCR: serial port control register:
|
|
* SPU - software power up = 0
|
|
* SAC - SIP port high Z
|
|
* SPM - timing mode 0
|
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* TLP - test loop = 0
|
|
* C1C, C2C - B1 and B2 switched to/from SPa
|
|
*/
|
|
ISAC_WRITE(I_SPCR, ISAC_SPCR_C1C1|ISAC_SPCR_C2C1);
|
|
|
|
/* SQXR: S/Q channel xmit register:
|
|
* SQIE - S/Q IRQ enable = 0
|
|
* SQX1-4 - Fa bits = 1
|
|
*/
|
|
ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
|
|
|
|
/* ADF1: additional feature reg 1:
|
|
* WTC - watchdog = 0
|
|
* TEM - test mode = 0
|
|
* PFS - pre-filter = 0
|
|
* CFS - IOM clock/frame always active
|
|
* FSC1/2 - polarity of 8kHz strobe
|
|
* ITF - interframe fill = idle
|
|
*/
|
|
ISAC_WRITE(I_ADF1, ISAC_ADF1_FC2); /* ADF1 */
|
|
|
|
/* STCR: sync transfer control reg:
|
|
* TSF - terminal secific functions = 0
|
|
* TBA - TIC bus address = 7
|
|
* STx/SCx = 0
|
|
*/
|
|
ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
|
|
|
|
/* MODE: Mode Register:
|
|
* MDSx - transparent mode 2
|
|
* TMD - timer mode = external
|
|
* RAC - Receiver enabled
|
|
* DIMx - digital i/f mode
|
|
*/
|
|
ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
|
|
}
|
|
else
|
|
{
|
|
DBGL1(L1_I_SETUP, "isic_isac_setup", ("configuring for IOM-2 mode\n"));
|
|
|
|
/* ADF2: Select mode IOM-2 */
|
|
ISAC_WRITE(I_ADF2, ISAC_ADF2_IMS);
|
|
|
|
/* SPCR: serial port control register:
|
|
* SPU - software power up = 0
|
|
* SPM - timing mode 0
|
|
* TLP - test loop = 0
|
|
* C1C, C2C - B1 + C1 and B2 + IC2 monitoring
|
|
*/
|
|
ISAC_WRITE(I_SPCR, 0x00);
|
|
|
|
/* SQXR: S/Q channel xmit register:
|
|
* IDC - IOM direction = 0 (master)
|
|
* CFS - Config Select = 0 (clock always active)
|
|
* CI1E - C/I channel 1 IRQ enable = 0
|
|
* SQIE - S/Q IRQ enable = 0
|
|
* SQX1-4 - Fa bits = 1
|
|
*/
|
|
ISAC_WRITE(I_SQXR, ISAC_SQXR_SQX1|ISAC_SQXR_SQX2|ISAC_SQXR_SQX3|ISAC_SQXR_SQX4);
|
|
|
|
/* ADF1: additional feature reg 1:
|
|
* WTC - watchdog = 0
|
|
* TEM - test mode = 0
|
|
* PFS - pre-filter = 0
|
|
* IOF - IOM i/f off = 0
|
|
* ITF - interframe fill = idle
|
|
*/
|
|
ISAC_WRITE(I_ADF1, 0x00);
|
|
|
|
/* STCR: sync transfer control reg:
|
|
* TSF - terminal secific functions = 0
|
|
* TBA - TIC bus address = 7
|
|
* STx/SCx = 0
|
|
*/
|
|
ISAC_WRITE(I_STCR, ISAC_STCR_TBA2|ISAC_STCR_TBA1|ISAC_STCR_TBA0);
|
|
|
|
/* MODE: Mode Register:
|
|
* MDSx - transparent mode 2
|
|
* TMD - timer mode = external
|
|
* RAC - Receiver enabled
|
|
* DIMx - digital i/f mode
|
|
*/
|
|
ISAC_WRITE(I_MODE, ISAC_MODE_MDS2|ISAC_MODE_MDS1|ISAC_MODE_RAC|ISAC_MODE_DIM0);
|
|
}
|
|
|
|
#ifdef NOTDEF
|
|
/*
|
|
* XXX a transmitter reset causes an ISAC tx IRQ which will not
|
|
* be serviced at attach time under some circumstances leaving
|
|
* the associated IRQ line on the ISA bus active. This prevents
|
|
* any further interrupts to be serviced because no low -> high
|
|
* transition can take place anymore. (-hm)
|
|
*/
|
|
|
|
/* command register:
|
|
* RRES - HDLC receiver reset
|
|
* XRES - transmitter reset
|
|
*/
|
|
ISAC_WRITE(I_CMDR, ISAC_CMDR_RRES|ISAC_CMDR_XRES);
|
|
ISACCMDRWRDELAY();
|
|
#endif
|
|
|
|
/* enabled interrupts:
|
|
* ===================
|
|
* RME - receive message end
|
|
* RPF - receive pool full
|
|
* XPR - transmit pool ready
|
|
* CISQ - CI or S/Q channel change
|
|
* EXI - extended interrupt
|
|
*/
|
|
|
|
ISAC_IMASK = ISAC_MASK_RSC | /* auto mode only */
|
|
ISAC_MASK_TIN | /* timer irq */
|
|
ISAC_MASK_SIN; /* sync xfer irq */
|
|
|
|
ISAC_WRITE(I_MASK, ISAC_IMASK);
|
|
|
|
return(0);
|
|
}
|
|
|
|
#endif /* NISIC > 0 */
|