John Baldwin c2175767b7 Intel QPI chipsets actually provide two extra "non-core" PCI buses that ... provide PCI devices for various hardware such as memory controllers, etc. These PCI buses are not enumerated via ACPI however. Add qpi(4) psuedo bus and Host-PCI bridge drivers to enumerate these buses. Currently the driver uses the CPU ID to determine the bridges' presence. In collaboration with: Joseph Golio @ Isilon Systems MFC after: 2 weeks		2010-08-25 19:12:05 +00:00
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acpica	When performing a sanity check on the SRAT table to ensure that each	2010-07-29 17:37:35 +00:00
bios
cpufreq	Core i5, same as previously Core2Duo, found to not set P-state for single	2010-06-19 13:09:42 +00:00
isa	Fix several un-/signedness bugs of r210290 and r210293. Add one more check.	2010-07-20 15:48:29 +00:00
pci	Intel QPI chipsets actually provide two extra "non-core" PCI buses that	2010-08-25 19:12:05 +00:00
x86	Enable timer interrupt before starting timer. This allows to handle very	2010-08-24 16:08:01 +00:00