398 lines
12 KiB
C
398 lines
12 KiB
C
/*-
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* Copyright (c) 1997, 1998, 1999
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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* Copyright (c) 2006 Bernd Walter. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* driver for RealTek 8305 pseudo PHYs
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/bus.h>
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#include <sys/taskqueue.h> /* XXXGL: if_rlreg.h contamination */
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/if_media.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include "miidevs.h"
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#include <machine/bus.h>
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#include <dev/rl/if_rlreg.h>
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#include "miibus_if.h"
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//#define RL_DEBUG
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#define RL_VLAN
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static int rlswitch_probe(device_t);
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static int rlswitch_attach(device_t);
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static device_method_t rlswitch_methods[] = {
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/* device interface */
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DEVMETHOD(device_probe, rlswitch_probe),
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DEVMETHOD(device_attach, rlswitch_attach),
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DEVMETHOD(device_detach, mii_phy_detach),
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DEVMETHOD(device_shutdown, bus_generic_shutdown),
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DEVMETHOD_END
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};
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static devclass_t rlswitch_devclass;
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static driver_t rlswitch_driver = {
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"rlswitch",
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rlswitch_methods,
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sizeof(struct mii_softc)
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};
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DRIVER_MODULE(rlswitch, miibus, rlswitch_driver, rlswitch_devclass, 0, 0);
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static int rlswitch_service(struct mii_softc *, struct mii_data *, int);
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static void rlswitch_status(struct mii_softc *);
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#ifdef RL_DEBUG
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static void rlswitch_phydump(device_t dev);
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#endif
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static const struct mii_phydesc rlswitches[] = {
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MII_PHY_DESC(REALTEK, RTL8305SC),
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MII_PHY_END
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};
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static const struct mii_phy_funcs rlswitch_funcs = {
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rlswitch_service,
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rlswitch_status,
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mii_phy_reset
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};
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static int
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rlswitch_probe(device_t dev)
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{
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int rv;
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rv = mii_phy_dev_probe(dev, rlswitches, BUS_PROBE_DEFAULT);
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if (rv <= 0)
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return (rv);
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return (ENXIO);
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}
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static int
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rlswitch_attach(device_t dev)
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{
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struct mii_softc *sc;
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sc = device_get_softc(dev);
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/*
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* We handle all pseudo PHYs in a single instance.
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*/
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mii_phy_dev_attach(dev, MIIF_NOISOLATE | MIIF_NOMANPAUSE,
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&rlswitch_funcs, 0);
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sc->mii_capabilities = BMSR_100TXFDX & sc->mii_capmask;
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device_printf(dev, " ");
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mii_phy_add_media(sc);
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printf("\n");
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#ifdef RL_DEBUG
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rlswitch_phydump(dev);
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#endif
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#ifdef RL_VLAN
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int val;
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/* Global Control 0 */
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val = 0;
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val |= 0 << 10; /* enable 802.1q VLAN Tag support */
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val |= 0 << 9; /* enable VLAN ingress filtering */
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val |= 1 << 8; /* disable VLAN tag admit control */
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val |= 1 << 6; /* internal use */
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val |= 1 << 5; /* internal use */
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val |= 1 << 4; /* internal use */
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val |= 1 << 3; /* internal use */
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val |= 1 << 1; /* reserved */
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MIIBUS_WRITEREG(sc->mii_dev, 0, 16, val);
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/* Global Control 2 */
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val = 0;
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val |= 1 << 15; /* reserved */
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val |= 0 << 14; /* enable 1552 Bytes support */
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val |= 1 << 13; /* enable broadcast input drop */
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val |= 1 << 12; /* forward reserved control frames */
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val |= 1 << 11; /* disable forwarding unicast frames to other VLAN's */
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val |= 1 << 10; /* disable forwarding ARP broadcasts to other VLAN's */
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val |= 1 << 9; /* enable 48 pass 1 */
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val |= 0 << 8; /* enable VLAN */
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val |= 1 << 7; /* reserved */
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val |= 1 << 6; /* enable defer */
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val |= 1 << 5; /* 43ms LED blink time */
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val |= 3 << 3; /* 16:1 queue weight */
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val |= 1 << 2; /* disable broadcast storm control */
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val |= 1 << 1; /* enable power-on LED blinking */
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val |= 1 << 0; /* reserved */
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MIIBUS_WRITEREG(sc->mii_dev, 0, 18, val);
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/* Port 0 Control Register 0 */
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val = 0;
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val |= 1 << 15; /* reserved */
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val |= 1 << 11; /* drop received packets with wrong VLAN tag */
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val |= 1 << 10; /* disable 802.1p priority classification */
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val |= 1 << 9; /* disable diffserv priority classification */
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val |= 1 << 6; /* internal use */
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val |= 3 << 4; /* internal use */
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val |= 1 << 3; /* internal use */
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val |= 1 << 2; /* internal use */
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val |= 1 << 0; /* remove VLAN tags on output */
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MIIBUS_WRITEREG(sc->mii_dev, 0, 22, val);
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/* Port 1 Control Register 0 */
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val = 0;
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val |= 1 << 15; /* reserved */
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val |= 1 << 11; /* drop received packets with wrong VLAN tag */
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val |= 1 << 10; /* disable 802.1p priority classification */
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val |= 1 << 9; /* disable diffserv priority classification */
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val |= 1 << 6; /* internal use */
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val |= 3 << 4; /* internal use */
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val |= 1 << 3; /* internal use */
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val |= 1 << 2; /* internal use */
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val |= 1 << 0; /* remove VLAN tags on output */
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MIIBUS_WRITEREG(sc->mii_dev, 1, 22, val);
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/* Port 2 Control Register 0 */
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val = 0;
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val |= 1 << 15; /* reserved */
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val |= 1 << 11; /* drop received packets with wrong VLAN tag */
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val |= 1 << 10; /* disable 802.1p priority classification */
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val |= 1 << 9; /* disable diffserv priority classification */
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val |= 1 << 6; /* internal use */
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val |= 3 << 4; /* internal use */
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val |= 1 << 3; /* internal use */
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val |= 1 << 2; /* internal use */
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val |= 1 << 0; /* remove VLAN tags on output */
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MIIBUS_WRITEREG(sc->mii_dev, 2, 22, val);
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/* Port 3 Control Register 0 */
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val = 0;
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val |= 1 << 15; /* reserved */
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val |= 1 << 11; /* drop received packets with wrong VLAN tag */
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val |= 1 << 10; /* disable 802.1p priority classification */
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val |= 1 << 9; /* disable diffserv priority classification */
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val |= 1 << 6; /* internal use */
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val |= 3 << 4; /* internal use */
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val |= 1 << 3; /* internal use */
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val |= 1 << 2; /* internal use */
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val |= 1 << 0; /* remove VLAN tags on output */
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MIIBUS_WRITEREG(sc->mii_dev, 3, 22, val);
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/* Port 4 (system port) Control Register 0 */
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val = 0;
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val |= 1 << 15; /* reserved */
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val |= 0 << 11; /* don't drop received packets with wrong VLAN tag */
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val |= 1 << 10; /* disable 802.1p priority classification */
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val |= 1 << 9; /* disable diffserv priority classification */
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val |= 1 << 6; /* internal use */
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val |= 3 << 4; /* internal use */
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val |= 1 << 3; /* internal use */
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val |= 1 << 2; /* internal use */
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val |= 2 << 0; /* add VLAN tags for untagged packets on output */
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MIIBUS_WRITEREG(sc->mii_dev, 4, 22, val);
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/* Port 0 Control Register 1 and VLAN A */
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val = 0;
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val |= 0x0 << 12; /* Port 0 VLAN Index */
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val |= 1 << 11; /* internal use */
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val |= 1 << 10; /* internal use */
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val |= 1 << 9; /* internal use */
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val |= 1 << 7; /* internal use */
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val |= 1 << 6; /* internal use */
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val |= 0x11 << 0; /* VLAN A membership */
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MIIBUS_WRITEREG(sc->mii_dev, 0, 24, val);
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/* Port 0 Control Register 2 and VLAN A */
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val = 0;
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val |= 1 << 15; /* internal use */
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val |= 1 << 14; /* internal use */
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val |= 1 << 13; /* internal use */
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val |= 1 << 12; /* internal use */
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val |= 0x100 << 0; /* VLAN A ID */
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MIIBUS_WRITEREG(sc->mii_dev, 0, 25, val);
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/* Port 1 Control Register 1 and VLAN B */
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val = 0;
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val |= 0x1 << 12; /* Port 1 VLAN Index */
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val |= 1 << 11; /* internal use */
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val |= 1 << 10; /* internal use */
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val |= 1 << 9; /* internal use */
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val |= 1 << 7; /* internal use */
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val |= 1 << 6; /* internal use */
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val |= 0x12 << 0; /* VLAN B membership */
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MIIBUS_WRITEREG(sc->mii_dev, 1, 24, val);
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/* Port 1 Control Register 2 and VLAN B */
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val = 0;
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val |= 1 << 15; /* internal use */
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val |= 1 << 14; /* internal use */
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val |= 1 << 13; /* internal use */
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val |= 1 << 12; /* internal use */
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val |= 0x101 << 0; /* VLAN B ID */
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MIIBUS_WRITEREG(sc->mii_dev, 1, 25, val);
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/* Port 2 Control Register 1 and VLAN C */
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val = 0;
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val |= 0x2 << 12; /* Port 2 VLAN Index */
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val |= 1 << 11; /* internal use */
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val |= 1 << 10; /* internal use */
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val |= 1 << 9; /* internal use */
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val |= 1 << 7; /* internal use */
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val |= 1 << 6; /* internal use */
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val |= 0x14 << 0; /* VLAN C membership */
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MIIBUS_WRITEREG(sc->mii_dev, 2, 24, val);
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/* Port 2 Control Register 2 and VLAN C */
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val = 0;
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val |= 1 << 15; /* internal use */
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val |= 1 << 14; /* internal use */
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val |= 1 << 13; /* internal use */
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val |= 1 << 12; /* internal use */
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val |= 0x102 << 0; /* VLAN C ID */
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MIIBUS_WRITEREG(sc->mii_dev, 2, 25, val);
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/* Port 3 Control Register 1 and VLAN D */
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val = 0;
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val |= 0x3 << 12; /* Port 3 VLAN Index */
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val |= 1 << 11; /* internal use */
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val |= 1 << 10; /* internal use */
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val |= 1 << 9; /* internal use */
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val |= 1 << 7; /* internal use */
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val |= 1 << 6; /* internal use */
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val |= 0x18 << 0; /* VLAN D membership */
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MIIBUS_WRITEREG(sc->mii_dev, 3, 24, val);
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/* Port 3 Control Register 2 and VLAN D */
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val = 0;
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val |= 1 << 15; /* internal use */
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val |= 1 << 14; /* internal use */
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val |= 1 << 13; /* internal use */
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val |= 1 << 12; /* internal use */
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val |= 0x103 << 0; /* VLAN D ID */
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MIIBUS_WRITEREG(sc->mii_dev, 3, 25, val);
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/* Port 4 Control Register 1 and VLAN E */
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val = 0;
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val |= 0x0 << 12; /* Port 4 VLAN Index */
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val |= 1 << 11; /* internal use */
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val |= 1 << 10; /* internal use */
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val |= 1 << 9; /* internal use */
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val |= 1 << 7; /* internal use */
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val |= 1 << 6; /* internal use */
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val |= 0 << 0; /* VLAN E membership */
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MIIBUS_WRITEREG(sc->mii_dev, 4, 24, val);
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/* Port 4 Control Register 2 and VLAN E */
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val = 0;
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val |= 1 << 15; /* internal use */
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val |= 1 << 14; /* internal use */
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val |= 1 << 13; /* internal use */
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val |= 1 << 12; /* internal use */
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val |= 0x104 << 0; /* VLAN E ID */
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MIIBUS_WRITEREG(sc->mii_dev, 4, 25, val);
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#endif
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#ifdef RL_DEBUG
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rlswitch_phydump(dev);
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#endif
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MIIBUS_MEDIAINIT(sc->mii_dev);
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return (0);
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}
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static int
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rlswitch_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
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{
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switch (cmd) {
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case MII_POLLSTAT:
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break;
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case MII_MEDIACHG:
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break;
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case MII_TICK:
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break;
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}
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/* Update the media status. */
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PHY_STATUS(sc);
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/* Callback if something changed. */
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// mii_phy_update(sc, cmd);
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return (0);
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}
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static void
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rlswitch_status(struct mii_softc *phy)
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{
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struct mii_data *mii = phy->mii_pdata;
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mii->mii_media_status = IFM_AVALID;
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mii->mii_media_active = IFM_ETHER;
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mii->mii_media_status |= IFM_ACTIVE;
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mii->mii_media_active |=
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IFM_100_TX | IFM_FDX | mii_phy_flowstatus(phy);
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}
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#ifdef RL_DEBUG
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static void
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rlswitch_phydump(device_t dev) {
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int phy, reg, val;
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struct mii_softc *sc;
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sc = device_get_softc(dev);
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device_printf(dev, "rlswitchphydump\n");
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for (phy = 0; phy <= 5; phy++) {
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printf("PHY%i:", phy);
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for (reg = 0; reg <= 31; reg++) {
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val = MIIBUS_READREG(sc->mii_dev, phy, reg);
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printf(" 0x%x", val);
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}
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printf("\n");
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}
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}
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#endif
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