1109 lines
43 KiB
Plaintext
1109 lines
43 KiB
Plaintext
<!-- $Id: uart.sgml,v 1.2 1996/02/27 15:57:51 jfieber Exp $ -->
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<!-- The FreeBSD Documentation Project -->
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<!--
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<!DOCTYPE linuxdoc PUBLIC "-//FreeBSD//DTD linuxdoc//EN" [
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<!ENTITY % authors SYSTEM "authors.sgml">
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%authors;
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]>
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-->
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<sect2><heading>The UART: What it is and how it works<label id="uart"></heading>
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<p><em>Copyright © 1996 &a.uhclem;, All Rights Reserved.<newline>
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13 January 1996.</em>
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<!-- Version 1(2) 13-Jan-96 -->
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The Universal Asynchronous Receiver/Transmitter (UART) controller
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is the key component of the serial communications subsystem of a
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computer. The UART takes bytes of data and transmits the individual
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bits in a sequential fashion. At the destination, a second UART
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re-assembles the bits into complete bytes.
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Serial transmission is commonly used with modems and for
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non-networked communication between computers, terminals
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and other devices.
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There are two primary forms of serial transmission: Synchronous and
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Asynchronous. Depending on the modes that are supported by the
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hardware, the name of the communication sub-system will usually
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include a "A" if it supports Asynchronous communications, and a
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"S" if it supports Synchronous communications. Both forms are
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described below.
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Some common acronyms are:
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<quote>UART Universal Asynchronous Receiver/Transmitter</quote>
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<quote>USART Universal Synchronous-Asynchronous Receiver/Transmitter</quote>
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<sect3><heading>Synchronous Serial Transmission</heading>
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<p>Synchronous serial transmission requires that the sender and
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receiver share a clock with one another, or that the sender provide
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a strobe or other timing signal so that the receiver knows when to
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"read" the next bit of the data. In most forms of serial
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Synchronous communication, if there is no data available at a given
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instant to transmit, a fill character must be sent instead so that
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data is always being transmitted. Synchronous communication is
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usually more efficient because only data bits are transmitted
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between sender and receiver, and synchronous communication can be
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more more costly if extra wiring and circuits are required to
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share a clock signal between the sender and receiver.
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A form of Synchronous transmission is used with printers and
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fixed disk devices in that the data is sent on one set of wires
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while a clock or strobe is sent on a different wire. Printers and
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fixed disk devices are not normally serial devices because most
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fixed disk interface standards send an entire word of data for each
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clock or strobe signal by using a separate wire for each bit of the
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word. In the PC industry, these are known as Parallel devices.
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The standard serial communications hardware in the PC does not
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support Synchronous operations. This mode is described here for
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comparison purposes only.
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<sect3><heading>Asynchronous Serial Transmission</heading>
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<p>Asynchronous transmission allows data to be transmitted without
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the sender having to send a clock signal to the receiver. Instead,
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the sender and receiver must agree on timing parameters in advance
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and special bits are added to each word which are used to
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synchronize the sending and receiving units.
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When a word is given to the UART for Asynchronous transmissions,
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a bit called the "Start Bit" is added to the beginning of each word
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that is to be transmitted. The Start Bit is used to alert the
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receiver that a word of data is about to be sent, and to force the
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clock in the receiver into synchronization with the clock in the
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transmitter. These two clocks must be accurate enough to not
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have the frequency drift by more than 10% during the transmission
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of the remaining bits in the word. (This requirement was set in
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the days of mechanical teleprinters and is easily met by modern
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electronic equipment.)
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After the Start Bit, the individual bits of the word of data are
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sent, with the Least Significant Bit (LSB) being sent first. Each
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bit in the transmission is transmitted for exactly the same
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amount of time as all of the other bits, and the receiver "looks"
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at the wire at approximately halfway through the period assigned
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to each bit to determine if the bit is a "1" or a "0". For example,
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if it takes two seconds to send each bit, the receiver will examine
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the signal to determine if it is a "1" or a "0" after one second
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has passed, then it will wait two seconds and then examine the value
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of the next bit, and so on.
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The sender does not know when the receiver has "looked" at the
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value of the bit. The sender only knows when the clock says to
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begin transmitting the next bit of the word.
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When the entire data word has been sent, the transmitter may add
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a Parity Bit that the transmitter generates. The Parity Bit may
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be used by the receiver to perform simple error checking. Then at
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least one Stop Bit is sent by the transmitter.
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When the receiver has received all of the bits in the data word,
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it may check for the Parity Bits (both sender and receiver must
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agree on whether a Parity Bit is to be used), and then the receiver
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looks for a Stop Bit. If the Stop Bit does not appear when it is
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supposed to, the UART considers the entire word to be garbled and
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will report a Framing Error to the host processor when the data
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word is read. The usual cause of a Framing Error is that the sender
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and receiver clocks were not running at the same speed, or that
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the signal was interrupted.
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Regardless of whether the data was received correctly or not, the
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UART automatically discards the Start, Parity and Stop bits. If the
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sender and receiver are configured identically, these bits are not
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passed to the host.
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If another word is ready for transmission, the Start Bit for the new
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word can be sent as soon as the Stop Bit for the previous
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word has been sent.
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Because asynchronous data is "self synchronizing", if there is no
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data to transmit, the transmission line can be idle.
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<sect3><heading>Other UART Functions</heading>
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<p>In addition to the basic job of converting data from parallel to
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serial for transmission and from serial to parallel on reception,
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a UART will usually provide additional circuits for signals that
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can be used to indicate the state of the transmission media, and
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to regulate the flow of data in the event that the remote device
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is not prepared to accept more data. For example, when the
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device connected to the UART is a modem, the modem may report the
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presence of a carrier on the phone line while the computer may be
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able to instruct the modem to reset itself or to not take calls
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by asserting or deasserting one more more of these extra signals.
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The function of each of these additional signals is defined in
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the EIA RS232-C standard.
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<sect3><heading>The RS232-C and V.24 Standards</heading>
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<p>In most computer systems, the UART is connected to circuitry that
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generates signals that comply with the EIA RS232-C specification.
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There is also a CCITT standard named V.24 that mirrors the
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specifications included in RS232-C.
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<sect4><heading>RS232-C Bit Assignments (Marks and Spaces)</heading>
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<p>In RS232-C, a value of "1" is called a "Mark" and a value of "0"
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is called a "Space". When a communication line is idle, the line
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is said to be "Marking", or transmitting continuous "1" values.
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The Start bit always has a value of "0" (a Space). The Stop Bit
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always has a value of "1" (a Mark). This means that there will
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always be a Mark (1) to Space (0) transition on the line at the
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start of every word, even when multiple word are
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transmitted back to back. This guarantees that sender and
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receiver can resynchronize their clocks regardless of the content
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of the data bits that are being transmitted.
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The idle time between Stop and Start bits does not have
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to be an exact multiple (including zero) of the bit rate of the
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communication link, but most UARTs are designed this way for
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simplicity.
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In RS232-C, the "Marking" signal (a "1") is represented by a voltage
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between -2 VDC and -12 VDC, and a "Spacing" signal (a "0") is
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represented by a voltage between 0 and +12 VDC. The transmitter
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is supposed to send +12 VDC or -12 VDC, and the receiver is supposed
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to allow for some voltage loss in long cables. Some transmitters
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in low power devices (like portable computers) sometimes use only
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+5 VDC and -5 VDC, but these values are still acceptable to a
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RS232-C receiver, provided that the cable lengths are short.
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<sect4><heading>RS232-C Break Signal</heading>
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<p>RS232-C also specifies a signal called a "Break", which is caused
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by sending continuous Spacing values (no Start or Stop bits). When
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there is no electricity present on the data circuit, the line is
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considered to be sending "Break".
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The "Break" signal must be of a duration longer than the time
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it takes to send a complete byte plus Start, Stop and Parity bits.
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Most UARTs can distinguish between a Framing Error and a
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Break, but if the UART cannot do this, the Framing Error detection
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can be used to identify Breaks.
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In the days of teleprinters, when numerous printers around the
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country were wired in series (such as news services), any unit
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could cause a "Break" by temporarily opening the entire circuit
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so that no current flowed. This was used to allow a location with
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urgent news to interrupt some other location that was currently
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sending information.
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In modern systems there are two types of Break signals. If the
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Break is longer than 1.6 seconds, it is considered a "Modem Break",
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and some modems can be programmed to terminate the conversation and
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go on-hook or enter the modems' command mode when the modem detects
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this signal. If the Break is smaller than 1.6 seconds, it signifies
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a Data Break and it is up to the remote computer to respond to
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this signal. Sometimes this form of Break is used as an Attention
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or Interrupt signal and sometimes is accepted as a substitute for
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the ASCII CONTROL-C character.
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Marks and Spaces are also equivalent to "Holes" and "No Holes"
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in paper tape systems.
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Note that Breaks cannot be generated from paper tape or from any
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other byte value, since bytes are always sent with Start and Stop
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bit. The UART is usually capable of generating the continuous
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Spacing signal in response to a special command from the host
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processor.
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<sect4><heading>RS232-C DTE and DCE Devices</heading>
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<p>The RS232-C specification defines two types of equipment: the Data
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Terminal Equipment (DTE) and the Data Carrier Equipment (DCE).
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Usually, the DTE device is the terminal (or computer), and the DCE
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is a modem. Across the phone line at the other end of a
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conversation, the receiving modem is also a DCE device and the
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computer that is connected to that modem is a DTE device. The DCE
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device receives signals on the pins that the DTE device transmits on,
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and vice versa.
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When two devices that are both DTE or both DCE must be connected
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together without a modem or a similar media translater between them,
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a NULL modem must be used. The NULL modem electrically re-arranges
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the cabling so that the transmitter output is connected to the
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receiver input on the other device, and vice versa. Similar
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translations are performed on all of the control signals so that
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each device will see what it thinks are DCE (or DTE) signals from
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the other device.
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The number of signals generated by the DTE and DCE devices are
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not symmetrical. The DTE device generates fewer signals for
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the DCE device than the DTE device receives from the DCE.
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<sect4><heading>RS232-C Pin Assignments</heading>
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<p>The EIA RS232-C specification (and the ITU equivalent, V.24) calls
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for a twenty-five pin connector (usually a DB25) and defines the
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purpose of most of the pins in that connector.
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In the IBM Personal Computer and similar systems, a subset of
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RS232-C signals are provided via nine pin connectors (DB9).
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The signals that are not included on the PC connector deal mainly
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with synchronous operation, and this transmission mode is not
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supported by the UART that IBM selected for use in the IBM PC.
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Depending on the computer manufacturer, a DB25, a DB9, or
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both types of connector may be used for RS232-C communications.
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(The IBM PC also uses a DB25 connector for the parallel printer
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interface which causes some confusion.)
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Below is a table of the RS232-C signal assignments in the DB25
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and DB9 connectors.
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<verb>
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DB25 DB9 EIA CCITT Common Signal Description
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RS232-C IBM PC Circuit Circuit Name Source
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Pin Pin Symbol Symbol
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1 - AA 101 PG/FG --- Frame/Protective Ground
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2 3 BA 103 TD DTE Transmit Data
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3 2 BB 104 RD DCE Receive Data
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4 7 CA 105 RTS DTE Request to Send
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5 8 CB 106 CTS DCE Clear to Send
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6 6 CC 107 DSR DCE Data Set Ready
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7 5 AV 102 SG/GND --- Signal Ground
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8 1 CF 109 DCD/CD DCE Data Carrier Detect
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9 - - - - - Reserved for Test
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10 - - - - - Reserved for Test
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11 - - - - - Unassigned
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12 - CI 122 SRLSD DCE Sec. Recv. Line Signal Detector
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13 - SCB 121 SCTS DCE Secondary Clear To Send
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14 - SBA 118 STD DTE Secondary Transmit Data
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15 - DB 114 TSET DCE Trans. Sig. Element Timing
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16 - SBB 119 SRD DCE Secondary Received Data
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17 - DD 115 RSET DCE Receiver Signal Element Timing
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18 - - 141 LOOP DTE Local Loopback
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19 - SCA 120 SRS DTE Secondary Request to Send
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20 4 CD 108.2 DTR DTE Data Terminal Ready
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21 - - - RDL DTE Remote Digital Loopback
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22 9 CE 125 RI DCE Ring Indicator
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23 - CH 111 DSRS DTE Data Signal Rate Selector
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24 - DA 113 TSET DTE Trans. Sig. Element Timing
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25 - - 142 - DCE Test Mode
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</verb>
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<sect3><heading>Bits, Baud and Symbols</heading>
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<p>Baud is a measurement of transmission speed in asynchronous
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communication. Because of advances in modem communication
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technology, this term is frequently misused when describing
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the data rates in newer devices.
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Traditionally, a Baud Rate represents the number of bits that are
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actually being sent over the media, not the amount of data
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that is actually moved from one DTE device to the other. The
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Baud count includes the overhead bits Start, Stop and Parity
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that are generated by the sending UART and removed by the
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receiving UART. This means that seven-bit words of data
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actually take 10 bits to be completely transmitted.
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Therefore, a modem capable of moving 300 bits per second from one
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place to another can normally only move 30 7-bit words if
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Parity is used and one Start and Stop bit are present.
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If 8-bit data words are used and Parity bits are also used, the
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data rate falls to 27.27 words per second, because it now
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takes 11 bits to send the eight-bit words, and the modem still
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only sends 300 bits per second.
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The formula for converting bytes per second into a baud rate
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and vice versa was simple until error-correcting modems
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came along. These modems receive the serial stream of bits
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from the UART in the host computer (even when internal modems
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are used the data is still frequently serialized) and converts
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the bits back into bytes. These bytes are then combined into
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packets and sent over the phone line using a Synchronous
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transmission method. This means that the Stop, Start, and Parity
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bits added by the UART in the DTE (the computer) were removed by
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the modem before transmission by the sending modem. When these
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bytes are received by the remote modem, the remote modem adds
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Start, Stop and Parity bits to the words, converts them to a
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serial format and then sends them to the receiving UART in the remote
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computer, who then strips the Start, Stop and Parity bits.
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The reason all these extra conversions are done is so that the
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two modems can perform error correction, which means that the
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receiving modem is able to ask the sending modem to resend a
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block of data that was not received with the correct checksum.
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This checking is handled by the modems, and the DTE devices are
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usually unaware that the process is occurring.
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By striping the Start, Stop and Parity bits, the additional bits of
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data that the two modems must share between themselves to perform
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error-correction are mostly concealed from the effective
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transmission rate seen by the sending and receiving DTE equipment.
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For example, if a modem sends ten 7-bit words to another modem
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without including the Start, Stop and Parity bits, the sending
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modem will be able to add 30 bits of its own information that
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the receiving modem can use to do error-correction without
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impacting the transmission speed of the real data.
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The use of the term Baud is further confused by modems that perform
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compression. A single 8-bit word passed over the telephone
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line might represent a dozen words that were transmitted to
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the sending modem. The receiving modem will expand the data back
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to its original content and pass that data to the receiving DTE.
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Modern modems also include buffers that allow the rate that
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bits move across the phone line (DCE to DCE) to be a different speed
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than the speed that the bits move between the DTE and DCE on both
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ends of the conversation. Normally the speed between the DTE and
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DCE is higher than the DCE to DCE speed because of the use of
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compression by the modems.
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Because the number of bits needed to describe a byte varied
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during the trip between the two machines plus the differing
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bits-per-seconds speeds that are used present on the DTE-DCE and
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DCE-DCE links, the usage of the term Baud to describe the
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overall communication speed causes problems and can misrepresent
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the true transmission speed. So Bits Per Second (bps) is the correct
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term to use to describe the transmission rate seen at the
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DCE to DCE interface and Baud or Bits Per Second are acceptable
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terms to use when a connection is made between two systems with a
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wired connection, or if a modem is in use that is not performing
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error-correction or compression.
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Modern high speed modems (2400, 9600, 14,400, and 19,200bps) in
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reality still operate at or below 2400 baud, or more accurately,
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2400 Symbols per second. High speed modem are able to encode more
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bits of data into each Symbol using a technique called Constellation
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Stuffing, which is why the effective bits per second rate of the
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modem is higher, but the modem continues to operate within the
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limited audio bandwidth that the telephone system provides.
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Modems operating at 28,800 and higher speeds have variable Symbol
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rates, but the technique is the same.
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<sect3><heading>The IBM Personal Computer UART</heading>
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<p>Starting with the original IBM Personal Computer, IBM selected
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the National Semiconductor INS8250 UART for use in the IBM PC
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Parallel/Serial Adapter. Subsequent generations of compatible
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computers from IBM and other vendors continued to use the INS8250
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or improved versions of the National Semiconductor UART family.
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<sect4><heading>National Semiconductor UART Family Tree</heading>
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<p>There have been several versions and subsequent generations of
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the INS8250 UART. Each major version is described below.
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<verb>
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INS8250 -> INS8250B
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\
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\
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\-> INS8250A -> INS82C50A
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\
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\
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\-> NS16450 -> NS16C450
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\
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\
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\-> NS16550 -> NS16550A -> PC16550D
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</verb>
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<descrip>
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<tag>INS8250</tag>This part was used in the original IBM PC and
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IBM PC/XT. The original name for this part was the INS8250 ACE
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(Asynchronous Communications Element) and it is made from NMOS
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technology.
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The 8250 uses eight I/O ports and has a one-byte send and
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a one-byte receive buffer. This original UART has several
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race conditions and other flaws. The original IBM BIOS
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includes code to work around these flaws, but this made
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the BIOS dependent on the flaws being present, so subsequent
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parts like the 8250A, 16450 or 16550 could not be used in
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the original IBM PC or IBM PC/XT.
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<tag>INS8250-B</tag>This is the slower speed of the INS8250 made
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from NMOS technology. It contains the same problems as the original
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INS8250.
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<tag>INS8250A</tag>An improved version of the INS8250 using XMOS
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technology with various functional flaws corrected. The INS8250A
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was used initially in PC clone computers by vendors who used
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"clean" BIOS designs. Because of the corrections in the chip, this
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part could not be used with a BIOS compatible with the INS8250
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or INS8250B.
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<tag>INS82C50A</tag>This is a CMOS version (low power consumption)
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of the INS8250A and has similar functional characteristics.
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<tag>NS16450</tag>Same as NS8250A with improvements so it can be
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used with faster CPU bus designs. IBM used this part in the IBM AT
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and updated the IBM BIOS to no longer rely on the bugs in the
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INS8250.
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<tag>NS16C450</tag>This is a CMOS version (low power consumption)
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of the NS16450.
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<tag>NS16550</tag>Same as NS16450 with a 16-byte send and receive
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buffer but the buffer design was flawed and could not be reliably
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be used.
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|
|
<tag>NS16550A</tag>Same as NS16550 with the buffer flaws corrected.
|
|
The 16550A and its successors have become the most popular UART
|
|
design in the PC industry, mainly due it its ability to reliably
|
|
handle higher data rates on operating systems with sluggish interrupt
|
|
response times.
|
|
|
|
<tag>NS16C552</tag>This component consists of two NS16C550A CMOS
|
|
UARTs in a single package.
|
|
|
|
<tag>PC16550D</tag>Same as NS16550A with subtle flaws corrected. This
|
|
is revision D of the 16550 family and is the latest design available
|
|
from National Semiconductor.
|
|
</descrip>
|
|
|
|
<sect4><heading>The NS16550AF and the PC16550D are the same thing</heading>
|
|
|
|
<p>National reorganized their part numbering system a few years ago,
|
|
and the NS16550AFN no longer exists by that name. (If you
|
|
have a NS16550AFN, look at the date code on the part, which is a
|
|
four digit number that usually starts with a nine. The first two
|
|
digits of the number are the year, and the last two digits are the
|
|
week in that year when the part was packaged. If you have a
|
|
NS16550AFN, it is probably a few years old.)
|
|
|
|
The new numbers are like PC16550DV, with minor differences in the
|
|
suffix letters depending on the package material and its shape.
|
|
(A description of the numbering system can be found below.)
|
|
|
|
It is important to understand that in some stores, you may pay
|
|
$15(US) for a NS16550AFN made in 1990 and in the next bin are the
|
|
new PC16550DN parts with minor fixes that National has made since the
|
|
AFN part was in production, the PC16550DN was probably made in the
|
|
past six months and it costs half (as low as $5(US) in volume) as
|
|
much as the NS16550AFN because they are readily available.
|
|
|
|
As the supply of NS16550AFN chips continues to shrink, the price will
|
|
probably continue to increase until more people discover and accept
|
|
that the PC16550DN really has the same function as the old part
|
|
number.
|
|
|
|
<sect4><heading>National Semiconductor Part Numbering System</heading>
|
|
|
|
<p>The older NS<em>nnnnnrqp</em> part numbers are now of the
|
|
format PC<em>nnnnnrgp</em>.
|
|
|
|
The "<em>r</em>" is the revision field. The current revision of
|
|
the 16550 from National Semiconductor is "D".
|
|
|
|
The "<em>p</em>" is the package-type field. The types are:
|
|
<verb> "F" QFP (quad flat pack) L lead type
|
|
"N" DIP (dual inline package) through hole straight lead type
|
|
"V" LPCC (lead plastic chip carrier) J lead type</verb>
|
|
|
|
The "<em>g</em>" is the product grade field. If an "I" precedes
|
|
the package-type letter, it indicates an "industrial" grade part,
|
|
which has higher specs than a standard part but not as high as
|
|
Military Specification (Milspec) component. This is an optional field.
|
|
|
|
So what we used to call a NS16550AFN (DIP Package) is now called a
|
|
PC16550DN or PC16550DIN.
|
|
|
|
|
|
<sect3><heading>Other Vendors and Similar UARTs</heading>
|
|
|
|
<p>Over the years, the 8250, 8250A, 16450 and 16550 have been licensed
|
|
or copied by other chip vendors. In the case of the 8250, 8250A
|
|
and 16450, the exact circuit (the "megacell") was licensed to many
|
|
vendors, including Western Digital and Intel. Other vendors
|
|
reverse-engineered the part or produced emulations that had similar
|
|
behavior.
|
|
|
|
In internal modems, the modem designer will frequently emulate the
|
|
8250A/16450 with the modem microprocessor, and the emulated UART will
|
|
frequently have a hidden buffer consisting of several hundred bytes.
|
|
Because of the size of the buffer, these emulations can be as
|
|
reliable as a 16550A in their ability to handle high speed data.
|
|
However, most operating systems will still report that
|
|
the UART is only a 8250A or 16450, and may not make effective use
|
|
of the extra buffering present in the emulated UART unless special
|
|
drivers are used.
|
|
|
|
Some modem makers are driven by market forces to abandon a design
|
|
that has hundreds of bytes of buffer and instead use a 16550A UART
|
|
so that the product will compare favorably in market comparisons
|
|
even though the effective performance may be lowered by this action.
|
|
|
|
A common misconception is that all parts with "16550A" written on
|
|
them are identical in performance. There are differences, and in
|
|
some cases, outright flaws in most of these 16550A clones.
|
|
|
|
When the NS16550 was developed, the National Semiconductor obtained
|
|
several patents on the design and they also limited licensing, making
|
|
it harder for other vendors to provide a chip with similar features.
|
|
Because of the patents, reverse-engineered designs and emulations
|
|
had to avoid infringing the claims covered by the patents.
|
|
Subsequently, these copies almost never perform exactly the same as
|
|
the NS16550A or PC16550D, which are the parts most computer and
|
|
modem makers want to buy but are sometimes unwilling to pay the
|
|
price required to get the genuine part.
|
|
|
|
Some of the differences in the clone 16550A parts are unimportant,
|
|
while others can prevent the device from being used at all with a
|
|
given operating system or driver. These differences may show up
|
|
when using other drivers, or when particular combinations of events
|
|
occur that were not well tested or considered in the Windows driver.
|
|
This is because most modem vendors and 16550-clone makers use the
|
|
Microsoft drivers from Windows for Workgroups 3.11 and the Microsoft
|
|
MSD utility as the primary tests for compatibility with the
|
|
NS16550A. This over-simplistic criteria means that if a different
|
|
operating system is used, problems could appear due to subtle
|
|
differences between the clones and genuine components.
|
|
|
|
National Semiconductor has made available a program named COMTEST
|
|
that performs compatibility tests independent of any OS drivers.
|
|
It should be remembered that the purpose of this type of program is
|
|
to demonstrate the flaws in the products of the competition, so the
|
|
program will report major as well as extremely subtle differences in
|
|
behavior in the part being tested.
|
|
|
|
In a series of tests performed by the author of this document in
|
|
1994, components made by National Semiconductor, TI, StarTech, and
|
|
CMD as well as megacells and emulations embedded in internal modems
|
|
were tested with COMTEST. A difference count for some of these
|
|
components is listed below. Because these tests were performed in
|
|
1994, they may not reflect the current performance of the given
|
|
product from a vendor.
|
|
|
|
It should be noted that COMTEST normally aborts when an excessive
|
|
number or certain types of problems have been detected. As part of
|
|
this testing, COMTEST was modified so that it would not abort no
|
|
matter how many differences were encountered.
|
|
|
|
|
|
<verb>Vendor Part number Errors aka "differences" reported
|
|
National (PC16550DV) 0 *
|
|
|
|
National (NS16550AFN) 0
|
|
|
|
National (NS16C552V) 0 *
|
|
|
|
TI (TL16550AFN) 3
|
|
|
|
CMD (16C550PE) 19
|
|
|
|
StarTech (ST16C550J) 23
|
|
|
|
Rockwell reference modem
|
|
with internal 16550 or an
|
|
emulation (RC144DPi/C3000-25) 117
|
|
|
|
Sierra modem with an internal
|
|
16550 (SC11951/SC11351) 91</verb>
|
|
|
|
<p>It is important to understand that a simple count of differences
|
|
from COMTEST does not reveal a lot about what differences are
|
|
important and which are not. For example, about half of the
|
|
differences reported in the two modems listed above that have
|
|
internal UARTs were caused by the clone UARTs not supporting
|
|
five- and six-bit character modes. The real 16550, 16450, and
|
|
8250 UARTs all support these modes and COMTEST checks the
|
|
functionality of these modes so over fifty differences are
|
|
reported. However, almost no modern modem supports five- or
|
|
six-bit characters, particularly those with error-correction
|
|
and compression capabilities. This means that the differences
|
|
related to five- and six-bit character modes can be discounted.
|
|
|
|
Many of the differences COMTEST reports have to do with timing. In
|
|
many of the clone designs, when the host reads from one port, the
|
|
status bits in some other port may not update in the same amount
|
|
of time (some faster, some slower) as a <em>real</em> NS16550AFN
|
|
and COMTEST looks for these differences. This means that the number
|
|
of differences can be misleading in that one device may only have
|
|
one or two differences but they are extremely serious, and some
|
|
other device that updates the status registers faster or slower
|
|
than the reference part (that would probably never affect the
|
|
operation of a properly written driver) could have dozens of
|
|
differences reported.
|
|
|
|
* To date, the author of this document has not found any non-National
|
|
parts that report zero differences using the COMTEST program. It
|
|
should also be noted that National has had five versions of the
|
|
16550 over the years and the newest parts behave a bit differently
|
|
than the classic NS16550AFN that is considered the benchmark for
|
|
functionality. COMTEST appears to turn a blind eye to the
|
|
differences within the National product line and reports no errors
|
|
on the National parts (except for the original 16550) even when
|
|
there are official erratas that describe bugs in the A, B and C
|
|
revisions of the parts, so this bias in COMTEST must be taken into
|
|
account.
|
|
|
|
COMTEST can be used as a screening tool to alert the administrator
|
|
to the presence of potentially incompatible components
|
|
that might cause problems or have to be handled as a special case.
|
|
|
|
If you run COMTEST on a 16550 that is in a modem or a modem is
|
|
attached to the serial port, you need to first issue a ATE0&W
|
|
command to the modem so that the modem will not echo any of the test
|
|
characters. If you forget to do this, COMTEST will report at least
|
|
this one difference:
|
|
<quote>Error (6)...Timeout interrupt failed: IIR = c1 LSR = 61</quote>
|
|
|
|
|
|
<sect3><heading>8250/16450/16550 Registers</heading>
|
|
|
|
<p>The 8250/16450/16550 UART occupies eight contiguous I/O port
|
|
addresses. In the IBM PC, there are two defined locations for
|
|
these eight ports and they are known collectively as COM1 and COM2.
|
|
The makers of PC-clones and add-on cards have created two additional
|
|
areas known as COM3 and COM4, but these extra COM ports conflict
|
|
with other hardware on some systems. The most common conflict is
|
|
with video adapters that provide IBM 8514 emulation.
|
|
|
|
<verb>
|
|
COM1 is located from 0x3f8 to 0x3ff and normally uses IRQ 4
|
|
COM2 is located from 0x2f8 to 0x2ff and normally uses IRQ 3
|
|
COM3 is located from 0x3e8 to 0x3ef and has no standardized IRQ
|
|
COM4 is located from 0x2e8 to 0x2ef and has no standardized IRQ
|
|
</verb>
|
|
<p>A description of the I/O ports of the 8250/16450/16550 UART is
|
|
provided below.
|
|
|
|
<verb>
|
|
I/O Access Description
|
|
Port Allowed
|
|
|
|
+0x00 write Transmit Holding Register (THR)
|
|
(DLAB==0) Information written to this port are treated
|
|
as data words and will be transmitted by the
|
|
UART.
|
|
|
|
+0x00 read Receive Buffer Register (RBR)
|
|
(DLAB==0) Any data words received by the UART from the
|
|
serial link are accessed by the host by
|
|
reading this port.
|
|
|
|
|
|
+0x00 write/read Divisor Latch LSB (DLL)
|
|
(DLAB==1) This value will be divided from the master
|
|
input clock (in the IBM PC, the master
|
|
clock is 1.8432MHz) and the resulting clock
|
|
will determine the baud rate of the UART.
|
|
This register holds bits 0 thru 7 of the
|
|
divisor.
|
|
|
|
|
|
+0x01 write/read Divisor Latch MSB (DLH)
|
|
(DLAB==1) This value will be divided from the master
|
|
input clock (in the IBM PC, the master
|
|
clock is 1.8432MHz) and the resulting clock
|
|
will determine the baud rate of the UART.
|
|
This register holds bits 8 thru 15 of the
|
|
divisor.
|
|
|
|
|
|
+0x01 write/read Interrupt Enable Register (IER)
|
|
(DLAB==0) The 8250/16450/16550 UART classifies events into
|
|
one of four categories. Each category can be
|
|
configured to generate an interrupt when any of
|
|
the events occurs. The 8250/16450/16550 UART
|
|
generates a single external interrupt signal
|
|
regardless of how many events in the enabled
|
|
categories have occurred. It is up to the host
|
|
processor to respond to the interrupt and then
|
|
poll the enabled interrupt categories (usually
|
|
all categories have interrupts enabled) to
|
|
determine the true cause(s) of the interrupt.
|
|
|
|
Bit 7 Reserved, always 0.
|
|
|
|
Bit 6 Reserved, always 0.
|
|
|
|
Bit 5 Reserved, always 0.
|
|
|
|
Bit 4 Reserved, always 0.
|
|
|
|
Bit 3 Enable Modem Status Interrupt (EDSSI)
|
|
Setting this bit to "1" allows the UART
|
|
to generate an interrupt when a
|
|
change occurs on one or more of the
|
|
status lines.
|
|
|
|
Bit 2 Enable Receiver Line Status
|
|
Interrupt (ELSI)
|
|
Setting this bit to "1" causes the UART
|
|
to generate an interrupt when the
|
|
an error (or a BREAK signal) has been
|
|
detected in the incoming data.
|
|
|
|
Bit 1 Enable Transmitter Holding Register
|
|
Empty Interrupt (ETBEI)
|
|
Setting this bit to "1" causes the UART
|
|
to generate an interrupt when the
|
|
UART has room for one or more
|
|
additional characters that are to
|
|
be transmitted.
|
|
|
|
Bit 0 Enable Received Data Available
|
|
Interrupt (ERBFI)
|
|
Setting this bit to "1" causes the UART
|
|
to generate an interrupt when the UART
|
|
has received enough characters to exceed
|
|
the trigger level of the FIFO, or the
|
|
FIFO timer has expired (stale data), or
|
|
a single character has been received
|
|
when the FIFO is disabled.
|
|
|
|
|
|
+0x02 write FIFO Control Register (FCR)
|
|
(This port does not exist on the 8250 and 16450
|
|
UART.)
|
|
|
|
Bit 7 Receiver Trigger Bit #1
|
|
Bit 6 Receiver Trigger Bit #0
|
|
These two bits control at what point the
|
|
receiver is to generate an interrupt when
|
|
the FIFO is active.
|
|
|
|
7 6 How many words are received
|
|
before an interrupt is generated.
|
|
0 0 1
|
|
|
|
0 1 4
|
|
|
|
1 0 8
|
|
|
|
1 1 14
|
|
|
|
Bit 5 Reserved, always 0.
|
|
|
|
Bit 4 Reserved, always 0.
|
|
|
|
Bit 3 DMA Mode Select
|
|
If Bit 0 is set to "1" (FIFOs enabled),
|
|
setting this bit changes the operation
|
|
of the -RXRDY and -TXRDY signals from
|
|
Mode 0 to Mode 1.
|
|
|
|
Bit 2 Transmit FIFO Reset
|
|
When a "1" is written to this bit,
|
|
the contents of the FIFO are discarded.
|
|
Any word currently being transmitted
|
|
will be sent intact. This function is
|
|
useful in aborting transfers.
|
|
|
|
Bit 1 Receiver FIFO Reset
|
|
When a "1" is written to this bit,
|
|
the contents of the FIFO are discarded.
|
|
Any word currently being assembled
|
|
in the shift register will be received
|
|
intact.
|
|
|
|
Bit 0 16550 FIFO Enable
|
|
When set, both the transmit and receive
|
|
FIFOs are enabled. Any contents in the
|
|
holding register, shift registers or
|
|
FIFOs are lost when FIFOs are enabled or
|
|
disabled.
|
|
|
|
|
|
+0x02 read Interrupt Identification Register (IIR)
|
|
|
|
Bit 7 FIFOs enabled.
|
|
On the 8250/16450 UART, this bit is zero.
|
|
|
|
Bit 6 FIFOs enabled.
|
|
On the 8250/16450 UART, this bit is zero.
|
|
|
|
Bit 5 Reserved, always 0.
|
|
|
|
Bit 4 Reserved, always 0.
|
|
|
|
Bit 3 Interrupt ID Bit #2
|
|
On the 8250/16450 UART, this bit is zero.
|
|
Bit 2 Interrupt ID Bit #1
|
|
Bit 1 Interrupt ID Bit #0
|
|
These three bits combine to report
|
|
the category of event that caused the
|
|
interrupt that is in progress. These
|
|
categories have priorities, so if
|
|
multiple categories of events occur at
|
|
the same time, the UART will report the
|
|
more important events first and the host
|
|
must resolve the events in the order they
|
|
are reported. All events that caused the
|
|
current interrupt must be resolved before
|
|
any new interrupts will be generated.
|
|
(This is a limitation of the PC
|
|
architecture.)
|
|
|
|
2 1 0 Priority Description
|
|
|
|
0 1 1 First Receiver Error
|
|
(OE, PE, BI or FE)
|
|
|
|
0 1 0 Second Received Data
|
|
Available
|
|
|
|
1 1 0 Second Trigger level
|
|
identification
|
|
(Stale data in
|
|
receive buffer)
|
|
|
|
0 0 1 Third Transmitter has
|
|
room for more
|
|
words (THRE)
|
|
|
|
0 0 0 Fourth Modem Status
|
|
Change (-CTS,
|
|
-DSR, -RI, or
|
|
-DCD)
|
|
|
|
Bit 0 Interrupt Pending Bit
|
|
If this bit is set to "0", then at least
|
|
one interrupt is pending.
|
|
|
|
|
|
+0x03 write/read Line Control Register (LCR)
|
|
|
|
Bit 7 Divisor Latch Access Bit (DLAB)
|
|
When set, access to the data
|
|
transmit/receive register (THR/RBR) and
|
|
the Interrupt Enable Register (IER) is
|
|
disabled. Any access to these ports is
|
|
now redirected to the Divisor Latch
|
|
Registers. Setting this bit, loading
|
|
the Divisor Registers, and clearing
|
|
DLAB should be done with interrupts
|
|
disabled.
|
|
|
|
Bit 6 Set Break
|
|
When set to "1", the transmitter begins
|
|
to transmit continuous Spacing until
|
|
this bit is set to "0". This overrides
|
|
any bits of characters that are being
|
|
transmitted.
|
|
|
|
Bit 5 Stick Parity
|
|
When parity is enabled, setting this
|
|
bit causes parity to always be "1" or
|
|
"0", based on the value of Bit 4.
|
|
|
|
Bit 4 Even Parity Select (EPS)
|
|
When parity is enabled and Bit 5 is "0",
|
|
setting this bit causes even parity
|
|
to be transmitted and expected.
|
|
Otherwise, odd parity is used.
|
|
|
|
Bit 3 Parity Enable (PEN)
|
|
When set to "1", a parity bit is
|
|
inserted between the last bit of the
|
|
data and the Stop Bit. The UART will
|
|
also expect parity to be present in
|
|
the received data.
|
|
|
|
Bit 2 Number of Stop Bits (STB)
|
|
If set to "1" and using 5-bit data words,
|
|
1.5 Stop Bits are transmitted and
|
|
expected in each data word. For 6, 7
|
|
and 8-bit data words, 2 Stop Bits are
|
|
transmitted and expected. When this bit
|
|
is set to "0", one Stop Bit is used on
|
|
each data word.
|
|
|
|
Bit 1 Word Length Select Bit #1 (WLSB1)
|
|
Bit 0 Word Length Select Bit #0 (WLSB0)
|
|
Together these bits specify the number
|
|
of bits in each data word.
|
|
|
|
1 0 Word Length
|
|
|
|
0 0 5 Data Bits
|
|
0 1 6 Data Bits
|
|
1 0 7 Data Bits
|
|
1 1 8 Data Bits
|
|
|
|
|
|
+0x04 write/read Modem Control Register (MCR)
|
|
|
|
Bit 7 Reserved, always 0.
|
|
|
|
Bit 6 Reserved, always 0.
|
|
|
|
Bit 5 Reserved, always 0.
|
|
|
|
Bit 4 Loop-Back Enable
|
|
When set to "1", the UART transmitter
|
|
and receiver are internally connected
|
|
together to allow diagnostic operations.
|
|
In addition, the UART modem control
|
|
outputs are connected to the UART modem
|
|
control inputs. CTS is connected to RTS,
|
|
DTR is connected to DSR, OUT1 is
|
|
connected to RI, and OUT 2 is connected
|
|
to DCD.
|
|
|
|
Bit 3 OUT 2
|
|
An auxiliary output that the host
|
|
processor may set high or low.
|
|
In the IBM PC serial adapter (and most
|
|
clones), OUT 2 is used to tri-state
|
|
(disable) the interrupt signal from the
|
|
8250/16450/16550 UART.
|
|
|
|
Bit 2 OUT 1
|
|
An auxiliary output that the host
|
|
processor may set high or low.
|
|
This output is not used on the IBM PC
|
|
serial adapter.
|
|
|
|
Bit 1 Request to Send (RTS)
|
|
When set to "1", the output of the UART
|
|
-RTS line is Low (Active).
|
|
|
|
Bit 0 Data Terminal Ready (DTR)
|
|
When set to "1", the output of the UART
|
|
-DTR line is Low (Active).
|
|
|
|
|
|
+0x05 write/read Line Status Register (LSR)
|
|
|
|
Bit 7 Error in Receiver FIFO
|
|
On the 8250/16450 UART, this bit is zero.
|
|
This bit is set to "1" when any of
|
|
the bytes in the FIFO have one or more
|
|
of the following error conditions: PE,
|
|
FE, or BI.
|
|
|
|
Bit 6 Transmitter Empty (TEMT)
|
|
When set to "1", there are no words
|
|
remaining in the transmit FIFO or the
|
|
transmit shift register. The
|
|
transmitter is completely idle.
|
|
|
|
Bit 5 Transmitter Holding Register Empty (THRE)
|
|
When set to "1", the FIFO (or holding
|
|
register) now has room for at least one
|
|
additional word to transmit. The
|
|
transmitter may still be transmitting
|
|
when this bit is set to "1".
|
|
|
|
Bit 4 Break Interrupt (BI)
|
|
The receiver has detected a Break signal.
|
|
|
|
Bit 3 Framing Error (FE)
|
|
A Start Bit was detected but the Stop
|
|
Bit did not appear at the expected time.
|
|
The received word is probably garbled.
|
|
|
|
Bit 2 Parity Error (PE)
|
|
The parity bit was incorrect for the
|
|
word received.
|
|
|
|
Bit 1 Overrun Error (OE)
|
|
A new word was received and there
|
|
was no room in the receive buffer. The
|
|
newly-arrived word in the shift
|
|
register is discarded. On 8250/16450
|
|
UARTs, the word in the holding
|
|
register is discarded and the newly-
|
|
arrived word is put in the holding
|
|
register.
|
|
|
|
Bit 0 Data Ready (DR)
|
|
One or more words are in the
|
|
receive FIFO that the host may read.
|
|
A word must be completely received
|
|
and moved from the shift register into
|
|
the FIFO (or holding register for
|
|
8250/16450 designs) before this bit is
|
|
set.
|
|
|
|
|
|
+0x06 write/read Modem Status Register (MSR)
|
|
|
|
Bit 7 Data Carrier Detect (DCD)
|
|
Reflects the state of the DCD line
|
|
on the UART.
|
|
|
|
Bit 6 Ring Indicator (RI)
|
|
Reflects the state of the RI line on
|
|
the UART.
|
|
|
|
Bit 5 Data Set Ready (DSR)
|
|
Reflects the state of the DSR line on
|
|
the UART.
|
|
|
|
Bit 4 Clear To Send (CTS)
|
|
Reflects the state of the CTS line on
|
|
the UART.
|
|
|
|
Bit 3 Delta Data Carrier Detect (DDCD)
|
|
Set to "1" if the -DCD line has changed
|
|
state one more more times since the last
|
|
time the MSR was read by the host.
|
|
|
|
Bit 2 Trailing Edge Ring Indicator (TERI)
|
|
Set to "1" if the -RI line has had a
|
|
low to high transition since the last
|
|
time the MSR was read by the host.
|
|
|
|
Bit 1 Delta Data Set Ready (DDSR)
|
|
Set to "1" if the -DSR line has changed
|
|
state one more more times since the last
|
|
time the MSR was read by the host.
|
|
|
|
Bit 0 Delta Clear To Send (DCTS)
|
|
Set to "1" if the -CTS line has changed
|
|
state one more more times since the last
|
|
time the MSR was read by the host.
|
|
|
|
|
|
+0x07 write/read Scratch Register (SCR)
|
|
This register performs no function in the
|
|
UART. Any value can be written by the host to
|
|
this location and read by the host later on.
|
|
</verb>
|
|
|
|
<sect3><heading>Beyond the 16550A UART</heading>
|
|
|
|
<p>Although National Semiconductor has not offered any components
|
|
compatible with the 16550 that provide additional features,
|
|
various other vendors have. Some of these components are described
|
|
below. It should be understood that to effectively utilize these
|
|
improvements, drivers may have to be provided by the chip vendor
|
|
since most of the popular operating systems do not support features
|
|
beyond those provided by the 16550.
|
|
|
|
<descrip>
|
|
<tag>ST16650</tag>By default this part is similar to the NS16550A, but an
|
|
extended 32-byte send and receive buffer can be optionally
|
|
enabled. Made by Startech.
|
|
|
|
<tag>TIL16660</tag>By default this part behaves similar to the NS16550A,
|
|
but an extended 64-byte send and receive buffer can be
|
|
optionally enabled. Made by Texas Instruments.
|
|
|
|
<tag>Hayes ESP</tag>This proprietary plug-in card contains a 2048-byte
|
|
send and receive buffer, and supports data rates
|
|
to 230.4Kbit/sec. Made by Hayes.
|
|
</descrip>
|
|
|
|
<p>In addition to these "dumb" UARTs, many vendors produce
|
|
intelligent serial communication boards. This type of design
|
|
usually provides a microprocessor that interfaces with several
|
|
UARTs, processes and buffers the data, and then alerts the main
|
|
PC processor when necessary. Because the UARTs are not directly
|
|
accessed by the PC processor in this type of communication system,
|
|
it is not necessary for the vendor to use UARTs that are compatible
|
|
with the 8250, 16450, or the 16550 UART. This leaves the
|
|
designer free to components that may have better performance
|
|
characteristics.
|
|
|
|
<!-- 601131 ? -->
|
|
|