c282e9faa8
through fork_trampoline.
This was caused because we were clearing the SR_INT_IE and setting
SR_EXL bits of the status register at the same time. This meant
that if an interrupt happened while this MTC0 was making its way
through the pipeline the exception processing would see the
status register with SR_EXL bit set. This in turn would mean that
the COP_0_EXC_PC would not be updated so the return from exception
would be to an incorrect address.
It is easy to verify this fix by a program that forks in a loop
and the child just exits:
while (1) {
pid_t pid = vfork();
if (pid == 0)
_exit(0);
if (pid != -1)
waitpid(pid, NULL, 0);
}
Also remove two instances where we set SR_EXL bit gratuitously in exception.S.
Approved by: imp (mentor)
|
||
|---|---|---|
| .. | ||
| adm5120 | ||
| alchemy | ||
| atheros | ||
| cavium | ||
| compile | ||
| conf | ||
| idt | ||
| include | ||
| malta | ||
| mips | ||
| rmi | ||
| sentry5 | ||
| sibyte | ||