Neel Natu c3498942a5 Restructure the MSR handling so it is entirely handled by processor-specific ... code. There are only a handful of MSRs common between the two so there isn't too much duplicate functionality. The VT-x code has the following types of MSRs: - MSRs that are unconditionally saved/restored on every guest/host context switch (e.g., MSR_GSBASE). - MSRs that are restored to guest values on entry to vmx_run() and saved before returning. This is an optimization for MSRs that are not used in host kernel context (e.g., MSR_KGSBASE). - MSRs that are emulated and every access by the guest causes a trap into the hypervisor (e.g., MSR_IA32_MISC_ENABLE). Reviewed by: grehan		2014-09-20 02:35:21 +00:00
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acpica	don't set CR4 PSE bit on amd64	2014-07-23 15:53:29 +00:00
amd64	- Use NULL instead of 0 for fpcurthread.	2014-09-18 09:13:20 +00:00
conf	Add mrsas(4) to GENERIC for i386 and amd64.	2014-09-04 21:06:33 +00:00
ia32	x86: Allow users to change PSL_RF via ptrace(PT_SETREGS...)	2013-11-14 15:37:20 +00:00
include	Restructure the MSR handling so it is entirely handled by processor-specific	2014-09-20 02:35:21 +00:00
linux32	Re-gen after r271743 implementing most of	2014-09-18 08:40:00 +00:00
pci	Pull in r267961 and r267973 again. Fix for issues reported will follow.	2014-06-28 03:56:17 +00:00
vmm	Restructure the MSR handling so it is entirely handled by processor-specific	2014-09-20 02:35:21 +00:00
Makefile