824b48eff3
This adds bhnd(4) bus-level support for querying backplane interrupt vector routing, and delegating machine/bridge-specific interrupt handling to the concrete bhnd(4) driver implementation. On bhndb(4) bridged PCI devices, we provide the PCI/MSI interrupt directly to attached cores. On MIPS devices, we report a backplane interrupt count of 0, effectively disabling the bus-level interrupt assignment. This allows mips/broadcom to temporarily continue using hard-coded MIPS IRQs until bhnd_mips PIC support is implemented. Reviewed by: mizhka Approved by: adrian (mentor, implicit)
170 lines
5.5 KiB
C
170 lines
5.5 KiB
C
/*-
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* Copyright (c) 2015 Landon Fuller <landon@landonf.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce at minimum a disclaimer
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* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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* redistribution must be conditioned upon including a substantially
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* similar Disclaimer requirement for further binary redistribution.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
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* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
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* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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* $FreeBSD$
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*/
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#ifndef _BCMA_BCMAVAR_H_
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#define _BCMA_BCMAVAR_H_
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/limits.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include "bcma.h"
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/*
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* Internal definitions shared by bcma(4) driver implementations.
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*/
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/** Base resource ID for per-core agent register allocations */
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#define BCMA_AGENT_RID_BASE 100
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/**
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* Return the device's core index.
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*
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* @param _dinfo The bcma_devinfo instance to query.
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*/
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#define BCMA_DINFO_COREIDX(_dinfo) \
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((_dinfo)->corecfg->core_info.core_idx)
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/** BCMA port identifier. */
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typedef u_int bcma_pid_t;
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#define BCMA_PID_MAX UINT_MAX /**< Maximum bcma_pid_t value */
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/** BCMA per-port region map identifier. */
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typedef u_int bcma_rmid_t;
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#define BCMA_RMID_MAX UINT_MAX /**< Maximum bcma_rmid_t value */
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struct bcma_devinfo;
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struct bcma_corecfg;
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struct bcma_map;
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struct bcma_mport;
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struct bcma_sport;
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int bcma_probe(device_t dev);
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int bcma_attach(device_t dev);
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int bcma_detach(device_t dev);
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int bcma_get_intr_count(device_t dev, device_t child);
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int bcma_get_core_ivec(device_t dev, device_t child,
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u_int intr, uint32_t *ivec);
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int bcma_add_children(device_t bus);
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struct bcma_sport_list *bcma_corecfg_get_port_list(struct bcma_corecfg *cfg,
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bhnd_port_type type);
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struct bcma_devinfo *bcma_alloc_dinfo(device_t bus);
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int bcma_init_dinfo(device_t bus,
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struct bcma_devinfo *dinfo,
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struct bcma_corecfg *corecfg);
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int bcma_dinfo_alloc_agent(device_t bus, device_t child,
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struct bcma_devinfo *dinfo);
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void bcma_free_dinfo(device_t bus,
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struct bcma_devinfo *dinfo);
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struct bcma_corecfg *bcma_alloc_corecfg(u_int core_index, int core_unit,
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uint16_t vendor, uint16_t device, uint8_t hwrev);
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void bcma_free_corecfg(struct bcma_corecfg *corecfg);
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struct bcma_sport *bcma_alloc_sport(bcma_pid_t port_num, bhnd_port_type port_type);
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void bcma_free_sport(struct bcma_sport *sport);
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/** BCMA master port descriptor */
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struct bcma_mport {
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bcma_pid_t mp_num; /**< AXI port identifier (bus-unique) */
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bcma_pid_t mp_vid; /**< AXI master virtual ID (core-unique) */
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STAILQ_ENTRY(bcma_mport) mp_link;
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};
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/** BCMA memory region descriptor */
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struct bcma_map {
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bcma_rmid_t m_region_num; /**< region identifier (port-unique). */
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bhnd_addr_t m_base; /**< base address */
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bhnd_size_t m_size; /**< size */
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int m_rid; /**< bus resource id, or -1. */
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STAILQ_ENTRY(bcma_map) m_link;
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};
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/** BCMA slave port descriptor */
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struct bcma_sport {
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bcma_pid_t sp_num; /**< slave port number (core-unique) */
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bhnd_port_type sp_type; /**< port type */
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u_long sp_num_maps; /**< number of regions mapped to this port */
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STAILQ_HEAD(, bcma_map) sp_maps;
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STAILQ_ENTRY(bcma_sport) sp_link;
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};
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STAILQ_HEAD(bcma_mport_list, bcma_mport);
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STAILQ_HEAD(bcma_sport_list, bcma_sport);
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/** BCMA IP core/block configuration */
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struct bcma_corecfg {
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struct bhnd_core_info core_info; /**< standard core info */
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u_long num_master_ports; /**< number of master port descriptors. */
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struct bcma_mport_list master_ports; /**< master port descriptors */
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u_long num_dev_ports; /**< number of device slave port descriptors. */
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struct bcma_sport_list dev_ports; /**< device port descriptors */
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u_long num_bridge_ports; /**< number of bridge slave port descriptors. */
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struct bcma_sport_list bridge_ports; /**< bridge port descriptors */
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u_long num_wrapper_ports; /**< number of wrapper slave port descriptors. */
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struct bcma_sport_list wrapper_ports; /**< wrapper port descriptors */
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};
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/**
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* BCMA per-device info
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*/
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struct bcma_devinfo {
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struct bhnd_devinfo bhnd_dinfo; /**< superclass device info. */
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struct resource_list resources; /**< Slave port memory regions. */
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struct bcma_corecfg *corecfg; /**< IP core/block config */
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struct bhnd_resource *res_agent; /**< Agent (wrapper) resource, or NULL. Not
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* all bcma(4) cores have or require an agent. */
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int rid_agent; /**< Agent resource ID, or -1 */
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};
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/** BMCA per-instance state */
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struct bcma_softc {
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struct bhnd_softc bhnd_sc; /**< bhnd state */
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};
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#endif /* _BCMA_BCMAVAR_H_ */
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