Jake Burkholder c465faf9d4 The data cache on UltraSPARC III is not directly mapped, so don't assert ... that. This breaks assumptions made by some of the cache flushing code, but UltraSPARC III has different methods for invalidating cache lines anyway.		2002-07-30 05:48:33 +00:00
..
compile
conf	Catch up to rev 1.339 of src/sys/conf/options (PCI_ENABLE_IO_MODES is	2002-07-27 15:28:35 +00:00
ebus
include	Create a new header <machine/_stdint.h> for storing MD parts of	2002-07-29 17:41:23 +00:00
isa
pci	When multiple IOMMUs are present in a system, use a single TSB for all	2002-07-16 18:17:03 +00:00
sbus	Set interrupt clear pointer for SBus slots to point to correct spot.	2002-07-25 20:14:59 +00:00
sparc64	The data cache on UltraSPARC III is not directly mapped, so don't assert	2002-07-30 05:48:33 +00:00