7d671d9b44
ARM Coresight is a solution for debug and trace of complex SoC designs. This includes a collection of drivers for ARM Coresight interconnect devices within a small Coresight framework. Supported devices are: o Embedded Trace Macrocell v4 (ETMv4) o Funnel o Dynamic Replicator o Trace Memory Controller (TMC) o CPU debug module Devices are connected to each other internally in SoC and the configuration of each device endpoints is described in FDT. Typical trace flow (as found on Qualcomm Snapdragon 410e): CPU0 -> ETM0 -> funnel1 -> funnel0 -> ETF -> replicator -> ETR -> DRAM CPU1 -> ETM1 -^ CPU2 -> ETM2 -^ CPU3 -> ETM3 -^ Note that both Embedded Trace FIFO (ETF) and Embedded Trace Router (ETR) are hardware configurations of TMC. This is required for upcoming HWPMC tracing support. This is tested on single-core system only. Reviewed by: andrew (partially) Sponsored by: DARPA, AFRL Differential Revision: https://reviews.freebsd.org/D14618
138 lines
3.9 KiB
C
138 lines
3.9 KiB
C
/*-
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* Copyright (c) 2018 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _ARM64_CORESIGHT_CORESIGHT_H_
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#define _ARM64_CORESIGHT_CORESIGHT_H_
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#include <dev/ofw/openfirm.h>
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#define CORESIGHT_ITCTRL 0xf00
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#define CORESIGHT_CLAIMSET 0xfa0
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#define CORESIGHT_CLAIMCLR 0xfa4
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#define CORESIGHT_LAR 0xfb0
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#define CORESIGHT_UNLOCK 0xc5acce55
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#define CORESIGHT_LSR 0xfb4
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#define CORESIGHT_AUTHSTATUS 0xfb8
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#define CORESIGHT_DEVID 0xfc8
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#define CORESIGHT_DEVTYPE 0xfcc
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enum cs_dev_type {
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CORESIGHT_ETMV4,
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CORESIGHT_TMC,
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CORESIGHT_DYNAMIC_REPLICATOR,
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CORESIGHT_FUNNEL,
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CORESIGHT_CPU_DEBUG,
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};
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struct coresight_device {
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TAILQ_ENTRY(coresight_device) link;
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device_t dev;
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phandle_t node;
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enum cs_dev_type dev_type;
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struct coresight_platform_data *pdata;
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};
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struct endpoint {
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TAILQ_ENTRY(endpoint) link;
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phandle_t my_node;
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phandle_t their_node;
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phandle_t dev_node;
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boolean_t slave;
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int reg;
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struct coresight_device *cs_dev;
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LIST_ENTRY(endpoint) endplink;
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};
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struct coresight_platform_data {
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int cpu;
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int in_ports;
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int out_ports;
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struct mtx mtx_lock;
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TAILQ_HEAD(endpoint_list, endpoint) endpoints;
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};
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struct coresight_desc {
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struct coresight_platform_data *pdata;
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device_t dev;
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enum cs_dev_type dev_type;
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};
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TAILQ_HEAD(coresight_device_list, coresight_device);
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#define ETM_N_COMPRATOR 16
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struct etm_state {
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uint32_t trace_id;
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};
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struct etr_state {
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boolean_t started;
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uint32_t cycle;
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uint32_t offset;
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uint32_t low;
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uint32_t high;
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uint32_t bufsize;
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uint32_t flags;
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#define ETR_FLAG_ALLOCATE (1 << 0)
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#define ETR_FLAG_RELEASE (1 << 1)
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};
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struct coresight_event {
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LIST_HEAD(, endpoint) endplist;
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uint64_t addr[ETM_N_COMPRATOR];
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uint32_t naddr;
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uint8_t excp_level;
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enum cs_dev_type src;
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enum cs_dev_type sink;
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struct etr_state etr;
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struct etm_state etm;
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};
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struct etm_config {
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uint64_t addr[ETM_N_COMPRATOR];
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uint32_t naddr;
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uint8_t excp_level;
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};
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struct coresight_platform_data * coresight_get_platform_data(device_t dev);
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struct endpoint * coresight_get_output_endpoint(struct coresight_platform_data *pdata);
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struct coresight_device * coresight_get_output_device(struct endpoint *endp, struct endpoint **);
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int coresight_register(struct coresight_desc *desc);
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int coresight_init_event(int cpu, struct coresight_event *event);
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void coresight_enable(int cpu, struct coresight_event *event);
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void coresight_disable(int cpu, struct coresight_event *event);
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void coresight_read(int cpu, struct coresight_event *event);
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#endif /* !_ARM64_CORESIGHT_CORESIGHT_H_ */
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