352e51d169
mips32r2 and mips64r2 (and close relatives) processors. There presently is support for ADMtek ADM5120, A mips 4Kc in a malta board, the RB533 routerboard (based on IDT RC32434) and some preliminary support for sibtye/broadcom designs. Other hardware support will be forthcomcing. This port boots multiuser under gxemul emulating the malta board and also bootstraps on the hardware whose support is forthcoming... Oleksandr Tymoshenko, Wojciech Koszek, Warner Losh, Olivier Houchard, Randall Stewert and others that have contributed to the mips2 and/or mips2-jnpr perforce branches. Juniper contirbuted a generic mips port late in the life cycle of the misp2 branch. Warner Losh merged the mips2 and Juniper code bases, and others list above have worked for the past several months to get to multiuser. In addition, the mips2 work owe a debt to the trail blazing efforts of the original mips branch in perforce done by Juli Mallett.
110 lines
3.7 KiB
C
110 lines
3.7 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)npx.h 5.3 (Berkeley) 1/18/91
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* $FreeBSD$
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*/
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/*
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* Floating Point Data Structures and Constants
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* W. Jolitz 1/90
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*/
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#ifndef _MACHINE_FPU_H_
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#define _MACHINE_FPU_H_
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/* Contents of each x87 floating point accumulator */
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struct fpacc87 {
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u_char fp_bytes[10];
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};
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/* Contents of each SSE extended accumulator */
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struct xmmacc {
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u_char xmm_bytes[16];
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};
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struct envxmm {
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u_int16_t en_cw; /* control word (16bits) */
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u_int16_t en_sw; /* status word (16bits) */
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u_int8_t en_tw; /* tag word (8bits) */
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u_int8_t en_zero;
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u_int16_t en_opcode; /* opcode last executed (11 bits ) */
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u_int64_t en_rip; /* floating point instruction pointer */
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u_int64_t en_rdp; /* floating operand pointer */
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u_int32_t en_mxcsr; /* SSE sontorol/status register */
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u_int32_t en_mxcsr_mask; /* valid bits in mxcsr */
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};
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struct savefpu {
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struct envxmm sv_env;
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struct {
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struct fpacc87 fp_acc;
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u_char fp_pad[6]; /* padding */
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} sv_fp[8];
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struct xmmacc sv_xmm[16];
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u_char sv_pad[96];
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} __aligned(16);
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/*
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* The hardware default control word for i387's and later coprocessors is
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* 0x37F, giving:
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*
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* round to nearest
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* 64-bit precision
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* all exceptions masked.
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*
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* FreeBSD/i386 uses 53 bit precision for things like fadd/fsub/fsqrt etc
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* because of the difference between memory and fpu register stack arguments.
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* If its using an intermediate fpu register, it has 80/64 bits to work
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* with. If it uses memory, it has 64/53 bits to work with. However,
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* gcc is aware of this and goes to a fair bit of trouble to make the
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* best use of it.
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*
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* This is mostly academic for AMD64, because the ABI prefers the use
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* SSE2 based math. For FreeBSD/amd64, we go with the default settings.
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*/
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#define __INITIAL_FPUCW__ 0x037F
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#define __INITIAL_MXCSR__ 0x1F80
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#define __INITIAL_MXCSR_MASK__ 0xFFBF
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#ifdef _KERNEL
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int fpudna(void);
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void fpudrop(void);
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void fpuexit(struct thread *td);
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int fpuformat(void);
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int fpugetregs(struct thread *td, struct savefpu *addr);
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void fpuinit(void);
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void fpusetregs(struct thread *td, struct savefpu *addr);
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int fputrap(void);
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#endif
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#endif /* !_MACHINE_FPU_H_ */
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