061b38cdcc
"pin_list" allows to specify child pins as a list of pin numbers. Existing hint "pins" serves the same purpose but with a 32-bit wide bit mask. One problem with that is that a controller can have more than 32 pins. One example is amdgpio. Also, a list of numbers is a little bit more human friendly than a matching bit mask. As a side note, it seems that in FDT pins are typically specified by their numbers as well. This commit also adds accessors for instance variables (IVARs) that define the child pins. My primary goal is to allow a child to be configured programmatically rather than via hints (assuming that FDT is not supported on a platform). Also, while a child should not care about specific pin numbers that are allocated to it, it could be interested in how many were actually assigned to it. While there, I removed "flags" instance variable. It was unused. Reviewed by: mizhka MFC after: 2 weeks Differential Revision: https://reviews.freebsd.org/D20459
185 lines
5.5 KiB
Groff
185 lines
5.5 KiB
Groff
.\" Copyright (c) 2013, Sean Bruno <sbruno@freebsd.org>
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.\" All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
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.\" modification, are permitted provided that the following conditions
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.\" are met:
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.\" 1. Redistributions of source code must retain the above copyright
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.\" notice, this list of conditions and the following disclaimer.
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.\" 2. Redistributions in binary form must reproduce the above copyright
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.\" notice, this list of conditions and the following disclaimer in the
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.\" documentation and/or other materials provided with the distribution.
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.\"
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.\" THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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.\" ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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.\" FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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.\" DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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.\" OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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.\" HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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.\" LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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.\" OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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.\" SUCH DAMAGE.
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.\"
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.\" $FreeBSD$
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.\"
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.Dd June 27, 2019
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.Dt GPIO 4
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.Os
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.Sh NAME
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.Nm gpiobus
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.Nd GPIO bus system
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.Sh SYNOPSIS
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To compile these devices into your kernel and use the device hints, place the
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following lines in your kernel configuration file:
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.Bd -ragged -offset indent
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.Cd "device gpio"
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.Cd "device gpioc"
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.Cd "device gpioiic"
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.Cd "device gpioled"
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.Ed
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.Pp
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Additional device entries for the
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.Li ARM
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architecture include:
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.Bd -ragged -offset indent
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.Cd "device a10_gpio"
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.Cd "device bcm_gpio"
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.Cd "device imx51_gpio"
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.Cd "device lpcgpio"
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.Cd "device mv_gpio"
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.Cd "device ti_gpio"
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.Cd "device gpio_avila"
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.Cd "device gpio_cambria"
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.Cd "device zy7_gpio"
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.Cd "device pxagpio"
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.Ed
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.Pp
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Additional device entries for the
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.Li MIPS
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architecture include:
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.Bd -ragged -offset indent
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.Cd "device ar71xxx_gpio"
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.Cd "device octeon_gpio"
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.Cd "device rt305_gpio"
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.Ed
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.Pp
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Additional device entries for the
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.Li POWERPC
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architecture include:
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.Bd -ragged -offset indent
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.Cd "device wiigpio"
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.Cd "device macgpio"
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.Ed
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.Sh DESCRIPTION
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The
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.Nm
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system provides a simple interface to the GPIO pins that are usually
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available on embedded architectures and can provide bit banging style
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devices to the system.
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.Pp
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The acronym
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.Li GPIO
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means
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.Dq General-Purpose Input/Output.
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.Pp
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The BUS physically consists of multiple pins that can be configured
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for input/output, IRQ delivery, SDA/SCL
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.Em iicbus
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use, etc.
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.Pp
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On some embedded architectures (like MIPS), discovery of the bus and
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configuration of the pins is done via
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.Xr device.hints 5
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in the platform's kernel
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.Xr config 5
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file.
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.Pp
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On some others (like ARM), where
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.Xr FDT 4
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is used to describe the device tree, the bus discovery is done via the DTS
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passed to the kernel, being either statically compiled in, or by a variety
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of ways where the boot loader (or Open Firmware enabled system) passes the
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DTS blob to the kernel at boot.
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.Pp
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On a
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.Xr device.hints 5
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based system these hints can be used to configure drivers for devices
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attached to
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.Nm
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pins:
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.Bl -tag -width ".Va hint.driver.unit.pin_list"
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.It Va hint.driver.unit.at
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The
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.Nm gpiobus
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where the device is attached.
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For example,
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.Qq gpiobus0 .
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.Ar driver
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and
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.Ar unit
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are the driver name and the unit number for the device driver.
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.It Va hint.driver.unit.pins
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This is a bitmask of the pins on the
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.Nm gpiobus
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that are connected to the device.
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The pins will be allocated to the specified driver instance.
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Only pins with numbers from 0 to 31 can be specified using this hint.
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.It Va hint.driver.unit.pin_list
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This is a list of pin numbers of pins on the
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.Nm gpiobus
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that are connected to the device.
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The pins will be allocated to the specified driver instance.
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This is a more user friendly alternative to the
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.Ar pins
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hint.
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Additionally, this hint allows specifying pin numbers greater than 31.
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The numbers can be decimal or hexadecimal with 0x prefix.
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Any non-digit character can be used as a separator.
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For example, it can be a comma, a slash or a space.
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The separator can be followed by any number of space characters.
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.El
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.Pp
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The following
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.Xr device.hints 5
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are only provided by the
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.Cd ar71xx_gpio
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driver:
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.Bl -tag -width ".Va hint.gpio.function_clear"
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.It Va hint.gpio.%d.pinmask
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This is a bitmask of pins on the GPIO board that we would like to expose
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for use to the host operating system.
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To expose pin 0, 4 and 7, use the bitmask of
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10010001 converted to the hexadecimal value 0x0091.
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.It Va hint.gpio.%d.pinon
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This is a bitmask of pins on the GPIO board that will be set to ON at host
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start.
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To set pin 2, 5 and 13 to be set ON at boot, use the bitmask of
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10000000010010 converted to the hexadecimal value 0x2012.
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.It Va hint.gpio.function_set
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.It Va hint.gpio.function_clear
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These are bitmasks of pins that will remap a pin to handle a specific
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function (USB, UART TX/RX, etc) in the Atheros function registers.
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This is mainly used to set/clear functions that we need when they are set up or
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not set up by uBoot.
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.El
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.Pp
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Simply put, each pin of the GPIO interface is connected to an input/output
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of some device in a system.
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.Sh SEE ALSO
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.Xr gpioiic 4 ,
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.Xr gpioled 4 ,
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.Xr iicbus 4 ,
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.Xr device.hints 5 ,
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.Xr gpioctl 8
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.Sh HISTORY
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The
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.Nm
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manual page first appeared in
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.Fx 10.0 .
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.Sh AUTHORS
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This
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manual page was written by
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.An Sean Bruno Aq Mt sbruno@FreeBSD.org .
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