298 lines
7.5 KiB
C
298 lines
7.5 KiB
C
/*-
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* Copyright (c) 1999 Andrew Gallatin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#define __RMAN_RESOURCE_VISIBLE
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <alpha/pci/tsunamireg.h>
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#include <alpha/pci/tsunamivar.h>
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#include <alpha/pci/pcibus.h>
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#include <machine/resource.h>
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#include <machine/bwx.h>
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#include "alphapci_if.h"
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#include "pcib_if.h"
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struct tsunami_hose_softc {
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struct bwx_space io; /* accessor for ports */
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struct bwx_space mem; /* accessor for memory */
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struct rman io_rman; /* resource manager for ports */
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struct rman mem_rman; /* resource manager for memory */
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};
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static devclass_t pcib_devclass;
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static int
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tsunami_pcib_probe(device_t dev)
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{
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struct tsunami_hose_softc *sc = device_get_softc(dev);
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device_t child;
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device_set_desc(dev, "21271 PCI host bus adapter");
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pci_init_resources(); /* XXX probably don't need */
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child = device_add_child(dev, "pci", -1);
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bwx_init_space(&sc->io, KV(TSUNAMI_IO(device_get_unit(dev))));
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bwx_init_space(&sc->mem, KV(TSUNAMI_MEM(device_get_unit(dev))));
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sc->io_rman.rm_start = 0;
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sc->io_rman.rm_end = ~0u;
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sc->io_rman.rm_type = RMAN_ARRAY;
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sc->io_rman.rm_descr = "I/O ports";
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if (rman_init(&sc->io_rman)
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|| rman_manage_region(&sc->io_rman, 0x0, (1L << 32)))
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panic("tsunami_pcib_probe: io_rman");
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sc->mem_rman.rm_start = 0;
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sc->mem_rman.rm_end = ~0u;
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sc->mem_rman.rm_type = RMAN_ARRAY;
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sc->mem_rman.rm_descr = "I/O memory";
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if (rman_init(&sc->mem_rman)
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|| rman_manage_region(&sc->mem_rman, 0x0, (1L << 32)))
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panic("tsunami_pcib_probe: mem_rman");
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/*
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* Replace the temporary bootstrap spaces with real onys. This
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* isn't stictly necessary but it keeps things tidy.
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*/
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if (device_get_unit(dev) == 0) {
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busspace_isa_io = (struct alpha_busspace *) &sc->io;
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busspace_isa_mem = (struct alpha_busspace *) &sc->mem;
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}
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return 0;
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}
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static int
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tsunami_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
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{
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if (which == PCIB_IVAR_BUS) {
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*result = 0;
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}
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return ENOENT;
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}
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static void *
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tsunami_pcib_cvt_dense(device_t dev, vm_offset_t addr)
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{
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int h = device_get_unit(dev);
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addr &= 0xffffffffUL;
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return (void *) KV(addr | TSUNAMI_MEM(h));
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}
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static void *
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tsunami_pcib_cvt_bwx(device_t dev, vm_offset_t addr)
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{
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int h = device_get_unit(dev);
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addr &= 0xffffffffUL;
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return (void *) KV(addr | TSUNAMI_MEM(h));
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}
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static kobj_t
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tsunami_pcib_get_bustag(device_t dev, int type)
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{
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struct tsunami_hose_softc *sc = device_get_softc(dev);
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switch (type) {
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case SYS_RES_IOPORT:
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return (kobj_t) &sc->io;
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case SYS_RES_MEMORY:
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return (kobj_t) &sc->mem;
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}
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return 0;
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}
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static struct rman *
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tsunami_pcib_get_rman(device_t dev, int type)
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{
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struct tsunami_hose_softc *sc = device_get_softc(dev);
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switch (type) {
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case SYS_RES_IOPORT:
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return &sc->io_rman;
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case SYS_RES_MEMORY:
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return &sc->mem_rman;
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}
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return 0;
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}
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static int
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tsunami_pcib_maxslots(device_t dev)
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{
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return 31;
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}
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static void
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tsunami_clear_abort(void)
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{
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alpha_mb();
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alpha_pal_draina();
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}
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static int
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tsunami_check_abort(void)
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{
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/* u_int32_t errbits;*/
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int ba = 0;
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alpha_pal_draina();
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alpha_mb();
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#if 0
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errbits = REGVAL(TSUNAMI_CSR_TSUNAMI_ERR);
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if (errbits & (TSUNAMI_ERR_RCVD_MAS_ABT|TSUNAMI_ERR_RCVD_TAR_ABT))
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ba = 1;
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if (errbits) {
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REGVAL(TSUNAMI_CSR_TSUNAMI_ERR) = errbits;
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alpha_mb();
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alpha_pal_draina();
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}
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#endif
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return ba;
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}
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#define TSUNAMI_CFGADDR(b, s, f, r, h) \
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KV(TSUNAMI_CONF(h) | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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#define CFGREAD(h, b, s, f, r, op, width, type) do { \
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vm_offset_t va; \
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type data; \
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va = TSUNAMI_CFGADDR(b, s, f, r, h); \
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tsunami_clear_abort(); \
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if (badaddr((caddr_t)va, width)) { \
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tsunami_check_abort(); \
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return ~0; \
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} \
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data = op(va); \
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if (tsunami_check_abort()) \
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return ~0; \
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return data; \
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} while (0)
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#define CFGWRITE(h, b, s, f, r, data, op, width) do { \
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vm_offset_t va; \
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va = TSUNAMI_CFGADDR(b, s, f, r, h); \
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tsunami_clear_abort(); \
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if (badaddr((caddr_t)va, width)) \
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return; \
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op(va, data); \
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tsunami_check_abort(); \
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} while (0)
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static u_int32_t
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tsunami_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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int h = device_get_unit(dev);
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switch (width) {
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case 1:
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CFGREAD(h, b, s, f, reg, ldbu, 1, u_int8_t);
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break;
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case 2:
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CFGREAD(h, b, s, f, reg, ldwu, 2, u_int16_t);
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break;
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case 4:
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CFGREAD(h, b, s, f, reg, ldl, 4, u_int32_t);
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}
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return ~0;
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}
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static void
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tsunami_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, u_int32_t val, int width)
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{
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int h = device_get_unit(dev);
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switch (width) {
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case 1:
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CFGWRITE(h, b, s, f, reg, val, stb, 1);
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break;
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case 2:
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CFGWRITE(h, b, s, f, reg, val, stw, 2);
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break;
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case 4:
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CFGWRITE(h, b, s, f, reg, val, stl, 4);
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}
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}
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static device_method_t tsunami_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, tsunami_pcib_probe),
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DEVMETHOD(device_attach, bus_generic_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, tsunami_pcib_read_ivar),
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DEVMETHOD(bus_alloc_resource, alpha_pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, alpha_platform_pci_setup_intr),
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DEVMETHOD(bus_teardown_intr, alpha_platform_pci_teardown_intr),
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/* alphapci interface */
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DEVMETHOD(alphapci_cvt_dense, tsunami_pcib_cvt_dense),
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DEVMETHOD(alphapci_cvt_bwx, tsunami_pcib_cvt_bwx),
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DEVMETHOD(alphapci_get_bustag, tsunami_pcib_get_bustag),
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DEVMETHOD(alphapci_get_rman, tsunami_pcib_get_rman),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, tsunami_pcib_maxslots),
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DEVMETHOD(pcib_read_config, tsunami_pcib_read_config),
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DEVMETHOD(pcib_write_config, tsunami_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, alpha_pci_route_interrupt),
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{ 0, 0 }
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};
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static driver_t tsunami_pcib_driver = {
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"pcib",
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tsunami_pcib_methods,
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sizeof(struct tsunami_hose_softc),
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};
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DRIVER_MODULE(pcib, tsunami, tsunami_pcib_driver, pcib_devclass, 0, 0);
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