31ae3b070d
Tested by: Johannes Lundberg <johannes@brilliantservice.co.jp> PR: kern/209179 Submitted by: Thomas Brierley <tomxor@gmail.com>
401 lines
15 KiB
C
401 lines
15 KiB
C
/*-
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* Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#define ASMC_MAXFANS 6
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struct asmc_softc {
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device_t sc_dev;
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struct mtx sc_mtx;
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int sc_nfan;
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int16_t sms_rest_x;
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int16_t sms_rest_y;
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int16_t sms_rest_z;
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struct sysctl_oid *sc_fan_tree[ASMC_MAXFANS+1];
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struct sysctl_oid *sc_temp_tree;
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struct sysctl_oid *sc_sms_tree;
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struct sysctl_oid *sc_light_tree;
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struct asmc_model *sc_model;
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int sc_rid_port;
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int sc_rid_irq;
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struct resource *sc_ioport;
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struct resource *sc_irq;
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void *sc_cookie;
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int sc_sms_intrtype;
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struct taskqueue *sc_sms_tq;
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struct task sc_sms_task;
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uint8_t sc_sms_intr_works;
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};
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/*
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* Data port.
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*/
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#define ASMC_DATAPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x00)
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#define ASMC_DATAPORT_WRITE(sc, val) \
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bus_write_1(sc->sc_ioport, 0x00, val)
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#define ASMC_STATUS_MASK 0x0f
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/*
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* Command port.
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*/
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#define ASMC_CMDPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x04)
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#define ASMC_CMDPORT_WRITE(sc, val) \
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bus_write_1(sc->sc_ioport, 0x04, val)
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#define ASMC_CMDREAD 0x10
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#define ASMC_CMDWRITE 0x11
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/*
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* Interrupt port.
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*/
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#define ASMC_INTPORT_READ(sc) bus_read_1(sc->sc_ioport, 0x1f)
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/* Number of keys */
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#define ASMC_NKEYS "#KEY" /* RO; 4 bytes */
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/*
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* Fan control via SMC.
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*/
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#define ASMC_KEY_FANCOUNT "FNum" /* RO; 1 byte */
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#define ASMC_KEY_FANMANUAL "FS! " /* RW; 2 bytes */
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#define ASMC_KEY_FANID "F%dID" /* RO; 16 bytes */
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#define ASMC_KEY_FANSPEED "F%dAc" /* RO; 2 bytes */
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#define ASMC_KEY_FANMINSPEED "F%dMn" /* RO; 2 bytes */
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#define ASMC_KEY_FANMAXSPEED "F%dMx" /* RO; 2 bytes */
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#define ASMC_KEY_FANSAFESPEED "F%dSf" /* RO; 2 bytes */
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#define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
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/*
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* Sudden Motion Sensor (SMS).
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*/
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#define ASMC_SMS_INIT1 0xe0
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#define ASMC_SMS_INIT2 0xf8
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#define ASMC_KEY_SMS "MOCN" /* RW; 2 bytes */
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#define ASMC_KEY_SMS_X "MO_X" /* RO; 2 bytes */
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#define ASMC_KEY_SMS_Y "MO_Y" /* RO; 2 bytes */
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#define ASMC_KEY_SMS_Z "MO_Z" /* RO; 2 bytes */
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#define ASMC_KEY_SMS_LOW "MOLT" /* RW; 2 bytes */
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#define ASMC_KEY_SMS_HIGH "MOHT" /* RW; 2 bytes */
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#define ASMC_KEY_SMS_LOW_INT "MOLD" /* RW; 1 byte */
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#define ASMC_KEY_SMS_HIGH_INT "MOHD" /* RW; 1 byte */
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#define ASMC_KEY_SMS_FLAG "MSDW" /* RW; 1 byte */
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#define ASMC_SMS_INTFF 0x60 /* Free fall Interrupt */
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#define ASMC_SMS_INTHA 0x6f /* High Acceleration Interrupt */
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#define ASMC_SMS_INTSH 0x80 /* Shock Interrupt */
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/*
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* Keyboard backlight.
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*/
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#define ASMC_KEY_LIGHTLEFT "ALV0" /* RO; 6 bytes */
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#define ASMC_KEY_LIGHTRIGHT "ALV1" /* RO; 6 bytes */
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#define ASMC_KEY_LIGHTVALUE "LKSB" /* WO; 2 bytes */
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/*
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* Clamshell.
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*/
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#define ASMC_KEY_CLAMSHELL "MSLD" /* RO; 1 byte */
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/*
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* Interrupt keys.
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*/
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#define ASMC_KEY_INTOK "NTOK" /* WO; 1 byte */
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/*
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* Temperatures.
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*
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* First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
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* fourth the Mac Pro 8-core and finally the MacBook Air.
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*
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*/
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/* maximum array size for temperatures including the last NULL */
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#define ASMC_TEMP_MAX 80
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#define ASMC_MB_TEMPS { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
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"TM0P", NULL }
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#define ASMC_MB_TEMPNAMES { "enclosure", "northbridge1", \
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"northbridge2", "heatsink1", \
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"heatsink2", "memory", }
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#define ASMC_MB_TEMPDESCS { "Enclosure Bottomside", \
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"Northbridge Point 1", \
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"Northbridge Point 2", "Heatsink 1", \
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"Heatsink 2", "Memory Bank A", }
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#define ASMC_MB31_TEMPS { "TB0T", "TN0P", "Th0H", "Th1H", \
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"TM0P", NULL }
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#define ASMC_MB31_TEMPNAMES { "enclosure", "northbridge1", \
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"heatsink1", "heatsink2", \
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"memory", }
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#define ASMC_MB31_TEMPDESCS { "Enclosure Bottomside", \
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"Northbridge Point 1", \
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"Heatsink 1","Heatsink 2" \
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"Memory Bank A", }
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#define ASMC_MBP_TEMPS { "TB0T", "Th0H", "Th1H", "Tm0P", \
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"TG0H", "TG0P", "TG0T", NULL }
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#define ASMC_MBP_TEMPNAMES { "enclosure", "heatsink1", \
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"heatsink2", "memory", "graphics", \
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"graphicssink", "unknown", }
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#define ASMC_MBP_TEMPDESCS { "Enclosure Bottomside", \
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"Heatsink 1", "Heatsink 2", \
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"Memory Controller", \
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"Graphics Chip", "Graphics Heatsink", \
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"Unknown", }
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#define ASMC_MBP4_TEMPS { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
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"TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
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"TTF0", "TW0P", NULL }
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#define ASMC_MBP4_TEMPNAMES { "enclosure", "heatsink1", "heatsink2", \
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"heatsink3", "memory", "graphicssink", \
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"graphics", "cpu", "cpu2", "unknown1", \
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"unknown2", "wireless", }
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#define ASMC_MBP4_TEMPDESCS { "Enclosure Bottomside", \
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"Main Heatsink 1", "Main Heatsink 2", \
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"Main Heatsink 3", \
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"Memory Controller", \
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"Graphics Chip Heatsink", \
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"Graphics Chip Diode", \
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"CPU Temperature Diode", "CPU Point 2", \
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"Unknown", "Unknown", \
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"Wireless Module", }
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#define ASMC_MBP5_TEMPS { "TB0T", "TB1T", "TB2T", "TB3T", "TC0D", \
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"TC0F", "TC0P", "TG0D", "TG0F", "TG0H", \
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"TG0P", "TG0T", "TG1H", "TN0D", "TN0P", \
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"TTF0", "Th2H", "Tm0P", "Ts0P", "Ts0S", \
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NULL }
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#define ASMC_MBP5_TEMPNAMES { "enclosure_bottom_0", "enclosure_bottom_1", \
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"enclosure_bottom_2", "enclosure_bottom_3", \
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"cpu_diode", "cpu", \
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"cpu_pin", "gpu_diode", \
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"gpu", "gpu_heatsink", \
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"gpu_pin", "gpu_transistor", \
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"gpu_2_heatsink", "northbridge_diode", \
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"northbridge_pin", "unknown", \
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"heatsink_2", "memory_controller", \
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"pci_express_slot_pin", "pci_express_slot_unk" }
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#define ASMC_MBP5_TEMPDESCS { "Enclosure Bottom 0", "Enclosure Bottom 1", \
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"Enclosure Bottom 2", "Enclosure Bottom 3", \
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"CPU Diode", "CPU ???", \
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"CPU Pin", "GPU Diode", \
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"GPU ???", "GPU Heatsink", \
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"GPU Pin", "GPU Transistor", \
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"GPU 2 Heatsink", "Northbridge Diode", \
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"Northbridge Pin", "Unknown", \
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"Heatsink 2", "Memory Controller", \
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"PCI Express Slot Pin", "PCI Express Slot (unk)" }
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#define ASMC_MBP8_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", "TC0D", \
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"TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
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"TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
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"TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
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"TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
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"Th2H", "Tm0P", "Ts0P", "Ts0S", NULL }
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#define ASMC_MBP8_TEMPNAMES { "enclosure", "TB1T", "TB2T", "TC0C", "TC0D", \
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"TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
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"TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
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"TCTD", "graphics", "TG0P", "THSP", "TM0S", \
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"TMBS", "TP0P", "TPCD", "wireless", "Th1H", \
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"Th2H", "memory", "Ts0P", "Ts0S" }
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#define ASMC_MBP8_TEMPDESCS { "Enclosure Bottomside", "TB1T", "TB2T", "TC0C", "TC0D", \
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"TC0E", "TC0F", "TC0P", "TC1C", "TC2C", \
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"TC3C", "TC4C", "TCFC", "TCGC", "TCSA", \
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"TCTD", "TG0D", "TG0P", "THSP", "TM0S", \
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"TMBS", "TP0P", "TPCD", "TW0P", "Th1H", \
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"Th2H", "Tm0P", "Ts0P", "Ts0S" }
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#define ASMC_MBP11_TEMPS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
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"TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
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"TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
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"TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
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"TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
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"TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
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"TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
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"TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
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"Ts1S", NULL }
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#define ASMC_MBP11_TEMPNAMES { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
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"TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
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"TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
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"TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
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"TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
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"TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
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"TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
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"TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
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"Ts1S" }
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#define ASMC_MBP11_TEMPDESCS { "TB0T", "TB1T", "TB2T", "TBXT", "TC0E", \
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"TC0F", "TC0P", "TC1C", "TC2C", "TC3C", \
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"TC4C", "TCFC", "TCGC", "TCSA", "TCTD", \
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"TCXC", "TG0D", "TG0P", "TG1D", "TG1F", \
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"TG1d", "TH0A", "TH0B", "TH0F", "TH0R", \
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"TH0V", "TH0a", "TH0b", "TH0c", "TM0P", \
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"TM0S", "TP0P", "TPCD", "TW0P", "Ta0P", \
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"TaSP", "Th1H", "Th2H", "Ts0P", "Ts0S", \
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"Ts1S" }
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#define ASMC_MM_TEMPS { "TN0P", "TN1P", NULL }
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#define ASMC_MM_TEMPNAMES { "northbridge1", "northbridge2" }
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#define ASMC_MM_TEMPDESCS { "Northbridge Point 1", \
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"Northbridge Point 2" }
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#define ASMC_MM31_TEMPS { "TC0D", "TC0H", \
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"TC0P", "TH0P", \
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"TN0D", "TN0P", \
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"TW0P", NULL }
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#define ASMC_MM31_TEMPNAMES { "cpu0_die", "cpu0_heatsink", \
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"cpu0_proximity", "hdd_bay", \
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"northbridge_die", \
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"northbridge_proximity", \
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"wireless_module", }
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#define ASMC_MM31_TEMPDESCS { "CPU0 Die Core Temperature", \
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"CPU0 Heatsink Temperature", \
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"CPU0 Proximity Temperature", \
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"HDD Bay Temperature", \
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"Northbridge Die Core Temperature", \
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"Northbridge Proximity Temperature", \
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"Wireless Module Temperature", }
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#define ASMC_MP_TEMPS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
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"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
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"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
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"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
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"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
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"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
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"TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
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NULL }
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#define ASMC_MP_TEMPNAMES { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
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"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
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"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
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"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
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"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
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"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
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"TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
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#define ASMC_MP_TEMPDESCS { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
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"TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
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"TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
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"TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
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"TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
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"TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
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"TM8S", "TM9P", "TM9S", "TN0H", "TS0C", }
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#define ASMC_MP5_TEMPS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
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"TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
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"TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
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"TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
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"TH4F", "TH4P", "TH4V", "THPS", "THTG", \
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"TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
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"TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
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"TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
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"TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
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"TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
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"TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
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"Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
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"Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
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"Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
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"TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", \
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NULL }
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#define ASMC_MP5_TEMPNAMES { "ambient", "TCAC", "TCAD", "TCAG", "TCAH", \
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"TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
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"TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
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"TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
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"TH4F", "TH4P", "TH4V", "THPS", "THTG", \
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"TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
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"TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
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"TM7V", "TM8P", "TM8V", "TM9V", "ram_a1", \
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"ram_a2", "ram_a3", "ram_a4", "ram_b1", "ram_b2", \
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"ram_b3", "ram_b4", "TMHS", "TMLS", "TMPS", \
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"TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
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"Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
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"Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
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"Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
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"TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
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#define ASMC_MP5_TEMPDESCS { "TA0P", "TCAC", "TCAD", "TCAG", "TCAH", \
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"TCAS", "TCBC", "TCBD", "TCBG", "TCBH", \
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"TCBS", "TH1F", "TH1P", "TH1V", "TH2F", \
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"TH2P", "TH2V", "TH3F", "TH3P", "TH3V", \
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"TH4F", "TH4P", "TH4V", "THPS", "THTG", \
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"TM1P", "TM2P", "TM2V", "TM3P", "TM3V", \
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"TM4P", "TM5P", "TM6P", "TM6V", "TM7P", \
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"TM7V", "TM8P", "TM8V", "TM9V", "TMA1", \
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"TMA2", "TMA3", "TMA4", "TMB1", "TMB2", \
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"TMB3", "TMB4", "TMHS", "TMLS", "TMPS", \
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"TMPV", "TMTG", "TN0D", "TN0H", "TNTG", \
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"Te1F", "Te1P", "Te1S", "Te2F", "Te2S", \
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"Te3F", "Te3S", "Te4F", "Te4S", "Te5F", \
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"Te5S", "TeGG", "TeGP", "TeRG", "TeRP", \
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"TeRV", "Tp0C", "Tp1C", "TpPS", "TpTG", }
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#define ASMC_MBA_TEMPS { "TB0T", NULL }
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#define ASMC_MBA_TEMPNAMES { "enclosure" }
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#define ASMC_MBA_TEMPDESCS { "Enclosure Bottom" }
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#define ASMC_MBA3_TEMPS { "TB0T", "TB1T", "TB2T", \
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"TC0D", "TC0E", "TC0P", NULL }
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#define ASMC_MBA3_TEMPNAMES { "enclosure", "TB1T", "TB2T", \
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"TC0D", "TC0E", "TC0P" }
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#define ASMC_MBA3_TEMPDESCS { "Enclosure Bottom", "TB1T", "TB2T", \
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"TC0D", "TC0E", "TC0P" }
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#define ASMC_MBA5_TEMPS { "TB0T", "TB1T", "TB2T", "TC0C", \
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"TC0D", "TC0E", "TC0F", "TC0P", \
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"TC1C", "TC2C", "TCGC", "TCSA", \
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"TCXC", "THSP", "TM0P", "TPCD", \
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"Ta0P", "Th1H", "Tm0P", "Tm1P", \
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"Ts0P", "Ts0S", NULL }
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#define ASMC_MBA5_TEMPNAMES { "enclosure1", "enclosure2", "enclosure3", "TC0C", \
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"cpudiode", "cputemp1", "cputemp2", "cpuproximity", \
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"cpucore1", "cpucore2", "cpupeci", "pecisa", \
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"TCXC", "THSP", "memorybank", "pchdie", \
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"Ta0P", "heatpipe", "mainboardproximity1", "mainboardproximity2", \
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"palmrest", "memoryproximity" }
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#define ASMC_MBA5_TEMPDESCS { "Enclosure Bottom 1", "Enclosure Bottom 2", "Enclosure Bottom 3", "TC0C",\
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"CPU Diode", "CPU Temp 1", "CPU Temp 2", "CPU Proximity", \
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"CPU Core 1", "CPU Core 2", "CPU Peci Core", "PECI SA", \
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"TCXC", "THSP", "Memory Bank A", "PCH Die", \
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"Ta0P", "Heatpipe", "Mainboard Proximity 1", "Mainboard Proximity 2", \
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"Palm Rest", "Memory Proximity" }
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