4732247002
David Somayajulu (davidcs): Overall RDMA Driver infrastructure and iWARP Anand Khoje (akhoje@marvell.com): RoCEv1 verbs implementation MFC after:5 days
676 lines
20 KiB
C
676 lines
20 KiB
C
/*
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* Copyright (c) 2018-2019 Cavium, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __QLNXR_ROCE_H__
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#define __QLNXR_ROCE_H__
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/*
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* roce completion notification queue element
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*/
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struct roce_cnqe {
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struct regpair cq_handle;
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};
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struct roce_cqe_responder {
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struct regpair srq_wr_id;
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struct regpair qp_handle;
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__le32 imm_data_or_inv_r_Key;
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__le32 length;
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__le32 reserved0;
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__le16 rq_cons;
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u8 flags;
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#define ROCE_CQE_RESPONDER_TOGGLE_BIT_MASK 0x1
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#define ROCE_CQE_RESPONDER_TOGGLE_BIT_SHIFT 0
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#define ROCE_CQE_RESPONDER_TYPE_MASK 0x3
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#define ROCE_CQE_RESPONDER_TYPE_SHIFT 1
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#define ROCE_CQE_RESPONDER_INV_FLG_MASK 0x1
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#define ROCE_CQE_RESPONDER_INV_FLG_SHIFT 3
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#define ROCE_CQE_RESPONDER_IMM_FLG_MASK 0x1
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#define ROCE_CQE_RESPONDER_IMM_FLG_SHIFT 4
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#define ROCE_CQE_RESPONDER_RDMA_FLG_MASK 0x1
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#define ROCE_CQE_RESPONDER_RDMA_FLG_SHIFT 5
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#define ROCE_CQE_RESPONDER_RESERVED2_MASK 0x3
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#define ROCE_CQE_RESPONDER_RESERVED2_SHIFT 6
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u8 status;
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};
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struct roce_cqe_requester {
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__le16 sq_cons;
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__le16 reserved0;
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__le32 reserved1;
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struct regpair qp_handle;
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struct regpair reserved2;
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__le32 reserved3;
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__le16 reserved4;
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u8 flags;
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#define ROCE_CQE_REQUESTER_TOGGLE_BIT_MASK 0x1
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#define ROCE_CQE_REQUESTER_TOGGLE_BIT_SHIFT 0
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#define ROCE_CQE_REQUESTER_TYPE_MASK 0x3
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#define ROCE_CQE_REQUESTER_TYPE_SHIFT 1
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#define ROCE_CQE_REQUESTER_RESERVED5_MASK 0x1F
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#define ROCE_CQE_REQUESTER_RESERVED5_SHIFT 3
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u8 status;
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};
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struct roce_cqe_common {
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struct regpair reserved0;
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struct regpair qp_handle;
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__le16 reserved1[7];
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u8 flags;
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#define ROCE_CQE_COMMON_TOGGLE_BIT_MASK 0x1
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#define ROCE_CQE_COMMON_TOGGLE_BIT_SHIFT 0
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#define ROCE_CQE_COMMON_TYPE_MASK 0x3
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#define ROCE_CQE_COMMON_TYPE_SHIFT 1
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#define ROCE_CQE_COMMON_RESERVED2_MASK 0x1F
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#define ROCE_CQE_COMMON_RESERVED2_SHIFT 3
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u8 status;
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};
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/*
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* roce completion queue element
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*/
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union roce_cqe {
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struct roce_cqe_responder resp;
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struct roce_cqe_requester req;
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struct roce_cqe_common cmn;
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};
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/*
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* CQE requester status enumeration
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*/
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enum roce_cqe_requester_status_enum {
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ROCE_CQE_REQ_STS_OK,
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ROCE_CQE_REQ_STS_BAD_RESPONSE_ERR,
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ROCE_CQE_REQ_STS_LOCAL_LENGTH_ERR,
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ROCE_CQE_REQ_STS_LOCAL_QP_OPERATION_ERR,
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ROCE_CQE_REQ_STS_LOCAL_PROTECTION_ERR,
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ROCE_CQE_REQ_STS_MEMORY_MGT_OPERATION_ERR,
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ROCE_CQE_REQ_STS_REMOTE_INVALID_REQUEST_ERR,
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ROCE_CQE_REQ_STS_REMOTE_ACCESS_ERR,
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ROCE_CQE_REQ_STS_REMOTE_OPERATION_ERR,
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ROCE_CQE_REQ_STS_RNR_NAK_RETRY_CNT_ERR,
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ROCE_CQE_REQ_STS_TRANSPORT_RETRY_CNT_ERR,
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ROCE_CQE_REQ_STS_WORK_REQUEST_FLUSHED_ERR,
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MAX_ROCE_CQE_REQUESTER_STATUS_ENUM
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};
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/*
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* CQE responder status enumeration
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*/
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enum roce_cqe_responder_status_enum {
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ROCE_CQE_RESP_STS_OK,
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ROCE_CQE_RESP_STS_LOCAL_ACCESS_ERR,
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ROCE_CQE_RESP_STS_LOCAL_LENGTH_ERR,
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ROCE_CQE_RESP_STS_LOCAL_QP_OPERATION_ERR,
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ROCE_CQE_RESP_STS_LOCAL_PROTECTION_ERR,
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ROCE_CQE_RESP_STS_MEMORY_MGT_OPERATION_ERR,
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ROCE_CQE_RESP_STS_REMOTE_INVALID_REQUEST_ERR,
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ROCE_CQE_RESP_STS_WORK_REQUEST_FLUSHED_ERR,
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MAX_ROCE_CQE_RESPONDER_STATUS_ENUM
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};
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/*
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* CQE type enumeration
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*/
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enum roce_cqe_type {
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ROCE_CQE_TYPE_REQUESTER,
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ROCE_CQE_TYPE_RESPONDER_RQ,
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ROCE_CQE_TYPE_RESPONDER_SRQ,
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ROCE_CQE_TYPE_INVALID,
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MAX_ROCE_CQE_TYPE
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};
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/*
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* memory window type enumeration
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*/
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enum roce_mw_type {
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ROCE_MW_TYPE_1,
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ROCE_MW_TYPE_2A,
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MAX_ROCE_MW_TYPE
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};
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struct roce_rq_sge {
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struct regpair addr;
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__le32 length;
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__le32 flags;
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#define ROCE_RQ_SGE_L_KEY_MASK 0x3FFFFFF
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#define ROCE_RQ_SGE_L_KEY_SHIFT 0
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#define ROCE_RQ_SGE_NUM_SGES_MASK 0x7
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#define ROCE_RQ_SGE_NUM_SGES_SHIFT 26
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#define ROCE_RQ_SGE_RESERVED0_MASK 0x7
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#define ROCE_RQ_SGE_RESERVED0_SHIFT 29
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};
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struct roce_sq_atomic_wqe {
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struct regpair remote_va;
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__le32 xrc_srq;
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u8 req_type;
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u8 flags;
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#define ROCE_SQ_ATOMIC_WQE_COMP_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_COMP_FLG_SHIFT 0
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#define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_ATOMIC_WQE_SE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_SE_FLG_SHIFT 3
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#define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_ATOMIC_WQE_RESERVED0_MASK 0x7
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#define ROCE_SQ_ATOMIC_WQE_RESERVED0_SHIFT 5
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u8 reserved1;
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u8 prev_wqe_size;
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struct regpair swap_data;
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__le32 r_key;
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__le32 reserved2;
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struct regpair cmp_data;
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struct regpair reserved3;
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};
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/*
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* First element (16 bytes) of atomic wqe
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*/
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struct roce_sq_atomic_wqe_1st {
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struct regpair remote_va;
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__le32 xrc_srq;
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u8 req_type;
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u8 flags;
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#define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_1ST_COMP_FLG_SHIFT 0
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#define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_1ST_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_1ST_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_1ST_SE_FLG_SHIFT 3
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#define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_ATOMIC_WQE_1ST_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_MASK 0x7
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#define ROCE_SQ_ATOMIC_WQE_1ST_RESERVED0_SHIFT 5
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u8 reserved1;
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u8 prev_wqe_size;
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};
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/*
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* Second element (16 bytes) of atomic wqe
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*/
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struct roce_sq_atomic_wqe_2nd {
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struct regpair swap_data;
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__le32 r_key;
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__le32 reserved2;
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};
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/*
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* Third element (16 bytes) of atomic wqe
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*/
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struct roce_sq_atomic_wqe_3rd {
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struct regpair cmp_data;
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struct regpair reserved3;
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};
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struct roce_sq_bind_wqe {
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struct regpair addr;
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__le32 l_key;
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u8 req_type;
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u8 flags;
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#define ROCE_SQ_BIND_WQE_COMP_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_COMP_FLG_SHIFT 0
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#define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_BIND_WQE_SE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_SE_FLG_SHIFT 3
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#define ROCE_SQ_BIND_WQE_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_BIND_WQE_RESERVED0_MASK 0x7
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#define ROCE_SQ_BIND_WQE_RESERVED0_SHIFT 5
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u8 access_ctrl;
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#define ROCE_SQ_BIND_WQE_REMOTE_READ_MASK 0x1
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#define ROCE_SQ_BIND_WQE_REMOTE_READ_SHIFT 0
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#define ROCE_SQ_BIND_WQE_REMOTE_WRITE_MASK 0x1
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#define ROCE_SQ_BIND_WQE_REMOTE_WRITE_SHIFT 1
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#define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_MASK 0x1
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#define ROCE_SQ_BIND_WQE_ENABLE_ATOMIC_SHIFT 2
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#define ROCE_SQ_BIND_WQE_LOCAL_READ_MASK 0x1
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#define ROCE_SQ_BIND_WQE_LOCAL_READ_SHIFT 3
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#define ROCE_SQ_BIND_WQE_LOCAL_WRITE_MASK 0x1
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#define ROCE_SQ_BIND_WQE_LOCAL_WRITE_SHIFT 4
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#define ROCE_SQ_BIND_WQE_RESERVED1_MASK 0x7
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#define ROCE_SQ_BIND_WQE_RESERVED1_SHIFT 5
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u8 prev_wqe_size;
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u8 bind_ctrl;
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#define ROCE_SQ_BIND_WQE_ZERO_BASED_MASK 0x1
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#define ROCE_SQ_BIND_WQE_ZERO_BASED_SHIFT 0
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#define ROCE_SQ_BIND_WQE_MW_TYPE_MASK 0x1
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#define ROCE_SQ_BIND_WQE_MW_TYPE_SHIFT 1
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#define ROCE_SQ_BIND_WQE_RESERVED2_MASK 0x3F
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#define ROCE_SQ_BIND_WQE_RESERVED2_SHIFT 2
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u8 reserved3[2];
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u8 length_hi;
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__le32 length_lo;
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__le32 parent_l_key;
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__le32 reserved6;
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};
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/*
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* First element (16 bytes) of bind wqe
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*/
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struct roce_sq_bind_wqe_1st {
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struct regpair addr;
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__le32 l_key;
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u8 req_type;
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u8 flags;
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#define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_COMP_FLG_SHIFT 0
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#define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_BIND_WQE_1ST_SE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_SE_FLG_SHIFT 3
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#define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_BIND_WQE_1ST_RESERVED0_MASK 0x7
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#define ROCE_SQ_BIND_WQE_1ST_RESERVED0_SHIFT 5
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u8 access_ctrl;
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#define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_REMOTE_READ_SHIFT 0
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#define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_REMOTE_WRITE_SHIFT 1
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#define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_ENABLE_ATOMIC_SHIFT 2
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#define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_LOCAL_READ_SHIFT 3
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#define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_MASK 0x1
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#define ROCE_SQ_BIND_WQE_1ST_LOCAL_WRITE_SHIFT 4
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#define ROCE_SQ_BIND_WQE_1ST_RESERVED1_MASK 0x7
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#define ROCE_SQ_BIND_WQE_1ST_RESERVED1_SHIFT 5
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u8 prev_wqe_size;
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};
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/*
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* Second element (16 bytes) of bind wqe
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*/
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struct roce_sq_bind_wqe_2nd {
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u8 bind_ctrl;
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#define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_MASK 0x1
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#define ROCE_SQ_BIND_WQE_2ND_ZERO_BASED_SHIFT 0
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#define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_MASK 0x1
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#define ROCE_SQ_BIND_WQE_2ND_MW_TYPE_SHIFT 1
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#define ROCE_SQ_BIND_WQE_2ND_RESERVED2_MASK 0x3F
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#define ROCE_SQ_BIND_WQE_2ND_RESERVED2_SHIFT 2
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u8 reserved3[2];
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u8 length_hi;
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__le32 length_lo;
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__le32 parent_l_key;
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__le32 reserved6;
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};
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/*
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* Structure with only the SQ WQE common fields. Size is of one SQ element (16B)
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*/
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struct roce_sq_common_wqe {
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__le32 reserved1[3];
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u8 req_type;
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u8 flags;
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#define ROCE_SQ_COMMON_WQE_COMP_FLG_MASK 0x1
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#define ROCE_SQ_COMMON_WQE_COMP_FLG_SHIFT 0
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#define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_COMMON_WQE_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_COMMON_WQE_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_COMMON_WQE_SE_FLG_MASK 0x1
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#define ROCE_SQ_COMMON_WQE_SE_FLG_SHIFT 3
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#define ROCE_SQ_COMMON_WQE_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_COMMON_WQE_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_COMMON_WQE_RESERVED0_MASK 0x7
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#define ROCE_SQ_COMMON_WQE_RESERVED0_SHIFT 5
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u8 reserved2;
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u8 prev_wqe_size;
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};
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struct roce_sq_fmr_wqe {
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struct regpair addr;
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__le32 l_key;
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u8 req_type;
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u8 flags;
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#define ROCE_SQ_FMR_WQE_COMP_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_COMP_FLG_SHIFT 0
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#define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_FMR_WQE_SE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_SE_FLG_SHIFT 3
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#define ROCE_SQ_FMR_WQE_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_FMR_WQE_RESERVED0_MASK 0x7
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#define ROCE_SQ_FMR_WQE_RESERVED0_SHIFT 5
|
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u8 access_ctrl;
|
|
#define ROCE_SQ_FMR_WQE_REMOTE_READ_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_REMOTE_READ_SHIFT 0
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#define ROCE_SQ_FMR_WQE_REMOTE_WRITE_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_REMOTE_WRITE_SHIFT 1
|
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#define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_ENABLE_ATOMIC_SHIFT 2
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#define ROCE_SQ_FMR_WQE_LOCAL_READ_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_LOCAL_READ_SHIFT 3
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#define ROCE_SQ_FMR_WQE_LOCAL_WRITE_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_LOCAL_WRITE_SHIFT 4
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#define ROCE_SQ_FMR_WQE_RESERVED1_MASK 0x7
|
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#define ROCE_SQ_FMR_WQE_RESERVED1_SHIFT 5
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u8 prev_wqe_size;
|
|
u8 fmr_ctrl;
|
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#define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_MASK 0x1F
|
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#define ROCE_SQ_FMR_WQE_PAGE_SIZE_LOG_SHIFT 0
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#define ROCE_SQ_FMR_WQE_ZERO_BASED_MASK 0x1
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#define ROCE_SQ_FMR_WQE_ZERO_BASED_SHIFT 5
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#define ROCE_SQ_FMR_WQE_BIND_EN_MASK 0x1
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#define ROCE_SQ_FMR_WQE_BIND_EN_SHIFT 6
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#define ROCE_SQ_FMR_WQE_RESERVED2_MASK 0x1
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#define ROCE_SQ_FMR_WQE_RESERVED2_SHIFT 7
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u8 reserved3[2];
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u8 length_hi;
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__le32 length_lo;
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struct regpair pbl_addr;
|
|
};
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|
|
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|
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/*
|
|
* First element (16 bytes) of fmr wqe
|
|
*/
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struct roce_sq_fmr_wqe_1st {
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|
struct regpair addr;
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|
__le32 l_key;
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u8 req_type;
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|
u8 flags;
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#define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_COMP_FLG_SHIFT 0
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#define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_RD_FENCE_FLG_SHIFT 1
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#define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_INV_FENCE_FLG_SHIFT 2
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#define ROCE_SQ_FMR_WQE_1ST_SE_FLG_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_1ST_SE_FLG_SHIFT 3
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#define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_INLINE_FLG_SHIFT 4
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#define ROCE_SQ_FMR_WQE_1ST_RESERVED0_MASK 0x7
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#define ROCE_SQ_FMR_WQE_1ST_RESERVED0_SHIFT 5
|
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u8 access_ctrl;
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#define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_REMOTE_READ_SHIFT 0
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#define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_REMOTE_WRITE_SHIFT 1
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#define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_ENABLE_ATOMIC_SHIFT 2
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#define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_MASK 0x1
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#define ROCE_SQ_FMR_WQE_1ST_LOCAL_READ_SHIFT 3
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#define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_MASK 0x1
|
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#define ROCE_SQ_FMR_WQE_1ST_LOCAL_WRITE_SHIFT 4
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#define ROCE_SQ_FMR_WQE_1ST_RESERVED1_MASK 0x7
|
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#define ROCE_SQ_FMR_WQE_1ST_RESERVED1_SHIFT 5
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u8 prev_wqe_size;
|
|
};
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|
|
|
|
|
/*
|
|
* Second element (16 bytes) of fmr wqe
|
|
*/
|
|
struct roce_sq_fmr_wqe_2nd {
|
|
u8 fmr_ctrl;
|
|
#define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_MASK 0x1F
|
|
#define ROCE_SQ_FMR_WQE_2ND_PAGE_SIZE_LOG_SHIFT 0
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#define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_MASK 0x1
|
|
#define ROCE_SQ_FMR_WQE_2ND_ZERO_BASED_SHIFT 5
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|
#define ROCE_SQ_FMR_WQE_2ND_BIND_EN_MASK 0x1
|
|
#define ROCE_SQ_FMR_WQE_2ND_BIND_EN_SHIFT 6
|
|
#define ROCE_SQ_FMR_WQE_2ND_RESERVED2_MASK 0x1
|
|
#define ROCE_SQ_FMR_WQE_2ND_RESERVED2_SHIFT 7
|
|
u8 reserved3[2];
|
|
u8 length_hi;
|
|
__le32 length_lo;
|
|
struct regpair pbl_addr;
|
|
};
|
|
|
|
|
|
struct roce_sq_local_inv_wqe {
|
|
struct regpair reserved;
|
|
__le32 inv_l_key;
|
|
u8 req_type;
|
|
u8 flags;
|
|
#define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_MASK 0x1
|
|
#define ROCE_SQ_LOCAL_INV_WQE_COMP_FLG_SHIFT 0
|
|
#define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_LOCAL_INV_WQE_RD_FENCE_FLG_SHIFT 1
|
|
#define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_LOCAL_INV_WQE_INV_FENCE_FLG_SHIFT 2
|
|
#define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_MASK 0x1
|
|
#define ROCE_SQ_LOCAL_INV_WQE_SE_FLG_SHIFT 3
|
|
#define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_MASK 0x1
|
|
#define ROCE_SQ_LOCAL_INV_WQE_INLINE_FLG_SHIFT 4
|
|
#define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_MASK 0x7
|
|
#define ROCE_SQ_LOCAL_INV_WQE_RESERVED0_SHIFT 5
|
|
u8 reserved1;
|
|
u8 prev_wqe_size;
|
|
};
|
|
|
|
|
|
struct roce_sq_rdma_wqe {
|
|
__le32 imm_data;
|
|
__le32 length;
|
|
__le32 xrc_srq;
|
|
u8 req_type;
|
|
u8 flags;
|
|
#define ROCE_SQ_RDMA_WQE_COMP_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_COMP_FLG_SHIFT 0
|
|
#define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_RD_FENCE_FLG_SHIFT 1
|
|
#define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_INV_FENCE_FLG_SHIFT 2
|
|
#define ROCE_SQ_RDMA_WQE_SE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_SE_FLG_SHIFT 3
|
|
#define ROCE_SQ_RDMA_WQE_INLINE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_INLINE_FLG_SHIFT 4
|
|
#define ROCE_SQ_RDMA_WQE_RESERVED0_MASK 0x7
|
|
#define ROCE_SQ_RDMA_WQE_RESERVED0_SHIFT 5
|
|
u8 wqe_size;
|
|
u8 prev_wqe_size;
|
|
struct regpair remote_va;
|
|
__le32 r_key;
|
|
__le32 reserved1;
|
|
};
|
|
|
|
|
|
/*
|
|
* First element (16 bytes) of rdma wqe
|
|
*/
|
|
struct roce_sq_rdma_wqe_1st {
|
|
__le32 imm_data;
|
|
__le32 length;
|
|
__le32 xrc_srq;
|
|
u8 req_type;
|
|
u8 flags;
|
|
#define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_1ST_COMP_FLG_SHIFT 0
|
|
#define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_1ST_RD_FENCE_FLG_SHIFT 1
|
|
#define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_1ST_INV_FENCE_FLG_SHIFT 2
|
|
#define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_1ST_SE_FLG_SHIFT 3
|
|
#define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_MASK 0x1
|
|
#define ROCE_SQ_RDMA_WQE_1ST_INLINE_FLG_SHIFT 4
|
|
#define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_MASK 0x7
|
|
#define ROCE_SQ_RDMA_WQE_1ST_RESERVED0_SHIFT 5
|
|
u8 wqe_size;
|
|
u8 prev_wqe_size;
|
|
};
|
|
|
|
|
|
/*
|
|
* Second element (16 bytes) of rdma wqe
|
|
*/
|
|
struct roce_sq_rdma_wqe_2nd {
|
|
struct regpair remote_va;
|
|
__le32 r_key;
|
|
__le32 reserved1;
|
|
};
|
|
|
|
|
|
/*
|
|
* SQ WQE req type enumeration
|
|
*/
|
|
enum roce_sq_req_type {
|
|
ROCE_SQ_REQ_TYPE_SEND,
|
|
ROCE_SQ_REQ_TYPE_SEND_WITH_IMM,
|
|
ROCE_SQ_REQ_TYPE_SEND_WITH_INVALIDATE,
|
|
ROCE_SQ_REQ_TYPE_RDMA_WR,
|
|
ROCE_SQ_REQ_TYPE_RDMA_WR_WITH_IMM,
|
|
ROCE_SQ_REQ_TYPE_RDMA_RD,
|
|
ROCE_SQ_REQ_TYPE_ATOMIC_CMP_AND_SWAP,
|
|
ROCE_SQ_REQ_TYPE_ATOMIC_ADD,
|
|
ROCE_SQ_REQ_TYPE_LOCAL_INVALIDATE,
|
|
ROCE_SQ_REQ_TYPE_FAST_MR,
|
|
ROCE_SQ_REQ_TYPE_BIND,
|
|
ROCE_SQ_REQ_TYPE_INVALID,
|
|
MAX_ROCE_SQ_REQ_TYPE
|
|
};
|
|
|
|
|
|
struct roce_sq_send_wqe {
|
|
__le32 inv_key_or_imm_data;
|
|
__le32 length;
|
|
__le32 xrc_srq;
|
|
u8 req_type;
|
|
u8 flags;
|
|
#define ROCE_SQ_SEND_WQE_COMP_FLG_MASK 0x1
|
|
#define ROCE_SQ_SEND_WQE_COMP_FLG_SHIFT 0
|
|
#define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_SEND_WQE_RD_FENCE_FLG_SHIFT 1
|
|
#define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_MASK 0x1
|
|
#define ROCE_SQ_SEND_WQE_INV_FENCE_FLG_SHIFT 2
|
|
#define ROCE_SQ_SEND_WQE_SE_FLG_MASK 0x1
|
|
#define ROCE_SQ_SEND_WQE_SE_FLG_SHIFT 3
|
|
#define ROCE_SQ_SEND_WQE_INLINE_FLG_MASK 0x1
|
|
#define ROCE_SQ_SEND_WQE_INLINE_FLG_SHIFT 4
|
|
#define ROCE_SQ_SEND_WQE_RESERVED0_MASK 0x7
|
|
#define ROCE_SQ_SEND_WQE_RESERVED0_SHIFT 5
|
|
u8 wqe_size;
|
|
u8 prev_wqe_size;
|
|
};
|
|
|
|
|
|
struct roce_sq_sge {
|
|
__le32 length;
|
|
struct regpair addr;
|
|
__le32 l_key;
|
|
};
|
|
|
|
|
|
struct roce_srq_prod {
|
|
__le16 prod;
|
|
};
|
|
|
|
|
|
struct roce_srq_sge {
|
|
struct regpair addr;
|
|
__le32 length;
|
|
__le32 l_key;
|
|
struct regpair wr_id;
|
|
u8 flags;
|
|
#define ROCE_SRQ_SGE_NUM_SGES_MASK 0x3
|
|
#define ROCE_SRQ_SGE_NUM_SGES_SHIFT 0
|
|
#define ROCE_SRQ_SGE_RESERVED0_MASK 0x3F
|
|
#define ROCE_SRQ_SGE_RESERVED0_SHIFT 2
|
|
u8 reserved1;
|
|
__le16 reserved2;
|
|
__le32 reserved3;
|
|
};
|
|
|
|
|
|
/*
|
|
* RoCE doorbell data for SQ and RQ
|
|
*/
|
|
struct roce_pwm_val16_data {
|
|
__le16 icid;
|
|
__le16 prod_val;
|
|
};
|
|
|
|
|
|
union roce_pwm_val16_data_union {
|
|
struct roce_pwm_val16_data as_struct;
|
|
__le32 as_dword;
|
|
};
|
|
|
|
|
|
/*
|
|
* RoCE doorbell data for CQ
|
|
*/
|
|
struct roce_pwm_val32_data {
|
|
__le16 icid;
|
|
u8 agg_flags;
|
|
u8 params;
|
|
#define ROCE_PWM_VAL32_DATA_AGG_CMD_MASK 0x3
|
|
#define ROCE_PWM_VAL32_DATA_AGG_CMD_SHIFT 0
|
|
#define ROCE_PWM_VAL32_DATA_BYPASS_EN_MASK 0x1
|
|
#define ROCE_PWM_VAL32_DATA_BYPASS_EN_SHIFT 2
|
|
#define ROCE_PWM_VAL32_DATA_RESERVED_MASK 0x1F
|
|
#define ROCE_PWM_VAL32_DATA_RESERVED_SHIFT 3
|
|
__le32 cq_cons_val;
|
|
};
|
|
|
|
|
|
union roce_pwm_val32_data_union {
|
|
struct roce_pwm_val32_data as_struct;
|
|
struct regpair as_repair;
|
|
};
|
|
|
|
#endif /* __QLNXR_ROCE_H__ */
|