a9ca1c79c6
Add support for two new devices: X552 SFP+ 10 GbE, and the single port version of X550T. Submitted by: erj Reviewed by: gnn Sponsored by: Intel Corporation Differential Revision: https://reviews.freebsd.org/D4186
212 lines
8.6 KiB
C
212 lines
8.6 KiB
C
/******************************************************************************
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Copyright (c) 2001-2015, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#ifndef _IXGBE_PHY_H_
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#define _IXGBE_PHY_H_
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#include "ixgbe_type.h"
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#define IXGBE_I2C_EEPROM_DEV_ADDR 0xA0
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#define IXGBE_I2C_EEPROM_DEV_ADDR2 0xA2
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#define IXGBE_I2C_EEPROM_BANK_LEN 0xFF
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/* EEPROM byte offsets */
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#define IXGBE_SFF_IDENTIFIER 0x0
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#define IXGBE_SFF_IDENTIFIER_SFP 0x3
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#define IXGBE_SFF_VENDOR_OUI_BYTE0 0x25
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#define IXGBE_SFF_VENDOR_OUI_BYTE1 0x26
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#define IXGBE_SFF_VENDOR_OUI_BYTE2 0x27
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#define IXGBE_SFF_1GBE_COMP_CODES 0x6
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#define IXGBE_SFF_10GBE_COMP_CODES 0x3
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#define IXGBE_SFF_CABLE_TECHNOLOGY 0x8
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#define IXGBE_SFF_CABLE_SPEC_COMP 0x3C
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#define IXGBE_SFF_SFF_8472_SWAP 0x5C
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#define IXGBE_SFF_SFF_8472_COMP 0x5E
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#define IXGBE_SFF_SFF_8472_OSCB 0x6E
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#define IXGBE_SFF_SFF_8472_ESCB 0x76
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#define IXGBE_SFF_IDENTIFIER_QSFP_PLUS 0xD
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#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0 0xA5
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#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1 0xA6
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#define IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2 0xA7
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#define IXGBE_SFF_QSFP_CONNECTOR 0x82
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#define IXGBE_SFF_QSFP_10GBE_COMP 0x83
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#define IXGBE_SFF_QSFP_1GBE_COMP 0x86
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#define IXGBE_SFF_QSFP_CABLE_LENGTH 0x92
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#define IXGBE_SFF_QSFP_DEVICE_TECH 0x93
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/* Bitmasks */
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#define IXGBE_SFF_DA_PASSIVE_CABLE 0x4
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#define IXGBE_SFF_DA_ACTIVE_CABLE 0x8
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#define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING 0x4
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#define IXGBE_SFF_1GBASESX_CAPABLE 0x1
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#define IXGBE_SFF_1GBASELX_CAPABLE 0x2
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#define IXGBE_SFF_1GBASET_CAPABLE 0x8
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#define IXGBE_SFF_10GBASESR_CAPABLE 0x10
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#define IXGBE_SFF_10GBASELR_CAPABLE 0x20
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#define IXGBE_SFF_SOFT_RS_SELECT_MASK 0x8
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#define IXGBE_SFF_SOFT_RS_SELECT_10G 0x8
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#define IXGBE_SFF_SOFT_RS_SELECT_1G 0x0
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#define IXGBE_SFF_ADDRESSING_MODE 0x4
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#define IXGBE_SFF_QSFP_DA_ACTIVE_CABLE 0x1
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#define IXGBE_SFF_QSFP_DA_PASSIVE_CABLE 0x8
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#define IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE 0x23
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#define IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL 0x0
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#define IXGBE_I2C_EEPROM_READ_MASK 0x100
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#define IXGBE_I2C_EEPROM_STATUS_MASK 0x3
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#define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION 0x0
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#define IXGBE_I2C_EEPROM_STATUS_PASS 0x1
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#define IXGBE_I2C_EEPROM_STATUS_FAIL 0x2
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#define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS 0x3
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#define IXGBE_CS4227 0xBE /* CS4227 address */
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#define IXGBE_CS4227_GLOBAL_ID_LSB 0
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#define IXGBE_CS4227_SCRATCH 2
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#define IXGBE_CS4227_GLOBAL_ID_VALUE 0x03E5
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#define IXGBE_CS4227_RESET_PENDING 0x1357
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#define IXGBE_CS4227_RESET_COMPLETE 0x5AA5
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#define IXGBE_CS4227_RETRIES 15
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#define IXGBE_CS4227_EFUSE_STATUS 0x0181
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#define IXGBE_CS4227_LINE_SPARE22_MSB 0x12AD /* Reg to program speed */
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#define IXGBE_CS4227_LINE_SPARE24_LSB 0x12B0 /* Reg to program EDC */
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#define IXGBE_CS4227_HOST_SPARE22_MSB 0x1AAD /* Reg to program speed */
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#define IXGBE_CS4227_HOST_SPARE24_LSB 0x1AB0 /* Reg to program EDC */
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#define IXGBE_CS4227_EEPROM_STATUS 0x5001
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#define IXGBE_CS4227_EEPROM_LOAD_OK 0x0001
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#define IXGBE_CS4227_SPEED_1G 0x8000
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#define IXGBE_CS4227_SPEED_10G 0
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#define IXGBE_CS4227_EDC_MODE_CX1 0x0002
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#define IXGBE_CS4227_EDC_MODE_SR 0x0004
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#define IXGBE_CS4227_EDC_MODE_DIAG 0x0008
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#define IXGBE_CS4227_RESET_HOLD 500 /* microseconds */
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#define IXGBE_CS4227_RESET_DELAY 450 /* milliseconds */
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#define IXGBE_CS4227_CHECK_DELAY 30 /* milliseconds */
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#define IXGBE_PE 0xE0 /* Port expander address */
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#define IXGBE_PE_OUTPUT 1 /* Output register offset */
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#define IXGBE_PE_CONFIG 3 /* Config register offset */
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#define IXGBE_PE_BIT1 (1 << 1)
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/* Flow control defines */
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#define IXGBE_TAF_SYM_PAUSE 0x400
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#define IXGBE_TAF_ASM_PAUSE 0x800
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/* Bit-shift macros */
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#define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT 24
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#define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT 16
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#define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT 8
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/* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
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#define IXGBE_SFF_VENDOR_OUI_TYCO 0x00407600
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#define IXGBE_SFF_VENDOR_OUI_FTL 0x00906500
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#define IXGBE_SFF_VENDOR_OUI_AVAGO 0x00176A00
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#define IXGBE_SFF_VENDOR_OUI_INTEL 0x001B2100
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/* I2C SDA and SCL timing parameters for standard mode */
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#define IXGBE_I2C_T_HD_STA 4
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#define IXGBE_I2C_T_LOW 5
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#define IXGBE_I2C_T_HIGH 4
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#define IXGBE_I2C_T_SU_STA 5
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#define IXGBE_I2C_T_HD_DATA 5
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#define IXGBE_I2C_T_SU_DATA 1
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#define IXGBE_I2C_T_RISE 1
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#define IXGBE_I2C_T_FALL 1
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#define IXGBE_I2C_T_SU_STO 4
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#define IXGBE_I2C_T_BUF 5
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#ifndef IXGBE_SFP_DETECT_RETRIES
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#define IXGBE_SFP_DETECT_RETRIES 10
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#endif /* IXGBE_SFP_DETECT_RETRIES */
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#define IXGBE_TN_LASI_STATUS_REG 0x9005
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#define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
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/* SFP+ SFF-8472 Compliance */
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#define IXGBE_SFF_SFF_8472_UNSUP 0x00
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s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
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bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
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enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
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s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
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s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
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s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
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s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 *phy_data);
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s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
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u16 phy_data);
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s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 *phy_data);
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s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
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u32 device_type, u16 phy_data);
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s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
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s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
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ixgbe_link_speed speed,
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bool autoneg_wait_to_complete);
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s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *autoneg);
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s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw);
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/* PHY specific */
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s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
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ixgbe_link_speed *speed,
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bool *link_up);
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s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
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s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
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u16 *firmware_version);
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s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
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u16 *firmware_version);
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s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
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s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on);
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s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
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s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
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s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw);
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s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
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s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
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u16 *list_offset,
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u16 *data_offset);
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s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
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s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data);
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s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 *data);
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s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data);
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s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
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u8 dev_addr, u8 data);
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s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 *eeprom_data);
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s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
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u8 eeprom_data);
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void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
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#endif /* _IXGBE_PHY_H_ */
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