624 lines
15 KiB
C
624 lines
15 KiB
C
/*-
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* Copyright (c) 2000 Matthew C. Forman
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*
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* Based (heavily) on alpm.c which is:
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*
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* Copyright (c) 1998, 1999 Nicolas Souchu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Power management function/SMBus function support for the AMD 756 chip.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/kernel.h>
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#include <sys/systm.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <sys/uio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/smbus/smbconf.h>
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#include "smbus_if.h"
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#define AMDPM_DEBUG(x) if (amdpm_debug) (x)
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#ifdef DEBUG
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static int amdpm_debug = 1;
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#else
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static int amdpm_debug = 0;
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#endif
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#define AMDPM_VENDORID_AMD 0x1022
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#define AMDPM_DEVICEID_AMD756PM 0x740b
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#define AMDPM_DEVICEID_AMD766PM 0x7413
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#define AMDPM_DEVICEID_AMD768PM 0x7443
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#define AMDPM_DEVICEID_AMD8111PM 0x746B
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/* nVidia nForce chipset */
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#define AMDPM_VENDORID_NVIDIA 0x10de
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#define AMDPM_DEVICEID_NF_SMB 0x01b4
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/* PCI Configuration space registers */
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#define AMDPCI_PMBASE 0x58
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#define NFPCI_PMBASE 0x14
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#define AMDPCI_GEN_CONFIG_PM 0x41
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#define AMDPCI_PMIOEN (1<<7)
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#define AMDPCI_SCIINT_CONFIG_PM 0x42
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#define AMDPCI_SCISEL_IRQ11 11
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#define AMDPCI_REVID 0x08
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/*
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* I/O registers.
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* Base address programmed via AMDPCI_PMBASE.
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*/
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#define AMDSMB_GLOBAL_STATUS (0x00)
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#define AMDSMB_GS_TO_STS (1<<5)
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#define AMDSMB_GS_HCYC_STS (1<<4)
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#define AMDSMB_GS_HST_STS (1<<3)
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#define AMDSMB_GS_PRERR_STS (1<<2)
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#define AMDSMB_GS_COL_STS (1<<1)
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#define AMDSMB_GS_ABRT_STS (1<<0)
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#define AMDSMB_GS_CLEAR_STS (AMDSMB_GS_TO_STS|AMDSMB_GS_HCYC_STS|AMDSMB_GS_PRERR_STS|AMDSMB_GS_COL_STS|AMDSMB_GS_ABRT_STS)
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#define AMDSMB_GLOBAL_ENABLE (0x02)
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#define AMDSMB_GE_ABORT (1<<5)
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#define AMDSMB_GE_HCYC_EN (1<<4)
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#define AMDSMB_GE_HOST_STC (1<<3)
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#define AMDSMB_GE_CYC_QUICK 0
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#define AMDSMB_GE_CYC_BYTE 1
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#define AMDSMB_GE_CYC_BDATA 2
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#define AMDSMB_GE_CYC_WDATA 3
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#define AMDSMB_GE_CYC_PROCCALL 4
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#define AMDSMB_GE_CYC_BLOCK 5
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#define AMDSMB_HSTADDR (0x04)
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#define AMDSMB_HSTDATA (0x06)
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#define AMDSMB_HSTCMD (0x08)
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#define AMDSMB_HSTDFIFO (0x09)
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#define AMDSMB_HSLVDATA (0x0A)
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#define AMDSMB_HSLVDA (0x0C)
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#define AMDSMB_HSLVDDR (0x0E)
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#define AMDSMB_SNPADDR (0x0F)
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struct amdpm_softc {
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int base;
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int rid;
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struct resource *res;
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bus_space_tag_t smbst;
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bus_space_handle_t smbsh;
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device_t smbus;
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};
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#define AMDPM_SMBINB(amdpm,register) \
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(bus_space_read_1(amdpm->smbst, amdpm->smbsh, register))
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#define AMDPM_SMBOUTB(amdpm,register,value) \
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(bus_space_write_1(amdpm->smbst, amdpm->smbsh, register, value))
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#define AMDPM_SMBINW(amdpm,register) \
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(bus_space_read_2(amdpm->smbst, amdpm->smbsh, register))
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#define AMDPM_SMBOUTW(amdpm,register,value) \
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(bus_space_write_2(amdpm->smbst, amdpm->smbsh, register, value))
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static int
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amdpm_probe(device_t dev)
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{
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u_long base;
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u_int16_t vid;
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u_int16_t did;
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vid = pci_get_vendor(dev);
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did = pci_get_device(dev);
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if ((vid == AMDPM_VENDORID_AMD) &&
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((did == AMDPM_DEVICEID_AMD756PM) ||
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(did == AMDPM_DEVICEID_AMD766PM) ||
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(did == AMDPM_DEVICEID_AMD768PM) ||
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(did == AMDPM_DEVICEID_AMD8111PM))) {
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device_set_desc(dev, "AMD 756/766/768/8111 Power Management Controller");
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/*
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* We have to do this, since the BIOS won't give us the
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* resource info (not mine, anyway).
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*/
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base = pci_read_config(dev, AMDPCI_PMBASE, 4);
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base &= 0xff00;
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bus_set_resource(dev, SYS_RES_IOPORT, AMDPCI_PMBASE,
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base+0xe0, 32);
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return (BUS_PROBE_DEFAULT);
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}
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if ((vid == AMDPM_VENDORID_NVIDIA) &&
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(did == AMDPM_DEVICEID_NF_SMB)) {
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device_set_desc(dev, "nForce SMBus Controller");
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/*
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* We have to do this, since the BIOS won't give us the
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* resource info (not mine, anyway).
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*/
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base = pci_read_config(dev, NFPCI_PMBASE, 4);
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base &= 0xff00;
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bus_set_resource(dev, SYS_RES_IOPORT, NFPCI_PMBASE,
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base, 32);
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return (BUS_PROBE_DEFAULT);
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}
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return ENXIO;
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}
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static int
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amdpm_attach(device_t dev)
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{
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struct amdpm_softc *amdpm_sc = device_get_softc(dev);
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u_char val_b;
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/* Enable I/O block access */
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val_b = pci_read_config(dev, AMDPCI_GEN_CONFIG_PM, 1);
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pci_write_config(dev, AMDPCI_GEN_CONFIG_PM, val_b | AMDPCI_PMIOEN, 1);
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/* Allocate I/O space */
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if (pci_get_vendor(dev) == AMDPM_VENDORID_AMD)
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amdpm_sc->rid = AMDPCI_PMBASE;
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else
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amdpm_sc->rid = NFPCI_PMBASE;
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amdpm_sc->res = bus_alloc_resource_any(dev, SYS_RES_IOPORT,
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&amdpm_sc->rid, RF_ACTIVE);
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if (amdpm_sc->res == NULL) {
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device_printf(dev, "could not map i/o space\n");
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return (ENXIO);
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}
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amdpm_sc->smbst = rman_get_bustag(amdpm_sc->res);
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amdpm_sc->smbsh = rman_get_bushandle(amdpm_sc->res);
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/* Allocate a new smbus device */
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amdpm_sc->smbus = device_add_child(dev, "smbus", -1);
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if (!amdpm_sc->smbus)
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return (EINVAL);
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bus_generic_attach(dev);
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return (0);
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}
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static int
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amdpm_detach(device_t dev)
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{
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struct amdpm_softc *amdpm_sc = device_get_softc(dev);
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if (amdpm_sc->smbus) {
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device_delete_child(dev, amdpm_sc->smbus);
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amdpm_sc->smbus = NULL;
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}
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if (amdpm_sc->res)
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bus_release_resource(dev, SYS_RES_IOPORT, amdpm_sc->rid,
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amdpm_sc->res);
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return (0);
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}
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static int
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amdpm_callback(device_t dev, int index, caddr_t *data)
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{
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int error = 0;
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switch (index) {
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case SMB_REQUEST_BUS:
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case SMB_RELEASE_BUS:
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break;
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default:
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error = EINVAL;
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}
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return (error);
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}
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static int
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amdpm_clear(struct amdpm_softc *sc)
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{
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_STATUS, AMDSMB_GS_CLEAR_STS);
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DELAY(10);
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return (0);
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}
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#if 0
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static int
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amdpm_abort(struct amdpm_softc *sc)
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{
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u_short l;
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, l | AMDSMB_GE_ABORT);
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return (0);
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}
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#endif
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static int
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amdpm_idle(struct amdpm_softc *sc)
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{
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u_short sts;
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sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
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AMDPM_DEBUG(printf("amdpm: busy? STS=0x%x\n", sts));
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return (~(sts & AMDSMB_GS_HST_STS));
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}
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/*
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* Poll the SMBus controller
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*/
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static int
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amdpm_wait(struct amdpm_softc *sc)
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{
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int count = 10000;
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u_short sts = 0;
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int error;
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/* Wait for command to complete (SMBus controller is idle) */
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while(count--) {
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DELAY(10);
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sts = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_STATUS);
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if (!(sts & AMDSMB_GS_HST_STS))
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break;
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}
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AMDPM_DEBUG(printf("amdpm: STS=0x%x (count=%d)\n", sts, count));
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error = SMB_ENOERR;
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if (!count)
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error |= SMB_ETIMEOUT;
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if (sts & AMDSMB_GS_ABRT_STS)
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error |= SMB_EABORT;
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if (sts & AMDSMB_GS_COL_STS)
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error |= SMB_ENOACK;
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if (sts & AMDSMB_GS_PRERR_STS)
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error |= SMB_EBUSERR;
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if (error != SMB_ENOERR)
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amdpm_clear(sc);
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return (error);
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}
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static int
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amdpm_quick(device_t dev, u_char slave, int how)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
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int error;
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u_short l;
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amdpm_clear(sc);
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if (!amdpm_idle(sc))
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return (EBUSY);
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switch (how) {
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case SMB_QWRITE:
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AMDPM_DEBUG(printf("amdpm: QWRITE to 0x%x", slave));
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
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break;
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case SMB_QREAD:
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AMDPM_DEBUG(printf("amdpm: QREAD to 0x%x", slave));
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
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break;
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default:
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panic("%s: unknown QUICK command (%x)!", __func__, how);
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}
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_QUICK | AMDSMB_GE_HOST_STC);
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error = amdpm_wait(sc);
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AMDPM_DEBUG(printf(", error=0x%x\n", error));
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return (error);
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}
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static int
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amdpm_sendb(device_t dev, u_char slave, char byte)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
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int error;
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u_short l;
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amdpm_clear(sc);
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if (!amdpm_idle(sc))
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return (SMB_EBUSY);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
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error = amdpm_wait(sc);
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AMDPM_DEBUG(printf("amdpm: SENDB to 0x%x, byte=0x%x, error=0x%x\n", slave, byte, error));
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return (error);
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}
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static int
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amdpm_recvb(device_t dev, u_char slave, char *byte)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
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int error;
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u_short l;
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amdpm_clear(sc);
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if (!amdpm_idle(sc))
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return (SMB_EBUSY);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BYTE | AMDSMB_GE_HOST_STC);
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if ((error = amdpm_wait(sc)) == SMB_ENOERR)
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*byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
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AMDPM_DEBUG(printf("amdpm: RECVB from 0x%x, byte=0x%x, error=0x%x\n", slave, *byte, error));
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return (error);
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}
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static int
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amdpm_writeb(device_t dev, u_char slave, char cmd, char byte)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
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int error;
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u_short l;
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amdpm_clear(sc);
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if (!amdpm_idle(sc))
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return (SMB_EBUSY);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, byte);
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AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
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error = amdpm_wait(sc);
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AMDPM_DEBUG(printf("amdpm: WRITEB to 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, byte, error));
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return (error);
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}
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static int
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amdpm_readb(device_t dev, u_char slave, char cmd, char *byte)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
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int error;
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u_short l;
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amdpm_clear(sc);
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if (!amdpm_idle(sc))
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return (SMB_EBUSY);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
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AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BDATA | AMDSMB_GE_HOST_STC);
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if ((error = amdpm_wait(sc)) == SMB_ENOERR)
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*byte = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
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AMDPM_DEBUG(printf("amdpm: READB from 0x%x, cmd=0x%x, byte=0x%x, error=0x%x\n", slave, cmd, *byte, error));
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return (error);
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}
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static int
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amdpm_writew(device_t dev, u_char slave, char cmd, short word)
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{
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struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
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int error;
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u_short l;
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amdpm_clear(sc);
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if (!amdpm_idle(sc))
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return (SMB_EBUSY);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
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AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, word);
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AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
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l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
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AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
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error = amdpm_wait(sc);
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AMDPM_DEBUG(printf("amdpm: WRITEW to 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, word, error));
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return (error);
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}
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static int
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amdpm_readw(device_t dev, u_char slave, char cmd, short *word)
|
|
{
|
|
struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
|
|
int error;
|
|
u_short l;
|
|
|
|
amdpm_clear(sc);
|
|
if (!amdpm_idle(sc))
|
|
return (SMB_EBUSY);
|
|
|
|
AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
|
|
AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
|
|
l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
|
|
AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_WDATA | AMDSMB_GE_HOST_STC);
|
|
|
|
if ((error = amdpm_wait(sc)) == SMB_ENOERR)
|
|
*word = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
|
|
|
|
AMDPM_DEBUG(printf("amdpm: READW from 0x%x, cmd=0x%x, word=0x%x, error=0x%x\n", slave, cmd, *word, error));
|
|
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
amdpm_bwrite(device_t dev, u_char slave, char cmd, u_char count, char *buf)
|
|
{
|
|
struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
|
|
u_char remain, len, i;
|
|
int error = SMB_ENOERR;
|
|
u_short l;
|
|
|
|
amdpm_clear(sc);
|
|
if(!amdpm_idle(sc))
|
|
return (SMB_EBUSY);
|
|
|
|
remain = count;
|
|
while (remain) {
|
|
len = min(remain, 32);
|
|
|
|
AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave & ~LSB);
|
|
|
|
/*
|
|
* Do we have to reset the internal 32-byte buffer?
|
|
* Can't see how to do this from the data sheet.
|
|
*/
|
|
|
|
AMDPM_SMBOUTW(sc, AMDSMB_HSTDATA, len);
|
|
|
|
/* Fill the 32-byte internal buffer */
|
|
for (i=0; i<len; i++) {
|
|
AMDPM_SMBOUTB(sc, AMDSMB_HSTDFIFO, buf[count-remain+i]);
|
|
DELAY(2);
|
|
}
|
|
AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
|
|
l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
|
|
AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
|
|
|
|
if ((error = amdpm_wait(sc)) != SMB_ENOERR)
|
|
goto error;
|
|
|
|
remain -= len;
|
|
}
|
|
|
|
error:
|
|
AMDPM_DEBUG(printf("amdpm: WRITEBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
|
|
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
amdpm_bread(device_t dev, u_char slave, char cmd, u_char count, char *buf)
|
|
{
|
|
struct amdpm_softc *sc = (struct amdpm_softc *)device_get_softc(dev);
|
|
u_char remain, len, i;
|
|
int error = SMB_ENOERR;
|
|
u_short l;
|
|
|
|
amdpm_clear(sc);
|
|
if (!amdpm_idle(sc))
|
|
return (SMB_EBUSY);
|
|
|
|
remain = count;
|
|
while (remain) {
|
|
AMDPM_SMBOUTW(sc, AMDSMB_HSTADDR, slave | LSB);
|
|
|
|
AMDPM_SMBOUTB(sc, AMDSMB_HSTCMD, cmd);
|
|
|
|
l = AMDPM_SMBINW(sc, AMDSMB_GLOBAL_ENABLE);
|
|
AMDPM_SMBOUTW(sc, AMDSMB_GLOBAL_ENABLE, (l & 0xfff8) | AMDSMB_GE_CYC_BLOCK | AMDSMB_GE_HOST_STC);
|
|
|
|
if ((error = amdpm_wait(sc)) != SMB_ENOERR)
|
|
goto error;
|
|
|
|
len = AMDPM_SMBINW(sc, AMDSMB_HSTDATA);
|
|
|
|
/* Read the 32-byte internal buffer */
|
|
for (i=0; i<len; i++) {
|
|
buf[count-remain+i] = AMDPM_SMBINB(sc, AMDSMB_HSTDFIFO);
|
|
DELAY(2);
|
|
}
|
|
|
|
remain -= len;
|
|
}
|
|
error:
|
|
AMDPM_DEBUG(printf("amdpm: READBLK to 0x%x, count=0x%x, cmd=0x%x, error=0x%x", slave, count, cmd, error));
|
|
|
|
return (error);
|
|
}
|
|
|
|
static devclass_t amdpm_devclass;
|
|
|
|
static device_method_t amdpm_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, amdpm_probe),
|
|
DEVMETHOD(device_attach, amdpm_attach),
|
|
DEVMETHOD(device_detach, amdpm_detach),
|
|
|
|
/* SMBus interface */
|
|
DEVMETHOD(smbus_callback, amdpm_callback),
|
|
DEVMETHOD(smbus_quick, amdpm_quick),
|
|
DEVMETHOD(smbus_sendb, amdpm_sendb),
|
|
DEVMETHOD(smbus_recvb, amdpm_recvb),
|
|
DEVMETHOD(smbus_writeb, amdpm_writeb),
|
|
DEVMETHOD(smbus_readb, amdpm_readb),
|
|
DEVMETHOD(smbus_writew, amdpm_writew),
|
|
DEVMETHOD(smbus_readw, amdpm_readw),
|
|
DEVMETHOD(smbus_bwrite, amdpm_bwrite),
|
|
DEVMETHOD(smbus_bread, amdpm_bread),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t amdpm_driver = {
|
|
"amdpm",
|
|
amdpm_methods,
|
|
sizeof(struct amdpm_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(amdpm, pci, amdpm_driver, amdpm_devclass, 0, 0);
|
|
|
|
MODULE_DEPEND(amdpm, pci, 1, 1, 1);
|
|
MODULE_DEPEND(amdpm, smbus, SMBUS_MINVER, SMBUS_PREFVER, SMBUS_MAXVER);
|
|
MODULE_VERSION(amdpm, 1);
|
|
|