1537078d8f
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
1818 lines
42 KiB
C
1818 lines
42 KiB
C
/* $NecBSD: nsp.c,v 1.21.12.6 2001/06/29 06:27:52 honda Exp $ */
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/* $NetBSD$ */
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#define NSP_DEBUG
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#define NSP_STATICS
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#define NSP_IO_CONTROL_FLAGS \
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(NSP_READ_SUSPEND_IO | NSP_WRITE_SUSPEND_IO | \
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NSP_READ_FIFO_INTERRUPTS | NSP_WRITE_FIFO_INTERRUPTS | \
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NSP_USE_MEMIO | NSP_WAIT_FOR_SELECT)
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/*-
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* SPDX-License-Identifier: BSD-3-Clause
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*
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* Copyright (c) 1998, 1999, 2000, 2001
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* NetBSD/pc98 porting staff. All rights reserved.
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*
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* Copyright (c) 1998, 1999, 2000, 2001
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* Naofumi HONDA. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/bio.h>
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#include <sys/buf.h>
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#include <sys/queue.h>
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#include <sys/malloc.h>
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#include <sys/errno.h>
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#include <sys/rman.h>
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#include <machine/cpu.h>
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#include <machine/bus.h>
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#include <cam/scsi/scsi_low.h>
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#include <dev/nsp/nspreg.h>
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#include <dev/nsp/nspvar.h>
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/***************************************************
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* USER SETTINGS
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***************************************************/
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/* DEVICE CONFIGURATION FLAGS (MINOR)
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*
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* 0x01 DISCONNECT OFF
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* 0x02 PARITY LINE OFF
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* 0x04 IDENTIFY MSG OFF ( = single lun)
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* 0x08 SYNC TRANSFER OFF
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*/
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/***************************************************
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* PARAMS
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***************************************************/
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#define NSP_NTARGETS 8
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#define NSP_NLUNS 8
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#define NSP_MAX_DATA_SIZE (64 * 1024)
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#define NSP_SELTIMEOUT (200)
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#define NSP_DELAY_MAX (2 * 1000 * 1000)
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#define NSP_DELAY_INTERVAL (1)
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#define NSP_TIMER_1MS (1000 / 51)
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/***************************************************
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* DEBUG
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***************************************************/
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#ifdef NSP_DEBUG
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int nsp_debug;
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#endif /* NSP_DEBUG */
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#ifdef NSP_STATICS
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struct nsp_statics {
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int arbit_conflict_1;
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int arbit_conflict_2;
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int device_data_write;
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int device_busy;
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int disconnect;
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int reselect;
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int data_phase_bypass;
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} nsp_statics;
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#endif /* NSP_STATICS */
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/***************************************************
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* IO control
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***************************************************/
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#define NSP_READ_SUSPEND_IO 0x0001
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#define NSP_WRITE_SUSPEND_IO 0x0002
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#define NSP_USE_MEMIO 0x0004
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#define NSP_READ_FIFO_INTERRUPTS 0x0010
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#define NSP_WRITE_FIFO_INTERRUPTS 0x0020
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#define NSP_WAIT_FOR_SELECT 0x0100
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u_int nsp_io_control = NSP_IO_CONTROL_FLAGS;
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int nsp_read_suspend_bytes = DEV_BSIZE;
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int nsp_write_suspend_bytes = DEV_BSIZE;
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int nsp_read_interrupt_bytes = 4096;
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int nsp_write_interrupt_bytes = 4096;
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/***************************************************
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* DEVICE STRUCTURE
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***************************************************/
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extern struct cfdriver nsp_cd;
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/**************************************************************
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* DECLARE
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**************************************************************/
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#define NSP_FIFO_ON 1
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#define NSP_FIFO_OFF 0
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static void nsp_pio_read(struct nsp_softc *, int);
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static void nsp_pio_write(struct nsp_softc *, int);
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static int nsp_xfer(struct nsp_softc *, u_int8_t *, int, int, int);
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static int nsp_msg(struct nsp_softc *, struct targ_info *, u_int);
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static int nsp_reselected(struct nsp_softc *);
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static int nsp_disconnected(struct nsp_softc *, struct targ_info *);
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static void nsp_pdma_end(struct nsp_softc *, struct targ_info *);
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static void nsphw_init(struct nsp_softc *);
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static int nsp_target_nexus_establish(struct nsp_softc *);
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static int nsp_lun_nexus_establish(struct nsp_softc *);
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static int nsp_ccb_nexus_establish(struct nsp_softc *);
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static int nsp_world_start(struct nsp_softc *, int);
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static int nsphw_start_selection(struct nsp_softc *sc, struct slccb *);
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static void nsphw_bus_reset(struct nsp_softc *);
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static void nsphw_attention(struct nsp_softc *);
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static u_int nsp_fifo_count(struct nsp_softc *);
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static u_int nsp_request_count(struct nsp_softc *);
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static int nsp_negate_signal(struct nsp_softc *, u_int8_t, u_char *);
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static int nsp_expect_signal(struct nsp_softc *, u_int8_t, u_int8_t);
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static void nsp_start_timer(struct nsp_softc *, int);
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static void nsp_setup_fifo(struct nsp_softc *, int, int, int);
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static int nsp_targ_init(struct nsp_softc *, struct targ_info *, int);
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static void nsphw_selection_done_and_expect_msgout(struct nsp_softc *);
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static void nsp_data_padding(struct nsp_softc *, int, u_int);
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static int nsp_timeout(struct nsp_softc *);
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static int nsp_read_fifo(struct nsp_softc *, int);
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static int nsp_write_fifo(struct nsp_softc *, int);
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static int nsp_phase_match(struct nsp_softc *, u_int8_t, u_int8_t);
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static int nsp_wait_interrupt(struct nsp_softc *);
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struct scsi_low_funcs nspfuncs = {
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SC_LOW_INIT_T nsp_world_start,
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SC_LOW_BUSRST_T nsphw_bus_reset,
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SC_LOW_TARG_INIT_T nsp_targ_init,
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SC_LOW_LUN_INIT_T NULL,
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SC_LOW_SELECT_T nsphw_start_selection,
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SC_LOW_NEXUS_T nsp_lun_nexus_establish,
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SC_LOW_NEXUS_T nsp_ccb_nexus_establish,
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SC_LOW_ATTEN_T nsphw_attention,
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SC_LOW_MSG_T nsp_msg,
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SC_LOW_TIMEOUT_T nsp_timeout,
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SC_LOW_POLL_T nspintr,
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NULL,
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};
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/****************************************************
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* hwfuncs
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****************************************************/
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static __inline uint8_t
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nsp_cr_read_1(struct resource *res, bus_addr_t ofs)
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{
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bus_write_1(res, nsp_idxr, ofs);
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return bus_read_1(res, nsp_datar);
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}
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static __inline void
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nsp_cr_write_1(struct resource *res, bus_addr_t ofs, uint8_t va)
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{
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bus_write_1(res, nsp_idxr, ofs);
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bus_write_1(res, nsp_datar, va);
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}
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static int
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nsp_expect_signal(struct nsp_softc *sc, u_int8_t curphase, u_int8_t mask)
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{
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struct scsi_low_softc *slp = &sc->sc_sclow;
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int wc;
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u_int8_t ph, isrc;
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for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++)
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{
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ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
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if (ph == (u_int8_t) -1)
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return -1;
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isrc = bus_read_1(sc->port_res, nsp_irqsr);
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if (isrc & IRQSR_SCSI)
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return 0;
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if ((ph & mask) != 0 && (ph & SCBUSMON_PHMASK) == curphase)
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return 1;
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DELAY(NSP_DELAY_INTERVAL);
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}
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device_printf(slp->sl_dev, "nsp_expect_signal timeout\n");
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return -1;
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}
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static void
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nsphw_init(sc)
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struct nsp_softc *sc;
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{
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/* block all interrupts */
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bus_write_1(sc->port_res, nsp_irqcr, IRQCR_ALLMASK);
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/* setup SCSI interface */
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bus_write_1(sc->port_res, nsp_ifselr, IFSELR_IFSEL);
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nsp_cr_write_1(sc->port_res, NSPR_SCIENR, 0);
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nsp_cr_write_1(sc->port_res, NSPR_XFERMR, XFERMR_IO8);
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nsp_cr_write_1(sc->port_res, NSPR_CLKDIVR, sc->sc_iclkdiv);
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nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr);
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nsp_cr_write_1(sc->port_res, NSPR_PARITYR, sc->sc_parr);
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nsp_cr_write_1(sc->port_res, NSPR_PTCLRR,
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PTCLRR_ACK | PTCLRR_REQ | PTCLRR_HOST | PTCLRR_RSS);
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/* setup fifo asic */
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bus_write_1(sc->port_res, nsp_ifselr, IFSELR_REGSEL);
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nsp_cr_write_1(sc->port_res, NSPR_TERMPWRC, 0);
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if ((nsp_cr_read_1(sc->port_res, NSPR_OCR) & OCR_TERMPWRS) == 0)
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nsp_cr_write_1(sc->port_res, NSPR_TERMPWRC, TERMPWRC_POWON);
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nsp_cr_write_1(sc->port_res, NSPR_XFERMR, XFERMR_IO8);
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nsp_cr_write_1(sc->port_res, NSPR_CLKDIVR, sc->sc_clkdiv);
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nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0);
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nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0);
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nsp_cr_write_1(sc->port_res, NSPR_SYNCR, 0);
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nsp_cr_write_1(sc->port_res, NSPR_ACKWIDTH, 0);
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/* enable interrupts and ack them */
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nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr);
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bus_write_1(sc->port_res, nsp_irqcr, IRQSR_MASK);
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nsp_setup_fifo(sc, NSP_FIFO_OFF, SCSI_LOW_READ, 0);
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}
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/****************************************************
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* scsi low interface
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****************************************************/
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static void
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nsphw_attention(sc)
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struct nsp_softc *sc;
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{
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u_int8_t cr;
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cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR)/* & ~SCBUSCR_ACK */;
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr | SCBUSCR_ATN);
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DELAY(10);
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}
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static void
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nsphw_bus_reset(sc)
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struct nsp_softc *sc;
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{
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int i;
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bus_write_1(sc->port_res, nsp_irqcr, IRQCR_ALLMASK);
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, SCBUSCR_RST);
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DELAY(100 * 1000); /* 100ms */
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 0);
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for (i = 0; i < 5; i ++)
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(void) nsp_cr_read_1(sc->port_res, NSPR_IRQPHS);
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bus_write_1(sc->port_res, nsp_irqcr, IRQSR_MASK);
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}
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static void
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nsphw_selection_done_and_expect_msgout(sc)
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struct nsp_softc *sc;
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{
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struct scsi_low_softc *slp = &sc->sc_sclow;
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/* clear ack counter */
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sc->sc_cnt = 0;
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nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_PT | PTCLRR_ACK |
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PTCLRR_REQ | PTCLRR_HOST);
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/* deassert sel and assert atten */
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sc->sc_seltout = 0;
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, sc->sc_busc);
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DELAY(1);
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR,
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sc->sc_busc | SCBUSCR_ADIR | SCBUSCR_ACKEN);
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SCSI_LOW_ASSERT_ATN(slp);
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}
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static int
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nsphw_start_selection(sc, cb)
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struct nsp_softc *sc;
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struct slccb *cb;
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{
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struct scsi_low_softc *slp = &sc->sc_sclow;
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struct targ_info *ti = cb->ti;
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register u_int8_t arbs, ph;
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int wc;
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wc = sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
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sc->sc_dataout_timeout = 0;
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/* check bus free */
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ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
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if (ph != SCBUSMON_FREE)
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{
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#ifdef NSP_STATICS
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nsp_statics.arbit_conflict_1 ++;
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#endif /* NSP_STATICS */
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return SCSI_LOW_START_FAIL;
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}
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/* start arbitration */
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nsp_cr_write_1(sc->port_res, NSPR_ARBITS, ARBITS_EXEC);
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SCSI_LOW_SETUP_PHASE(ti, PH_ARBSTART);
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do
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{
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/* XXX: what a stupid chip! */
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arbs = nsp_cr_read_1(sc->port_res, NSPR_ARBITS);
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DELAY(1);
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}
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while ((arbs & (ARBITS_WIN | ARBITS_FAIL)) == 0 && wc -- > 0);
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if ((arbs & ARBITS_WIN) == 0)
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{
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nsp_cr_write_1(sc->port_res, NSPR_ARBITS, ARBITS_CLR);
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#ifdef NSP_STATICS
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nsp_statics.arbit_conflict_2 ++;
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#endif /* NSP_STATICS */
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return SCSI_LOW_START_FAIL;
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}
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/* assert select line */
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SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
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scsi_low_arbit_win(slp);
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DELAY(3);
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nsp_cr_write_1(sc->port_res, NSPR_DATA,
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sc->sc_idbit | (1 << ti->ti_id));
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR,
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SCBUSCR_SEL | SCBUSCR_BSY | sc->sc_busc);
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DELAY(3);
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, SCBUSCR_SEL |
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SCBUSCR_BSY | SCBUSCR_DOUT | sc->sc_busc);
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nsp_cr_write_1(sc->port_res, NSPR_ARBITS, ARBITS_CLR);
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DELAY(3);
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nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR,
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SCBUSCR_SEL | SCBUSCR_DOUT | sc->sc_busc);
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DELAY(1);
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if ((nsp_io_control & NSP_WAIT_FOR_SELECT) != 0)
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{
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#define NSP_FIRST_SEL_WAIT 300
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#define NSP_SEL_CHECK_INTERVAL 10
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/* wait for a selection response */
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for (wc = 0; wc < NSP_FIRST_SEL_WAIT / NSP_SEL_CHECK_INTERVAL;
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wc ++)
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{
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ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
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if ((ph & SCBUSMON_BSY) == 0)
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{
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DELAY(NSP_SEL_CHECK_INTERVAL);
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continue;
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}
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DELAY(1);
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ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
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if ((ph & SCBUSMON_BSY) != 0)
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{
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nsphw_selection_done_and_expect_msgout(sc);
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SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
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return SCSI_LOW_START_OK;
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}
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}
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}
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/* check a selection timeout */
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nsp_start_timer(sc, NSP_TIMER_1MS);
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sc->sc_seltout = 1;
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return SCSI_LOW_START_OK;
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}
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static int
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nsp_world_start(sc, fdone)
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struct nsp_softc *sc;
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int fdone;
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{
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struct scsi_low_softc *slp = &sc->sc_sclow;
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sc->sc_cnt = 0;
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sc->sc_seltout = 0;
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if ((slp->sl_cfgflags & CFG_NOATTEN) == 0)
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sc->sc_busc = SCBUSCR_ATN;
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else
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sc->sc_busc = 0;
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if ((slp->sl_cfgflags & CFG_NOPARITY) == 0)
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sc->sc_parr = PARITYR_ENABLE | PARITYR_CLEAR;
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else
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sc->sc_parr = 0;
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sc->sc_icr = (SCIENR_SCCHG | SCIENR_RESEL | SCIENR_RST);
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nsphw_init(sc);
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scsi_low_bus_reset(slp);
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return 0;
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}
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struct ncp_synch_data {
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u_int min_period;
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u_int max_period;
|
|
u_int chip_period;
|
|
u_int ack_width;
|
|
};
|
|
|
|
static struct ncp_synch_data ncp_sync_data_40M[] = {
|
|
{0x0c,0x0c,0x1,0}, /* 20MB 50ns*/
|
|
{0x19,0x19,0x3,1}, /* 10MB 100ns*/
|
|
{0x1a,0x25,0x5,2}, /* 7.5MB 150ns*/
|
|
{0x26,0x32,0x7,3}, /* 5MB 200ns*/
|
|
{0x0, 0, 0, 0}
|
|
};
|
|
|
|
static struct ncp_synch_data ncp_sync_data_20M[] = {
|
|
{0x19,0x19,0x1,0}, /* 10MB 100ns*/
|
|
{0x1a,0x25,0x2,0}, /* 7.5MB 150ns*/
|
|
{0x26,0x32,0x3,1}, /* 5MB 200ns*/
|
|
{0x0, 0, 0, 0}
|
|
};
|
|
|
|
static int
|
|
nsp_msg(sc, ti, msg)
|
|
struct nsp_softc *sc;
|
|
struct targ_info *ti;
|
|
u_int msg;
|
|
{
|
|
struct ncp_synch_data *sdp;
|
|
struct nsp_targ_info *nti = (void *) ti;
|
|
u_int period, offset;
|
|
int i, error;
|
|
|
|
if ((msg & SCSI_LOW_MSG_WIDE) != 0)
|
|
{
|
|
if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
|
|
{
|
|
ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
|
|
return EINVAL;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
|
|
return 0;
|
|
|
|
period = ti->ti_maxsynch.period;
|
|
offset = ti->ti_maxsynch.offset;
|
|
if (sc->sc_iclkdiv == CLKDIVR_20M)
|
|
sdp = &ncp_sync_data_20M[0];
|
|
else
|
|
sdp = &ncp_sync_data_40M[0];
|
|
|
|
for (i = 0; sdp->max_period != 0; i ++, sdp ++)
|
|
{
|
|
if (period >= sdp->min_period && period <= sdp->max_period)
|
|
break;
|
|
}
|
|
|
|
if (period != 0 && sdp->max_period == 0)
|
|
{
|
|
/*
|
|
* NO proper period/offset found,
|
|
* Retry neg with the target.
|
|
*/
|
|
ti->ti_maxsynch.period = 0;
|
|
ti->ti_maxsynch.offset = 0;
|
|
nti->nti_reg_syncr = 0;
|
|
nti->nti_reg_ackwidth = 0;
|
|
error = EINVAL;
|
|
}
|
|
else
|
|
{
|
|
nti->nti_reg_syncr = (sdp->chip_period << SYNCR_PERS) |
|
|
(offset & SYNCR_OFFM);
|
|
nti->nti_reg_ackwidth = sdp->ack_width;
|
|
error = 0;
|
|
}
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_SYNCR, nti->nti_reg_syncr);
|
|
nsp_cr_write_1(sc->port_res, NSPR_ACKWIDTH, nti->nti_reg_ackwidth);
|
|
return error;
|
|
}
|
|
|
|
static int
|
|
nsp_targ_init(sc, ti, action)
|
|
struct nsp_softc *sc;
|
|
struct targ_info *ti;
|
|
int action;
|
|
{
|
|
struct nsp_targ_info *nti = (void *) ti;
|
|
|
|
if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
|
|
{
|
|
ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
|
|
ti->ti_maxsynch.period = 100 / 4;
|
|
ti->ti_maxsynch.offset = 15;
|
|
nti->nti_reg_syncr = 0;
|
|
nti->nti_reg_ackwidth = 0;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nsp_start_timer(sc, time)
|
|
struct nsp_softc *sc;
|
|
int time;
|
|
{
|
|
|
|
sc->sc_timer = time;
|
|
nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, time);
|
|
}
|
|
|
|
/**************************************************************
|
|
* General probe attach
|
|
**************************************************************/
|
|
int
|
|
nspprobesubr(struct resource *res, u_int dvcfg)
|
|
{
|
|
u_int8_t regv;
|
|
|
|
regv = bus_read_1(res, nsp_fifosr);
|
|
if (regv < 0x11 || regv >= 0x20)
|
|
return 0;
|
|
return 1;
|
|
}
|
|
|
|
void
|
|
nspattachsubr(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
|
|
sc->sc_idbit = (1 << slp->sl_hostid);
|
|
slp->sl_flags |= HW_READ_PADDING;
|
|
slp->sl_funcs = &nspfuncs;
|
|
sc->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
|
|
|
|
(void) scsi_low_attach(slp, 0, NSP_NTARGETS, NSP_NLUNS,
|
|
sizeof(struct nsp_targ_info), 0);
|
|
}
|
|
|
|
/**************************************************************
|
|
* PDMA functions
|
|
**************************************************************/
|
|
static u_int
|
|
nsp_fifo_count(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
u_int count;
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_RSS_ACK | PTCLRR_PT);
|
|
count = bus_read_1(sc->port_res, nsp_datar);
|
|
count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 8);
|
|
count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 16);
|
|
return count;
|
|
}
|
|
|
|
static u_int
|
|
nsp_request_count(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
u_int count;
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_RSS_REQ | PTCLRR_PT);
|
|
count = bus_read_1(sc->port_res, nsp_datar);
|
|
count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 8);
|
|
count += (((u_int) bus_read_1(sc->port_res, nsp_datar)) << 16);
|
|
return count;
|
|
}
|
|
|
|
static void
|
|
nsp_setup_fifo(sc, on, direction, datalen)
|
|
struct nsp_softc *sc;
|
|
int on;
|
|
int direction;
|
|
int datalen;
|
|
{
|
|
u_int8_t xfermode;
|
|
|
|
sc->sc_suspendio = 0;
|
|
if (on == NSP_FIFO_OFF)
|
|
{
|
|
xfermode = XFERMR_IO8;
|
|
goto out;
|
|
}
|
|
|
|
/* check if suspend io OK ? */
|
|
if (datalen > 0)
|
|
{
|
|
if (direction == SCSI_LOW_READ)
|
|
{
|
|
if ((nsp_io_control & NSP_READ_SUSPEND_IO) != 0 &&
|
|
(datalen % nsp_read_suspend_bytes) == 0)
|
|
sc->sc_suspendio = nsp_read_suspend_bytes;
|
|
}
|
|
else
|
|
{
|
|
if ((nsp_io_control & NSP_WRITE_SUSPEND_IO) != 0 &&
|
|
(datalen % nsp_write_suspend_bytes) == 0)
|
|
sc->sc_suspendio = nsp_write_suspend_bytes;
|
|
}
|
|
}
|
|
|
|
/* determine a transfer type */
|
|
if (datalen < DEV_BSIZE || (datalen & 3) != 0)
|
|
{
|
|
if (sc->mem_res != NULL &&
|
|
(nsp_io_control & NSP_USE_MEMIO) != 0)
|
|
xfermode = XFERMR_XEN | XFERMR_MEM8;
|
|
else
|
|
xfermode = XFERMR_XEN | XFERMR_IO8;
|
|
}
|
|
else
|
|
{
|
|
if (sc->mem_res != NULL &&
|
|
(nsp_io_control & NSP_USE_MEMIO) != 0)
|
|
xfermode = XFERMR_XEN | XFERMR_MEM32;
|
|
else
|
|
xfermode = XFERMR_XEN | XFERMR_IO32;
|
|
|
|
if (sc->sc_suspendio > 0)
|
|
xfermode |= XFERMR_FIFOEN;
|
|
}
|
|
|
|
out:
|
|
sc->sc_xfermr = xfermode;
|
|
nsp_cr_write_1(sc->port_res, NSPR_XFERMR, sc->sc_xfermr);
|
|
}
|
|
|
|
static void
|
|
nsp_pdma_end(sc, ti)
|
|
struct nsp_softc *sc;
|
|
struct targ_info *ti;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
struct slccb *cb = slp->sl_Qnexus;
|
|
u_int len = 0, cnt;
|
|
|
|
sc->sc_dataout_timeout = 0;
|
|
slp->sl_flags &= ~HW_PDMASTART;
|
|
nsp_setup_fifo(sc, NSP_FIFO_OFF, SCSI_LOW_READ, 0);
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
{
|
|
sc->sc_icr &= ~SCIENR_FIFO;
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr);
|
|
}
|
|
|
|
if (cb == NULL)
|
|
{
|
|
slp->sl_error |= PDMAERR;
|
|
return;
|
|
}
|
|
|
|
if (ti->ti_phase == PH_DATA)
|
|
{
|
|
cnt = nsp_fifo_count(sc);
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
|
|
{
|
|
len = sc->sc_cnt - cnt;
|
|
if (sc->sc_cnt >= cnt &&
|
|
slp->sl_scp.scp_datalen + len <=
|
|
cb->ccb_scp.scp_datalen)
|
|
{
|
|
slp->sl_scp.scp_data -= len;
|
|
slp->sl_scp.scp_datalen += len;
|
|
}
|
|
else
|
|
{
|
|
slp->sl_error |= PDMAERR;
|
|
device_printf(slp->sl_dev,
|
|
"len %x >= datalen %x\n",
|
|
len, slp->sl_scp.scp_datalen);
|
|
}
|
|
}
|
|
else if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
|
|
{
|
|
if (sc->sc_cnt != cnt ||
|
|
sc->sc_cnt > cb->ccb_scp.scp_datalen)
|
|
{
|
|
slp->sl_error |= PDMAERR;
|
|
device_printf(slp->sl_dev,
|
|
"data read count error %x != %x (%x)\n",
|
|
sc->sc_cnt, cnt,
|
|
cb->ccb_scp.scp_datalen);
|
|
}
|
|
}
|
|
sc->sc_cnt = cnt;
|
|
scsi_low_data_finish(slp);
|
|
}
|
|
else
|
|
{
|
|
|
|
device_printf(slp->sl_dev, "data phase miss\n");
|
|
slp->sl_error |= PDMAERR;
|
|
}
|
|
}
|
|
|
|
#define RFIFO_CRIT 64
|
|
#define WFIFO_CRIT 32
|
|
|
|
static void
|
|
nsp_data_padding(sc, direction, count)
|
|
struct nsp_softc *sc;
|
|
int direction;
|
|
u_int count;
|
|
{
|
|
|
|
if (count > NSP_MAX_DATA_SIZE)
|
|
count = NSP_MAX_DATA_SIZE;
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_XFERMR, XFERMR_XEN | XFERMR_IO8);
|
|
if (direction == SCSI_LOW_READ)
|
|
{
|
|
while (count -- > 0)
|
|
(void) bus_read_1(sc->port_res, nsp_fifodr);
|
|
}
|
|
else
|
|
{
|
|
while (count -- > 0)
|
|
(void) bus_write_1(sc->port_res, nsp_fifodr, 0);
|
|
}
|
|
nsp_cr_write_1(sc->port_res, NSPR_XFERMR, sc->sc_xfermr);
|
|
}
|
|
|
|
static int
|
|
nsp_read_fifo(sc, suspendio)
|
|
struct nsp_softc *sc;
|
|
int suspendio;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
u_int res;
|
|
|
|
res = nsp_fifo_count(sc);
|
|
if (res == sc->sc_cnt)
|
|
return 0;
|
|
|
|
#ifdef NSP_DEBUG
|
|
if (res < sc->sc_cnt || res == (u_int) -1)
|
|
{
|
|
device_printf(slp->sl_dev,
|
|
"strange fifo ack count 0x%x < 0x%x\n", res, sc->sc_cnt);
|
|
return 0;
|
|
}
|
|
#endif /* NSP_DEBUG */
|
|
|
|
res = res - sc->sc_cnt;
|
|
if (res > slp->sl_scp.scp_datalen)
|
|
{
|
|
if ((slp->sl_error & PDMAERR) == 0)
|
|
{
|
|
device_printf(slp->sl_dev, "data overrun 0x%x > 0x%x\n",
|
|
res, slp->sl_scp.scp_datalen);
|
|
}
|
|
|
|
slp->sl_error |= PDMAERR;
|
|
slp->sl_scp.scp_datalen = 0;
|
|
|
|
if ((slp->sl_flags & HW_READ_PADDING) == 0)
|
|
{
|
|
device_printf(slp->sl_dev, "read padding required\n");
|
|
return 0;
|
|
}
|
|
|
|
nsp_data_padding(sc, SCSI_LOW_READ, res);
|
|
sc->sc_cnt += res;
|
|
return 1; /* padding start */
|
|
}
|
|
|
|
if (suspendio > 0 && slp->sl_scp.scp_datalen >= suspendio)
|
|
res = suspendio;
|
|
|
|
if ((sc->sc_xfermr & (XFERMR_MEM32 | XFERMR_MEM8)) != 0)
|
|
{
|
|
if ((sc->sc_xfermr & XFERMR_MEM32) != 0)
|
|
{
|
|
res &= ~3;
|
|
bus_read_region_4(sc->mem_res, 0,
|
|
(u_int32_t *) slp->sl_scp.scp_data, res >> 2);
|
|
}
|
|
else
|
|
{
|
|
bus_read_region_1(sc->mem_res, 0,
|
|
(u_int8_t *) slp->sl_scp.scp_data, res);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((sc->sc_xfermr & XFERMR_IO32) != 0)
|
|
{
|
|
res &= ~3;
|
|
bus_read_multi_4(sc->port_res, nsp_fifodr,
|
|
(u_int32_t *) slp->sl_scp.scp_data, res >> 2);
|
|
}
|
|
else
|
|
{
|
|
bus_read_multi_1(sc->port_res, nsp_fifodr,
|
|
(u_int8_t *) slp->sl_scp.scp_data, res);
|
|
}
|
|
}
|
|
|
|
if (nsp_cr_read_1(sc->port_res, NSPR_PARITYR) & PARITYR_PE)
|
|
{
|
|
nsp_cr_write_1(sc->port_res, NSPR_PARITYR,
|
|
PARITYR_ENABLE | PARITYR_CLEAR);
|
|
scsi_low_assert_msg(slp, slp->sl_Tnexus, SCSI_LOW_MSG_ERROR, 1);
|
|
}
|
|
|
|
slp->sl_scp.scp_data += res;
|
|
slp->sl_scp.scp_datalen -= res;
|
|
sc->sc_cnt += res;
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nsp_write_fifo(sc, suspendio)
|
|
struct nsp_softc *sc;
|
|
int suspendio;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
u_int res;
|
|
register u_int8_t stat;
|
|
|
|
if (suspendio > 0)
|
|
{
|
|
#ifdef NSP_DEBUG
|
|
if ((slp->sl_scp.scp_datalen % WFIFO_CRIT) != 0)
|
|
{
|
|
device_printf(slp->sl_dev,
|
|
"strange write length 0x%x\n",
|
|
slp->sl_scp.scp_datalen);
|
|
}
|
|
#endif /* NSP_DEBUG */
|
|
res = slp->sl_scp.scp_datalen % suspendio;
|
|
if (res == 0)
|
|
{
|
|
res = suspendio;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
res = WFIFO_CRIT;
|
|
}
|
|
|
|
if (res > slp->sl_scp.scp_datalen)
|
|
res = slp->sl_scp.scp_datalen;
|
|
|
|
/* XXX: reconfirm! */
|
|
stat = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON) & SCBUSMON_PHMASK;
|
|
if (stat != PHASE_DATAOUT)
|
|
return 0;
|
|
|
|
if ((sc->sc_xfermr & (XFERMR_MEM32 | XFERMR_MEM8)) != 0)
|
|
{
|
|
if ((sc->sc_xfermr & XFERMR_MEM32) != 0)
|
|
{
|
|
bus_write_region_4(sc->mem_res, 0,
|
|
(u_int32_t *) slp->sl_scp.scp_data, res >> 2);
|
|
}
|
|
else
|
|
{
|
|
bus_write_region_1(sc->mem_res, 0,
|
|
(u_int8_t *) slp->sl_scp.scp_data, res);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if ((sc->sc_xfermr & XFERMR_IO32) != 0)
|
|
{
|
|
bus_write_multi_4(sc->port_res, nsp_fifodr,
|
|
(u_int32_t *) slp->sl_scp.scp_data, res >> 2);
|
|
}
|
|
else
|
|
{
|
|
bus_write_multi_1(sc->port_res, nsp_fifodr,
|
|
(u_int8_t *) slp->sl_scp.scp_data, res);
|
|
}
|
|
}
|
|
|
|
slp->sl_scp.scp_datalen -= res;
|
|
slp->sl_scp.scp_data += res;
|
|
sc->sc_cnt += res;
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nsp_wait_interrupt(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
int tout;
|
|
register u_int8_t isrc;
|
|
|
|
for (tout = 0; tout < DEV_BSIZE / 10; tout ++)
|
|
{
|
|
isrc = bus_read_1(sc->port_res, nsp_irqsr);
|
|
if ((isrc & (IRQSR_SCSI | IRQSR_FIFO)) != 0)
|
|
{
|
|
if ((isrc & IRQSR_FIFO) != 0)
|
|
{
|
|
bus_write_1(sc->port_res,
|
|
nsp_irqcr, IRQCR_FIFOCL);
|
|
}
|
|
return 1;
|
|
}
|
|
DELAY(1);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static void
|
|
nsp_pio_read(sc, suspendio)
|
|
struct nsp_softc *sc;
|
|
int suspendio;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
int tout, padding, datalen;
|
|
register u_int8_t stat, fstat;
|
|
|
|
padding = 0;
|
|
tout = sc->sc_tmaxcnt;
|
|
slp->sl_flags |= HW_PDMASTART;
|
|
datalen = slp->sl_scp.scp_datalen;
|
|
|
|
ReadLoop:
|
|
while (1)
|
|
{
|
|
stat = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
if (stat == (u_int8_t) -1)
|
|
return;
|
|
|
|
/* out of data phase */
|
|
if ((stat & SCBUSMON_PHMASK) != PHASE_DATAIN)
|
|
{
|
|
nsp_read_fifo(sc, 0);
|
|
return;
|
|
}
|
|
|
|
/* data phase */
|
|
fstat = bus_read_1(sc->port_res, nsp_fifosr);
|
|
if ((fstat & FIFOSR_FULLEMP) != 0)
|
|
{
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
{
|
|
bus_write_1(sc->port_res, nsp_irqcr,
|
|
IRQCR_FIFOCL);
|
|
}
|
|
|
|
if (suspendio > 0)
|
|
{
|
|
padding |= nsp_read_fifo(sc, suspendio);
|
|
}
|
|
else
|
|
{
|
|
padding |= nsp_read_fifo(sc, 0);
|
|
}
|
|
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
if (padding == 0 && slp->sl_scp.scp_datalen <= 0)
|
|
return;
|
|
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
break;
|
|
|
|
DELAY(1);
|
|
}
|
|
|
|
if ((-- tout) <= 0)
|
|
{
|
|
device_printf(slp->sl_dev, "nsp_pio_read: timeout\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
|
|
if (slp->sl_scp.scp_datalen > 0 &&
|
|
slp->sl_scp.scp_datalen > datalen - nsp_read_interrupt_bytes)
|
|
{
|
|
if (nsp_wait_interrupt(sc) != 0)
|
|
goto ReadLoop;
|
|
}
|
|
}
|
|
|
|
static void
|
|
nsp_pio_write(sc, suspendio)
|
|
struct nsp_softc *sc;
|
|
int suspendio;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
u_int rcount, acount;
|
|
int tout, datalen;
|
|
register u_int8_t stat, fstat;
|
|
|
|
tout = sc->sc_tmaxcnt;
|
|
slp->sl_flags |= HW_PDMASTART;
|
|
datalen = slp->sl_scp.scp_datalen;
|
|
|
|
WriteLoop:
|
|
while (1)
|
|
{
|
|
stat = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON) & SCBUSMON_PHMASK;
|
|
if (stat != PHASE_DATAOUT)
|
|
return;
|
|
|
|
if (slp->sl_scp.scp_datalen <= 0)
|
|
{
|
|
if (sc->sc_dataout_timeout == 0)
|
|
sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ;
|
|
return;
|
|
}
|
|
|
|
fstat = bus_read_1(sc->port_res, nsp_fifosr);
|
|
if ((fstat & FIFOSR_FULLEMP) != 0)
|
|
{
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
{
|
|
bus_write_1(sc->port_res, nsp_irqcr,
|
|
IRQCR_FIFOCL);
|
|
}
|
|
|
|
if (suspendio > 0)
|
|
{
|
|
/* XXX:IMPORTANT:
|
|
* To avoid timeout of pcmcia bus
|
|
* (not scsi bus!), we should check
|
|
* the scsi device sends us request
|
|
* signals, which means the scsi device
|
|
* is ready to receive data without
|
|
* heavy delays.
|
|
*/
|
|
if ((slp->sl_scp.scp_datalen % suspendio) == 0)
|
|
{
|
|
/* Step I:
|
|
* fill the nsp fifo, and waiting for
|
|
* the fifo empty.
|
|
*/
|
|
nsp_write_fifo(sc, 0);
|
|
}
|
|
else
|
|
{
|
|
/* Step II:
|
|
* check the request singals.
|
|
*/
|
|
acount = nsp_fifo_count(sc);
|
|
rcount = nsp_request_count(sc);
|
|
if (rcount <= acount)
|
|
{
|
|
nsp_write_fifo(sc, 0);
|
|
#ifdef NSP_STATICS
|
|
nsp_statics.device_busy ++;
|
|
#endif /* NSP_STATICS */
|
|
}
|
|
else
|
|
{
|
|
nsp_write_fifo(sc, suspendio);
|
|
#ifdef NSP_STATICS
|
|
nsp_statics.device_data_write ++;
|
|
#endif /* NSP_STATICS */
|
|
}
|
|
}
|
|
}
|
|
else
|
|
{
|
|
nsp_write_fifo(sc, 0);
|
|
}
|
|
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
break;
|
|
}
|
|
else
|
|
{
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
break;
|
|
|
|
DELAY(1);
|
|
}
|
|
|
|
if ((-- tout) <= 0)
|
|
{
|
|
device_printf(slp->sl_dev, "nsp_pio_write: timeout\n");
|
|
return;
|
|
}
|
|
}
|
|
|
|
if (slp->sl_scp.scp_datalen > 0 &&
|
|
slp->sl_scp.scp_datalen > datalen - nsp_write_interrupt_bytes)
|
|
{
|
|
if (nsp_wait_interrupt(sc) != 0)
|
|
goto WriteLoop;
|
|
}
|
|
}
|
|
|
|
static int
|
|
nsp_negate_signal(struct nsp_softc *sc, u_int8_t mask, u_char *s)
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
int wc;
|
|
u_int8_t regv;
|
|
|
|
for (wc = 0; wc < NSP_DELAY_MAX / NSP_DELAY_INTERVAL; wc ++)
|
|
{
|
|
regv = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
if (regv == (u_int8_t) -1)
|
|
return -1;
|
|
if ((regv & mask) == 0)
|
|
return 1;
|
|
DELAY(NSP_DELAY_INTERVAL);
|
|
}
|
|
|
|
device_printf(slp->sl_dev, "%s nsp_negate_signal timeout\n", s);
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
nsp_xfer(sc, buf, len, phase, clear_atn)
|
|
struct nsp_softc *sc;
|
|
u_int8_t *buf;
|
|
int len;
|
|
int phase;
|
|
int clear_atn;
|
|
{
|
|
int ptr, rv;
|
|
|
|
for (ptr = 0; len > 0; len --, ptr ++)
|
|
{
|
|
rv = nsp_expect_signal(sc, phase, SCBUSMON_REQ);
|
|
if (rv <= 0)
|
|
goto out;
|
|
|
|
if (len == 1 && clear_atn != 0)
|
|
{
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR,
|
|
SCBUSCR_ADIR | SCBUSCR_ACKEN);
|
|
SCSI_LOW_DEASSERT_ATN(&sc->sc_sclow);
|
|
}
|
|
|
|
if (phase & SCBUSMON_IO)
|
|
{
|
|
buf[ptr] = nsp_cr_read_1(sc->port_res, NSPR_DATAACK);
|
|
}
|
|
else
|
|
{
|
|
nsp_cr_write_1(sc->port_res, NSPR_DATAACK, buf[ptr]);
|
|
}
|
|
nsp_negate_signal(sc, SCBUSMON_ACK, "xfer<ACK>");
|
|
}
|
|
|
|
out:
|
|
return len;
|
|
}
|
|
|
|
/**************************************************************
|
|
* disconnect & reselect (HW low)
|
|
**************************************************************/
|
|
static int
|
|
nsp_reselected(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
struct targ_info *ti;
|
|
u_int sid;
|
|
u_int8_t cr;
|
|
|
|
sid = (u_int) nsp_cr_read_1(sc->port_res, NSPR_RESELR);
|
|
sid &= ~sc->sc_idbit;
|
|
sid = ffs(sid) - 1;
|
|
if ((ti = scsi_low_reselected(slp, sid)) == NULL)
|
|
return EJUSTRETURN;
|
|
|
|
nsp_negate_signal(sc, SCBUSMON_SEL, "reselect<SEL>");
|
|
|
|
cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR);
|
|
cr &= ~(SCBUSCR_BSY | SCBUSCR_ATN);
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr);
|
|
cr |= SCBUSCR_ADIR | SCBUSCR_ACKEN;
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr);
|
|
|
|
#ifdef NSP_STATICS
|
|
nsp_statics.reselect ++;
|
|
#endif /* NSP_STATCIS */
|
|
return EJUSTRETURN;
|
|
}
|
|
|
|
static int
|
|
nsp_disconnected(sc, ti)
|
|
struct nsp_softc *sc;
|
|
struct targ_info *ti;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_PTCLRR, PTCLRR_PT | PTCLRR_ACK |
|
|
PTCLRR_REQ | PTCLRR_HOST);
|
|
if ((sc->sc_icr & SCIENR_FIFO) != 0)
|
|
{
|
|
sc->sc_icr &= ~SCIENR_FIFO;
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCIENR, sc->sc_icr);
|
|
}
|
|
sc->sc_cnt = 0;
|
|
sc->sc_dataout_timeout = 0;
|
|
#ifdef NSP_STATICS
|
|
nsp_statics.disconnect ++;
|
|
#endif /* NSP_STATICS */
|
|
scsi_low_disconnected(slp, ti);
|
|
return 1;
|
|
}
|
|
|
|
/**************************************************************
|
|
* SEQUENCER
|
|
**************************************************************/
|
|
static void nsp_error(struct nsp_softc *, u_char *, u_int8_t, u_int8_t, u_int8_t);
|
|
|
|
static void
|
|
nsp_error(struct nsp_softc * sc, u_char *s, u_int8_t isrc, u_int8_t ph,
|
|
u_int8_t irqphs)
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
|
|
device_printf(slp->sl_dev, "%s\n", s);
|
|
device_printf(slp->sl_dev, "isrc 0x%x scmon 0x%x irqphs 0x%x\n",
|
|
(u_int) isrc, (u_int) ph, (u_int) irqphs);
|
|
}
|
|
|
|
static int
|
|
nsp_target_nexus_establish(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
struct targ_info *ti = slp->sl_Tnexus;
|
|
struct nsp_targ_info *nti = (void *) ti;
|
|
|
|
/* setup synch transfer registers */
|
|
nsp_cr_write_1(sc->port_res, NSPR_SYNCR, nti->nti_reg_syncr);
|
|
nsp_cr_write_1(sc->port_res, NSPR_ACKWIDTH, nti->nti_reg_ackwidth);
|
|
|
|
/* setup pdma fifo (minimum) */
|
|
nsp_setup_fifo(sc, NSP_FIFO_ON, SCSI_LOW_READ, 0);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nsp_lun_nexus_establish(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nsp_ccb_nexus_establish(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
struct slccb *cb = slp->sl_Qnexus;
|
|
|
|
sc->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
|
|
|
|
/* setup pdma fifo */
|
|
nsp_setup_fifo(sc, NSP_FIFO_ON,
|
|
slp->sl_scp.scp_direction, slp->sl_scp.scp_datalen);
|
|
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
|
|
{
|
|
if (sc->sc_suspendio > 0 &&
|
|
(nsp_io_control & NSP_READ_FIFO_INTERRUPTS) != 0)
|
|
{
|
|
sc->sc_icr |= SCIENR_FIFO;
|
|
nsp_cr_write_1(sc->port_res,
|
|
NSPR_SCIENR, sc->sc_icr);
|
|
}
|
|
}
|
|
else
|
|
{
|
|
if (sc->sc_suspendio > 0 &&
|
|
(nsp_io_control & NSP_WRITE_FIFO_INTERRUPTS) != 0)
|
|
{
|
|
sc->sc_icr |= SCIENR_FIFO;
|
|
nsp_cr_write_1(sc->port_res,
|
|
NSPR_SCIENR, sc->sc_icr);
|
|
}
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
nsp_phase_match(struct nsp_softc *sc, u_int8_t phase, u_int8_t stat)
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
|
|
if ((stat & SCBUSMON_PHMASK) != phase)
|
|
{
|
|
device_printf(slp->sl_dev, "phase mismatch 0x%x != 0x%x\n",
|
|
(u_int) phase, (u_int) stat);
|
|
return EINVAL;
|
|
}
|
|
|
|
if ((stat & SCBUSMON_REQ) == 0)
|
|
return EINVAL;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int
|
|
nspintr(arg)
|
|
void *arg;
|
|
{
|
|
struct nsp_softc *sc = arg;
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
struct targ_info *ti;
|
|
struct buf *bp;
|
|
u_int derror, flags;
|
|
int len, rv;
|
|
u_int8_t isrc, ph, irqphs, cr, regv;
|
|
|
|
/*******************************************
|
|
* interrupt check
|
|
*******************************************/
|
|
if (slp->sl_flags & HW_INACTIVE)
|
|
return 0;
|
|
|
|
bus_write_1(sc->port_res, nsp_irqcr, IRQCR_IRQDIS);
|
|
isrc = bus_read_1(sc->port_res, nsp_irqsr);
|
|
if (isrc == (u_int8_t) -1 || (isrc & IRQSR_MASK) == 0)
|
|
{
|
|
bus_write_1(sc->port_res, nsp_irqcr, 0);
|
|
return 0;
|
|
}
|
|
|
|
/* XXX: IMPORTANT
|
|
* Do not read an irqphs register if no scsi phase interrupt.
|
|
* Unless, you should lose a scsi phase interrupt.
|
|
*/
|
|
ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
if ((isrc & IRQSR_SCSI) != 0)
|
|
{
|
|
irqphs = nsp_cr_read_1(sc->port_res, NSPR_IRQPHS);
|
|
}
|
|
else
|
|
irqphs = 0;
|
|
|
|
/*
|
|
* timer interrupt handler (scsi vs timer interrupts)
|
|
*/
|
|
if (sc->sc_timer != 0)
|
|
{
|
|
nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0);
|
|
nsp_cr_write_1(sc->port_res, NSPR_TIMERCNT, 0);
|
|
sc->sc_timer = 0;
|
|
}
|
|
|
|
/* check a timer interrupt */
|
|
regv = 0;
|
|
if ((isrc & IRQSR_TIMER) != 0)
|
|
{
|
|
if ((isrc & IRQSR_MASK) == IRQSR_TIMER && sc->sc_seltout == 0)
|
|
{
|
|
bus_write_1(sc->port_res, nsp_irqcr, IRQCR_TIMERCL);
|
|
return 1;
|
|
}
|
|
regv |= IRQCR_TIMERCL;
|
|
}
|
|
|
|
/* check a fifo interrupt */
|
|
if ((isrc & IRQSR_FIFO) != 0)
|
|
{
|
|
regv |= IRQCR_FIFOCL;
|
|
}
|
|
|
|
/* OK. enable all interrupts */
|
|
bus_write_1(sc->port_res, nsp_irqcr, regv);
|
|
|
|
/*******************************************
|
|
* debug section
|
|
*******************************************/
|
|
#ifdef NSP_DEBUG
|
|
if (nsp_debug)
|
|
{
|
|
nsp_error(sc, "current status", isrc, ph, irqphs);
|
|
scsi_low_print(slp, NULL);
|
|
#ifdef KDB
|
|
if (nsp_debug > 1)
|
|
kdb_enter(KDB_WHY_CAM, "nsp");
|
|
#endif /* KDB */
|
|
}
|
|
#endif /* NSP_DEBUG */
|
|
|
|
/*******************************************
|
|
* Parse hardware SCSI irq reasons register
|
|
*******************************************/
|
|
if ((isrc & IRQSR_SCSI) != 0)
|
|
{
|
|
if ((irqphs & IRQPHS_RST) != 0)
|
|
{
|
|
scsi_low_restart(slp, SCSI_LOW_RESTART_SOFT,
|
|
"bus reset (power off?)");
|
|
return 1;
|
|
}
|
|
|
|
if ((irqphs & IRQPHS_RSEL) != 0)
|
|
{
|
|
bus_write_1(sc->port_res, nsp_irqcr, IRQCR_RESCL);
|
|
if (nsp_reselected(sc) == EJUSTRETURN)
|
|
return 1;
|
|
}
|
|
|
|
if ((irqphs & (IRQPHS_PCHG | IRQPHS_LBF)) == 0)
|
|
return 1;
|
|
}
|
|
|
|
/*******************************************
|
|
* nexus check
|
|
*******************************************/
|
|
if ((ti = slp->sl_Tnexus) == NULL)
|
|
{
|
|
/* unknown scsi phase changes */
|
|
nsp_error(sc, "unknown scsi phase changes", isrc, ph, irqphs);
|
|
return 0;
|
|
}
|
|
|
|
/*******************************************
|
|
* aribitration & selection
|
|
*******************************************/
|
|
switch (ti->ti_phase)
|
|
{
|
|
case PH_SELSTART:
|
|
if ((ph & SCBUSMON_BSY) == 0)
|
|
{
|
|
if (sc->sc_seltout >= NSP_SELTIMEOUT)
|
|
{
|
|
sc->sc_seltout = 0;
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, 0);
|
|
return nsp_disconnected(sc, ti);
|
|
}
|
|
sc->sc_seltout ++;
|
|
nsp_start_timer(sc, NSP_TIMER_1MS);
|
|
return 1;
|
|
}
|
|
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
|
|
nsphw_selection_done_and_expect_msgout(sc);
|
|
return 1;
|
|
|
|
case PH_SELECTED:
|
|
if ((isrc & IRQSR_SCSI) == 0)
|
|
return 1;
|
|
|
|
nsp_target_nexus_establish(sc);
|
|
break;
|
|
|
|
case PH_RESEL:
|
|
if ((isrc & IRQSR_SCSI) == 0)
|
|
return 1;
|
|
|
|
nsp_target_nexus_establish(sc);
|
|
if ((ph & SCBUSMON_PHMASK) != PHASE_MSGIN)
|
|
{
|
|
device_printf(slp->sl_dev,
|
|
"unexpected phase after reselect\n");
|
|
slp->sl_error |= FATALIO;
|
|
scsi_low_assert_msg(slp, ti, SCSI_LOW_MSG_ABORT, 1);
|
|
return 1;
|
|
}
|
|
break;
|
|
|
|
case PH_DATA:
|
|
if ((isrc & IRQSR_SCSI) != 0)
|
|
break;
|
|
if ((isrc & IRQSR_FIFO) != 0)
|
|
{
|
|
if (NSP_IS_PHASE_DATA(ph) == 0)
|
|
return 1;
|
|
irqphs = (ph & IRQPHS_PHMASK);
|
|
break;
|
|
}
|
|
return 1;
|
|
|
|
default:
|
|
if ((isrc & IRQSR_SCSI) == 0)
|
|
return 1;
|
|
break;
|
|
}
|
|
|
|
/*******************************************
|
|
* data phase control
|
|
*******************************************/
|
|
if (slp->sl_flags & HW_PDMASTART)
|
|
{
|
|
if ((isrc & IRQSR_SCSI) != 0 &&
|
|
NSP_IS_IRQPHS_DATA(irqphs) == 0)
|
|
{
|
|
if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
|
|
nsp_pio_read(sc, 0);
|
|
nsp_pdma_end(sc, ti);
|
|
}
|
|
}
|
|
|
|
/*******************************************
|
|
* scsi seq
|
|
*******************************************/
|
|
if (slp->sl_msgphase != 0 && (irqphs & IRQPHS_LBF) != 0)
|
|
return nsp_disconnected(sc, ti);
|
|
|
|
/* check unexpected bus free state */
|
|
if (ph == 0)
|
|
{
|
|
nsp_error(sc, "unexpected bus free", isrc, ph, irqphs);
|
|
return nsp_disconnected(sc, ti);
|
|
}
|
|
|
|
/* check normal scsi phase */
|
|
switch (irqphs & IRQPHS_PHMASK)
|
|
{
|
|
case IRQPHS_CMD:
|
|
if (nsp_phase_match(sc, PHASE_CMD, ph) != 0)
|
|
return 1;
|
|
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
|
|
if (scsi_low_cmd(slp, ti) != 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_CMDCR, CMDCR_PTCLR);
|
|
for (len = 0; len < slp->sl_scp.scp_cmdlen; len ++)
|
|
nsp_cr_write_1(sc->port_res, NSPR_CMDDR,
|
|
slp->sl_scp.scp_cmd[len]);
|
|
|
|
nsp_cr_write_1(sc->port_res, NSPR_CMDCR, CMDCR_PTCLR | CMDCR_EXEC);
|
|
break;
|
|
|
|
case IRQPHS_DATAOUT:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
|
|
if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
|
|
nsp_pio_write(sc, sc->sc_suspendio);
|
|
break;
|
|
|
|
case IRQPHS_DATAIN:
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
|
|
if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
|
|
nsp_pio_read(sc, sc->sc_suspendio);
|
|
break;
|
|
|
|
case IRQPHS_STATUS:
|
|
if (nsp_phase_match(sc, PHASE_STATUS, ph) != 0)
|
|
return 1;
|
|
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
|
|
regv = nsp_cr_read_1(sc->port_res, NSPR_DATA);
|
|
if (nsp_cr_read_1(sc->port_res, NSPR_PARITYR) & PARITYR_PE)
|
|
{
|
|
nsp_cr_write_1(sc->port_res, NSPR_PARITYR,
|
|
PARITYR_ENABLE | PARITYR_CLEAR);
|
|
derror = SCSI_LOW_DATA_PE;
|
|
}
|
|
else
|
|
derror = 0;
|
|
|
|
/* assert ACK */
|
|
cr = SCBUSCR_ACK | nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR);
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr);
|
|
|
|
if (scsi_low_statusin(slp, ti, derror | regv) != 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
|
|
/* check REQ nagated */
|
|
nsp_negate_signal(sc, SCBUSMON_REQ, "statin<REQ>");
|
|
|
|
/* deassert ACK */
|
|
cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR) & (~SCBUSCR_ACK);
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr);
|
|
break;
|
|
|
|
case IRQPHS_MSGOUT:
|
|
if (nsp_phase_match(sc, PHASE_MSGOUT, ph) != 0)
|
|
return 1;
|
|
|
|
#ifdef NSP_MSGOUT_SERIALIZE
|
|
/*
|
|
* XXX: NSP QUIRK
|
|
* NSP invoke interrupts only in the case of scsi phase changes,
|
|
* therefore we should poll the scsi phase here to catch
|
|
* the next "msg out" if exists (no scsi phase changes).
|
|
*/
|
|
rv = len = 16;
|
|
do {
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
|
|
flags = (ti->ti_ophase != ti->ti_phase) ?
|
|
SCSI_LOW_MSGOUT_INIT : 0;
|
|
len = scsi_low_msgout(slp, ti, flags);
|
|
|
|
if (len > 1 && slp->sl_atten == 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
|
|
if (nsp_xfer(sc, ti->ti_msgoutstr, len, PHASE_MSGOUT,
|
|
slp->sl_clear_atten) != 0)
|
|
{
|
|
slp->sl_error |= FATALIO;
|
|
nsp_error(sc, "MSGOUT: xfer short",
|
|
isrc, ph, irqphs);
|
|
}
|
|
|
|
/* catch a next signal */
|
|
rv = nsp_expect_signal(sc, PHASE_MSGOUT, SCBUSMON_REQ);
|
|
}
|
|
while (rv > 0 && len -- > 0);
|
|
|
|
#else /* !NSP_MSGOUT_SERIALIZE */
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
|
|
flags = SCSI_LOW_MSGOUT_UNIFY;
|
|
if (ti->ti_ophase != ti->ti_phase)
|
|
flags |= SCSI_LOW_MSGOUT_INIT;
|
|
len = scsi_low_msgout(slp, ti, flags);
|
|
|
|
if (len > 1 && slp->sl_atten == 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
|
|
if (nsp_xfer(sc, ti->ti_msgoutstr, len, PHASE_MSGOUT,
|
|
slp->sl_clear_atten) != 0)
|
|
{
|
|
nsp_error(sc, "MSGOUT: xfer short", isrc, ph, irqphs);
|
|
}
|
|
|
|
#endif /* !NSP_MSGOUT_SERIALIZE */
|
|
break;
|
|
|
|
case IRQPHS_MSGIN:
|
|
if (nsp_phase_match(sc, PHASE_MSGIN, ph) != 0)
|
|
return 1;
|
|
|
|
/*
|
|
* XXX: NSP QUIRK
|
|
* NSP invoke interrupts only in the case of scsi phase changes,
|
|
* therefore we should poll the scsi phase here to catch
|
|
* the next "msg in" if exists (no scsi phase changes).
|
|
*/
|
|
rv = len = 16;
|
|
do {
|
|
SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
|
|
|
|
/* read a data */
|
|
regv = nsp_cr_read_1(sc->port_res, NSPR_DATA);
|
|
if (nsp_cr_read_1(sc->port_res, NSPR_PARITYR) & PARITYR_PE)
|
|
{
|
|
nsp_cr_write_1(sc->port_res,
|
|
NSPR_PARITYR,
|
|
PARITYR_ENABLE | PARITYR_CLEAR);
|
|
derror = SCSI_LOW_DATA_PE;
|
|
}
|
|
else
|
|
{
|
|
derror = 0;
|
|
}
|
|
|
|
/* assert ack */
|
|
cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR) | SCBUSCR_ACK;
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr);
|
|
|
|
if (scsi_low_msgin(slp, ti, regv | derror) == 0)
|
|
{
|
|
if (scsi_low_is_msgout_continue(ti, 0) != 0)
|
|
{
|
|
scsi_low_attention(slp);
|
|
}
|
|
}
|
|
|
|
/* check REQ nagated */
|
|
nsp_negate_signal(sc, SCBUSMON_REQ, "msgin<REQ>");
|
|
|
|
/* deassert ack */
|
|
cr = nsp_cr_read_1(sc->port_res, NSPR_SCBUSCR) & (~SCBUSCR_ACK);
|
|
nsp_cr_write_1(sc->port_res, NSPR_SCBUSCR, cr);
|
|
|
|
/* catch a next signal */
|
|
rv = nsp_expect_signal(sc, PHASE_MSGIN, SCBUSMON_REQ);
|
|
}
|
|
while (rv > 0 && len -- > 0);
|
|
break;
|
|
|
|
default:
|
|
slp->sl_error |= FATALIO;
|
|
nsp_error(sc, "unknown scsi phase", isrc, ph, irqphs);
|
|
break;
|
|
}
|
|
|
|
return 1;
|
|
|
|
#if 0
|
|
timerout:
|
|
nsp_start_timer(sc, NSP_TIMER_1MS);
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
static int
|
|
nsp_timeout(sc)
|
|
struct nsp_softc *sc;
|
|
{
|
|
struct scsi_low_softc *slp = &sc->sc_sclow;
|
|
int tout;
|
|
u_int8_t ph, regv;
|
|
|
|
if (slp->sl_Tnexus == NULL)
|
|
return 0;
|
|
|
|
ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
switch (ph & SCBUSMON_PHMASK)
|
|
{
|
|
case PHASE_DATAOUT:
|
|
if (sc->sc_dataout_timeout == 0)
|
|
break;
|
|
|
|
/* check a fifo empty */
|
|
regv = bus_read_1(sc->port_res, nsp_fifosr);
|
|
if ((regv & FIFOSR_FULLEMP) == 0)
|
|
break;
|
|
bus_write_1(sc->port_res, nsp_irqcr, IRQCR_FIFOCL);
|
|
|
|
/* check still requested */
|
|
ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
if ((ph & SCBUSMON_REQ) == 0)
|
|
break;
|
|
/* check timeout */
|
|
if ((-- sc->sc_dataout_timeout) > 0)
|
|
break;
|
|
|
|
slp->sl_error |= PDMAERR;
|
|
if ((slp->sl_flags & HW_WRITE_PADDING) == 0)
|
|
{
|
|
device_printf(slp->sl_dev, "write padding required\n");
|
|
break;
|
|
}
|
|
|
|
tout = NSP_DELAY_MAX;
|
|
while (tout -- > 0)
|
|
{
|
|
ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
if ((ph & SCBUSMON_PHMASK) != PHASE_DATAOUT)
|
|
break;
|
|
regv = bus_read_1(sc->port_res, nsp_fifosr);
|
|
if ((regv & FIFOSR_FULLEMP) == 0)
|
|
{
|
|
DELAY(1);
|
|
continue;
|
|
}
|
|
|
|
bus_write_1(sc->port_res, nsp_irqcr, IRQCR_FIFOCL);
|
|
nsp_data_padding(sc, SCSI_LOW_WRITE, 32);
|
|
}
|
|
ph = nsp_cr_read_1(sc->port_res, NSPR_SCBUSMON);
|
|
if ((ph & SCBUSMON_PHMASK) == PHASE_DATAOUT)
|
|
sc->sc_dataout_timeout = SCSI_LOW_TIMEOUT_HZ;
|
|
break;
|
|
|
|
default:
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|