322 lines
7.8 KiB
C
322 lines
7.8 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: dwlpx.c,v 1.5 1998/08/10 07:53:59 dfr Exp $
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*/
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#include "opt_simos.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/swiz.h>
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#include <alpha/tlsb/dwlpxreg.h>
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#include <alpha/tlsb/tlsbreg.h>
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#include <alpha/tlsb/tlsbvar.h>
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#include <alpha/tlsb/kftxxvar.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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#define DWLPX_BASE(n, h) ((((u_long)(n) - 4) << 36) \
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| ((u_long)(h) << 34) \
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| (1L << 39))
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static devclass_t dwlpx_devclass;
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static device_t dwlpx0; /* XXX only one for now */
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struct dwlpx_softc {
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vm_offset_t dmem_base; /* dense memory */
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vm_offset_t smem_base; /* sparse memory */
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vm_offset_t io_base; /* sparse i/o */
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vm_offset_t cfg_base; /* sparse pci config */
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};
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#define DWLPX_SOFTC(dev) (struct dwlpx_softc*) device_get_softc(dev)
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static alpha_chipset_inb_t dwlpx_inb;
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static alpha_chipset_inw_t dwlpx_inw;
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static alpha_chipset_inl_t dwlpx_inl;
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static alpha_chipset_outb_t dwlpx_outb;
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static alpha_chipset_outw_t dwlpx_outw;
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static alpha_chipset_outl_t dwlpx_outl;
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static alpha_chipset_readb_t dwlpx_readb;
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static alpha_chipset_readw_t dwlpx_readw;
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static alpha_chipset_readl_t dwlpx_readl;
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static alpha_chipset_writeb_t dwlpx_writeb;
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static alpha_chipset_writew_t dwlpx_writew;
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static alpha_chipset_writel_t dwlpx_writel;
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static alpha_chipset_maxdevs_t dwlpx_maxdevs;
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static alpha_chipset_cfgreadb_t dwlpx_cfgreadb;
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static alpha_chipset_cfgreadw_t dwlpx_cfgreadw;
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static alpha_chipset_cfgreadl_t dwlpx_cfgreadl;
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static alpha_chipset_cfgwriteb_t dwlpx_cfgwriteb;
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static alpha_chipset_cfgwritew_t dwlpx_cfgwritew;
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static alpha_chipset_cfgwritel_t dwlpx_cfgwritel;
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static alpha_chipset_t dwlpx_chipset = {
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dwlpx_inb,
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dwlpx_inw,
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dwlpx_inl,
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dwlpx_outb,
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dwlpx_outw,
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dwlpx_outl,
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dwlpx_readb,
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dwlpx_readw,
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dwlpx_readl,
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dwlpx_writeb,
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dwlpx_writew,
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dwlpx_writel,
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dwlpx_maxdevs,
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dwlpx_cfgreadb,
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dwlpx_cfgreadw,
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dwlpx_cfgreadl,
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dwlpx_cfgwriteb,
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dwlpx_cfgwritew,
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dwlpx_cfgwritel,
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};
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/*
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* For supporting multiple busses, we will encode the dwlpx unit number into
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* the port address as Linux does.
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*/
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static u_int8_t
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dwlpx_inb(u_int32_t port)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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return SPARSE_READ_BYTE(sc->io_base, port);
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}
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static u_int16_t
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dwlpx_inw(u_int32_t port)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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return SPARSE_READ_WORD(sc->io_base, port);
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}
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static u_int32_t
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dwlpx_inl(u_int32_t port)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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return SPARSE_READ_LONG(sc->io_base, port);
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}
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static void
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dwlpx_outb(u_int32_t port, u_int8_t data)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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SPARSE_WRITE_BYTE(sc->io_base, port, data);
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}
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static void
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dwlpx_outw(u_int32_t port, u_int16_t data)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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SPARSE_WRITE_WORD(sc->io_base, port, data);
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}
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static void
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dwlpx_outl(u_int32_t port, u_int32_t data)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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SPARSE_WRITE_LONG(sc->io_base, port, data);
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}
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static u_int8_t
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dwlpx_readb(u_int32_t pa)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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return SPARSE_READ_BYTE(sc->smem_base, pa);
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}
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static u_int16_t
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dwlpx_readw(u_int32_t pa)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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return SPARSE_READ_WORD(sc->smem_base, pa);
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}
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static u_int32_t
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dwlpx_readl(u_int32_t pa)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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return SPARSE_READ_LONG(sc->smem_base, pa);
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}
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static void
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dwlpx_writeb(u_int32_t pa, u_int8_t data)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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SPARSE_WRITE_BYTE(sc->smem_base, pa, data);
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}
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static void
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dwlpx_writew(u_int32_t pa, u_int16_t data)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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SPARSE_WRITE_WORD(sc->smem_base, pa, data);
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}
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static void
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dwlpx_writel(u_int32_t pa, u_int32_t data)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0);
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SPARSE_WRITE_LONG(sc->smem_base, pa, data);
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}
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static int
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dwlpx_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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/* XXX only support bus 0 */
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#define DWLPX_CFGOFF(b, s, f, r) \
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(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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#define CFGREAD(b, s, f, r, width) \
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); \
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vm_offset_t off = DWLPX_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg_base, off); \
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if (badaddr((caddr_t)kv, 4)) return ~0; \
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return SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv))
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#define CFGWRITE(b, s, f, r, data, width) \
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struct dwlpx_softc* sc = DWLPX_SOFTC(dwlpx0); \
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vm_offset_t off = DWLPX_CFGOFF(b, s, f, r); \
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vm_offset_t kv = SPARSE_##width##_ADDRESS(sc->cfg_base, off); \
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if (badaddr((caddr_t)kv, 4)) return; \
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SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data))
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static u_int8_t
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dwlpx_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(b, s, f, r, BYTE);
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}
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static u_int16_t
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dwlpx_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(b, s, f, r, WORD);
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}
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static u_int32_t
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dwlpx_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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CFGREAD(b, s, f, r, LONG);
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}
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static void
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dwlpx_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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CFGWRITE(b, s, f, r, data, BYTE);
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}
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static void
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dwlpx_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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CFGWRITE(b, s, f, r, data, WORD);
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}
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static void
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dwlpx_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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CFGWRITE(b, s, f, r, data, LONG);
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}
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static int dwlpx_probe(device_t dev);
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static int dwlpx_attach(device_t dev);
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static driver_intr_t dwlpx_intr;
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static device_method_t dwlpx_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, dwlpx_probe),
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DEVMETHOD(device_attach, dwlpx_attach),
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{ 0, 0 }
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};
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static driver_t dwlpx_driver = {
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"dwlpx",
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dwlpx_methods,
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DRIVER_TYPE_MISC,
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sizeof(struct dwlpx_softc),
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};
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static int
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dwlpx_probe(device_t dev)
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{
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if (dwlpx0)
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return ENXIO;
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dwlpx0 = dev;
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device_set_desc(dev, "DWLPA or DWLPB PCI adapter");
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return 0;
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}
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static int
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dwlpx_attach(device_t dev)
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{
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struct dwlpx_softc* sc = DWLPX_SOFTC(dev);
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device_t parent = device_get_parent(dev);
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vm_offset_t regs;
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dwlpx0 = dev;
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chipset = dwlpx_chipset;
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chipset.intrdev = dev;
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regs = KV(DWLPX_BASE(kft_get_node(dev), kft_get_hosenum(dev)));
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sc->dmem_base = regs + (0L << 32);
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sc->smem_base = regs + (1L << 32);
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sc->io_base = regs + (2L << 32);
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sc->cfg_base = regs + (3L << 32);
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*(u_int32_t*) (regs + PCIA_CTL(0)) = 1; /* Type1 config cycles */
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BUS_CONNECT_INTR(parent,
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BUS_CREATE_INTR(parent, dev,
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0, dwlpx_intr, 0));
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return 0;
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}
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static void
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dwlpx_intr(void* arg)
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{
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#ifdef SIMOS
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extern void simos_intr(int);
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simos_intr(0);
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#endif
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}
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DRIVER_MODULE(dwlpx, kft, dwlpx_driver, dwlpx_devclass, 0, 0);
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