4edef187b8
I/O windows, the default is to preserve the firmware-assigned resources. PCI bus numbers are only managed if NEW_PCIB is enabled and the architecture defines a PCI_RES_BUS resource type. - Add a helper API to create top-level PCI bus resource managers for each PCI domain/segment. Host-PCI bridge drivers use this API to allocate bus numbers from their associated domain. - Change the PCI bus and CardBus drivers to allocate a bus resource for their bus number from the parent PCI bridge device. - Change the PCI-PCI and PCI-CardBus bridge drivers to allocate the full range of bus numbers from secbus to subbus from their parent bridge. The drivers also always program their primary bus register. The bridge drivers also support growing their bus range by extending the bus resource and updating subbus to match the larger range. - Add support for managing PCI bus resources to the Host-PCI bridge drivers used for amd64 and i386 (acpi_pcib, mptable_pcib, legacy_pcib, and qpi_pcib). - Define a PCI_RES_BUS resource type for amd64 and i386. Reviewed by: imp MFC after: 1 month
172 lines
6.4 KiB
C
172 lines
6.4 KiB
C
/*-
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* Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier
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* Copyright (c) 2000 Michael Smith <msmith@freebsd.org>
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* Copyright (c) 2000 BSDi
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __PCIB_PRIVATE_H__
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#define __PCIB_PRIVATE_H__
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#ifdef NEW_PCIB
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/*
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* Data structure and routines that Host to PCI bridge drivers can use
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* to restrict allocations for child devices to ranges decoded by the
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* bridge.
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*/
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struct pcib_host_resources {
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device_t hr_pcib;
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struct resource_list hr_rl;
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};
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int pcib_host_res_init(device_t pcib,
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struct pcib_host_resources *hr);
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int pcib_host_res_free(device_t pcib,
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struct pcib_host_resources *hr);
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int pcib_host_res_decodes(struct pcib_host_resources *hr, int type,
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u_long start, u_long end, u_int flags);
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struct resource *pcib_host_res_alloc(struct pcib_host_resources *hr,
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device_t dev, int type, int *rid, u_long start, u_long end,
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u_long count, u_int flags);
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int pcib_host_res_adjust(struct pcib_host_resources *hr,
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device_t dev, int type, struct resource *r, u_long start,
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u_long end);
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#endif
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/*
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* Export portions of generic PCI:PCI bridge support so that it can be
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* used by subclasses.
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*/
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DECLARE_CLASS(pcib_driver);
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#ifdef NEW_PCIB
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#define WIN_IO 0x1
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#define WIN_MEM 0x2
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#define WIN_PMEM 0x4
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struct pcib_window {
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pci_addr_t base; /* base address */
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pci_addr_t limit; /* topmost address */
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struct rman rman;
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struct resource **res;
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int count; /* size of 'res' array */
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int reg; /* resource id from parent */
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int valid;
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int mask; /* WIN_* bitmask of this window */
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int step; /* log_2 of window granularity */
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const char *name;
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};
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#endif
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struct pcib_secbus {
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u_int sec;
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u_int sub;
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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device_t dev;
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struct rman rman;
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struct resource *res;
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const char *name;
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int sub_reg;
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#endif
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};
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/*
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* Bridge-specific data.
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*/
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struct pcib_softc
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{
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device_t dev;
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uint32_t flags; /* flags */
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#define PCIB_SUBTRACTIVE 0x1
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#define PCIB_DISABLE_MSI 0x2
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#define PCIB_DISABLE_MSIX 0x4
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uint16_t command; /* command register */
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u_int domain; /* domain number */
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u_int pribus; /* primary bus number */
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struct pcib_secbus bus; /* secondary bus numbers */
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#ifdef NEW_PCIB
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struct pcib_window io; /* I/O port window */
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struct pcib_window mem; /* memory window */
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struct pcib_window pmem; /* prefetchable memory window */
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#else
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pci_addr_t pmembase; /* base address of prefetchable memory */
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pci_addr_t pmemlimit; /* topmost address of prefetchable memory */
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pci_addr_t membase; /* base address of memory window */
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pci_addr_t memlimit; /* topmost address of memory window */
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uint32_t iobase; /* base address of port window */
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uint32_t iolimit; /* topmost address of port window */
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#endif
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uint16_t secstat; /* secondary bus status register */
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uint16_t bridgectl; /* bridge control register */
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uint8_t seclat; /* secondary bus latency timer */
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};
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typedef uint32_t pci_read_config_fn(int b, int s, int f, int reg, int width);
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int host_pcib_get_busno(pci_read_config_fn read_config, int bus,
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int slot, int func, uint8_t *busnum);
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#if defined(NEW_PCIB) && defined(PCI_RES_BUS)
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struct resource *pci_domain_alloc_bus(int domain, device_t dev, int *rid,
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u_long start, u_long end, u_long count, u_int flags);
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int pci_domain_adjust_bus(int domain, device_t dev,
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struct resource *r, u_long start, u_long end);
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int pci_domain_release_bus(int domain, device_t dev, int rid,
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struct resource *r);
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struct resource *pcib_alloc_subbus(struct pcib_secbus *bus, device_t child,
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int *rid, u_long start, u_long end, u_long count,
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u_int flags);
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void pcib_setup_secbus(device_t dev, struct pcib_secbus *bus,
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int min_count);
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#endif
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int pcib_attach(device_t dev);
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void pcib_attach_common(device_t dev);
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#ifdef NEW_PCIB
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const char *pcib_child_name(device_t child);
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#endif
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int pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result);
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int pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value);
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struct resource *pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
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u_long start, u_long end, u_long count, u_int flags);
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#ifdef NEW_PCIB
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int pcib_adjust_resource(device_t bus, device_t child, int type,
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struct resource *r, u_long start, u_long end);
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int pcib_release_resource(device_t dev, device_t child, int type, int rid,
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struct resource *r);
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#endif
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int pcib_maxslots(device_t dev);
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uint32_t pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width);
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void pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width);
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int pcib_route_interrupt(device_t pcib, device_t dev, int pin);
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int pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs);
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int pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs);
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int pcib_alloc_msix(device_t pcib, device_t dev, int *irq);
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int pcib_release_msix(device_t pcib, device_t dev, int irq);
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int pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, uint32_t *data);
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#endif
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