028480bfb1
- Attempt to handle PCI devices where the interrupt is an ISA/EISA interrupt according to the mp table. - Attempt to handle multiple IO APIC pins connected to the same PCI or ISA/EISA interrupt source. Print a warning if this happens, since performance is suboptimal. This workaround is only used for PCI devices. With these two workarounds, the -SMP kernel is capable of running on my Asus P/I-P65UP5 motherboard when version 1.4 of the MP table is disabled.
613 lines
15 KiB
C
613 lines
15 KiB
C
/*
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* Copyright (c) 1997, Stefan Esser <se@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice unmodified, this list of conditions, and the following
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* disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: pci.c,v 1.81 1998/01/24 02:54:47 eivind Exp $
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*
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*/
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#include "pci.h"
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#if NPCI > 0
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#include "opt_devfs.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/malloc.h>
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#include <sys/fcntl.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#ifdef DEVFS
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#include <sys/devfsext.h>
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#endif /* DEVFS */
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <pci/pci_ioctl.h>
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#ifdef APIC_IO
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#include <machine/smp.h>
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#endif /* APIC_IO */
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/* return highest PCI bus number known to be used, or -1 if none */
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static int
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pci_bushigh(void)
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{
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if (pci_cfgopen() == 0)
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return (-1);
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return (0);
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}
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/* return base address of memory or port map */
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static int
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pci_mapbase(unsigned mapreg)
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{
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int mask = 0x03;
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if ((mapreg & 0x01) == 0)
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mask = 0x0f;
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return (mapreg & ~mask);
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}
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/* return map type of memory or port map */
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static int
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pci_maptype(unsigned mapreg)
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{
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static u_int8_t maptype[0x10] = {
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PCI_MAPMEM, PCI_MAPPORT,
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PCI_MAPMEM, 0,
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PCI_MAPMEM, PCI_MAPPORT,
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0, 0,
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PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
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PCI_MAPMEM|PCI_MAPMEMP, 0,
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PCI_MAPMEM|PCI_MAPMEMP, PCI_MAPPORT,
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0, 0,
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};
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return maptype[mapreg & 0x0f];
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}
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/* return log2 of map size decoded for memory or port map */
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static int
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pci_mapsize(unsigned testval)
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{
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int ln2size;
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testval = pci_mapbase(testval);
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ln2size = 0;
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if (testval != 0) {
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while ((testval & 1) == 0)
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{
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ln2size++;
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testval >>= 1;
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}
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}
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return (ln2size);
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}
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/* return log2 of address range supported by map register */
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static int
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pci_maprange(unsigned mapreg)
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{
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int ln2range = 0;
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switch (mapreg & 0x07) {
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case 0x00:
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case 0x01:
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case 0x05:
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ln2range = 32;
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break;
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case 0x02:
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ln2range = 20;
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break;
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case 0x04:
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ln2range = 64;
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break;
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}
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return (ln2range);
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}
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/* extract map parameters into newly allocated array of pcimap structures */
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static pcimap *
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pci_readmaps(pcicfgregs *cfg, int maxmaps)
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{
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int i;
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pcimap *map;
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int map64 = 0;
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for (i = 0; i < maxmaps; i++) {
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int reg = PCIR_MAPS + i*4;
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u_int32_t base;
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u_int32_t ln2range;
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base = pci_cfgread(cfg, reg, 4);
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ln2range = pci_maprange(base);
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if (base == 0 || ln2range == 0)
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maxmaps = i;
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else if (ln2range > 32)
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i++;
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}
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map = malloc(maxmaps * sizeof (pcimap), M_DEVBUF, M_WAITOK);
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if (map != NULL) {
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bzero(map, sizeof(pcimap) * maxmaps);
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for (i = 0; i < maxmaps; i++) {
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int reg = PCIR_MAPS + i*4;
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u_int32_t base;
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u_int32_t testval;
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base = pci_cfgread(cfg, reg, 4);
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if (map64 == 0) {
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pci_cfgwrite(cfg, reg, 0xffffffff, 4);
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testval = pci_cfgread(cfg, reg, 4);
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pci_cfgwrite(cfg, reg, base, 4);
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map[i].base = pci_mapbase(base);
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map[i].type = pci_maptype(base);
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map[i].ln2size = pci_mapsize(testval);
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map[i].ln2range = pci_maprange(testval);
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map64 = map[i].ln2range == 64;
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} else {
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/* only fill in base, other fields are 0 */
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map[i].base = base;
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map64 = 0;
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}
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}
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cfg->nummaps = maxmaps;
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}
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return (map);
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}
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/* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
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static void
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pci_fixancient(pcicfgregs *cfg)
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{
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if (cfg->hdrtype != 0)
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return;
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/* PCI to PCI bridges use header type 1 */
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if (cfg->class == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
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cfg->hdrtype = 1;
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}
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/* read config data specific to header type 1 device (PCI to PCI bridge) */
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static void *
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pci_readppb(pcicfgregs *cfg)
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{
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pcih1cfgregs *p;
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p = malloc(sizeof (pcih1cfgregs), M_DEVBUF, M_WAITOK);
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if (p == NULL)
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return (NULL);
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bzero(p, sizeof *p);
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p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_1, 2);
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p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_1, 2);
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p->seclat = pci_cfgread(cfg, PCIR_SECLAT_1, 1);
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p->iobase = PCI_PPBIOBASE (pci_cfgread(cfg, PCIR_IOBASEH_1, 2),
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pci_cfgread(cfg, PCIR_IOBASEL_1, 1));
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p->iolimit = PCI_PPBIOLIMIT (pci_cfgread(cfg, PCIR_IOLIMITH_1, 2),
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pci_cfgread(cfg, PCIR_IOLIMITL_1, 1));
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p->membase = PCI_PPBMEMBASE (0,
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pci_cfgread(cfg, PCIR_MEMBASE_1, 2));
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p->memlimit = PCI_PPBMEMLIMIT (0,
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pci_cfgread(cfg, PCIR_MEMLIMIT_1, 2));
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p->pmembase = PCI_PPBMEMBASE (
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(pci_addr_t)pci_cfgread(cfg, PCIR_PMBASEH_1, 4),
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pci_cfgread(cfg, PCIR_PMBASEL_1, 2));
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p->pmemlimit = PCI_PPBMEMLIMIT (
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(pci_addr_t)pci_cfgread(cfg, PCIR_PMLIMITH_1, 4),
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pci_cfgread(cfg, PCIR_PMLIMITL_1, 2));
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return (p);
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}
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/* read config data specific to header type 2 device (PCI to CardBus bridge) */
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static void *
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pci_readpcb(pcicfgregs *cfg)
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{
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pcih2cfgregs *p;
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p = malloc(sizeof (pcih2cfgregs), M_DEVBUF, M_WAITOK);
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if (p == NULL)
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return (NULL);
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bzero(p, sizeof *p);
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p->secstat = pci_cfgread(cfg, PCIR_SECSTAT_2, 2);
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p->bridgectl = pci_cfgread(cfg, PCIR_BRIDGECTL_2, 2);
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p->seclat = pci_cfgread(cfg, PCIR_SECLAT_2, 1);
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p->membase0 = pci_cfgread(cfg, PCIR_MEMBASE0_2, 4);
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p->memlimit0 = pci_cfgread(cfg, PCIR_MEMLIMIT0_2, 4);
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p->membase1 = pci_cfgread(cfg, PCIR_MEMBASE1_2, 4);
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p->memlimit1 = pci_cfgread(cfg, PCIR_MEMLIMIT1_2, 4);
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p->iobase0 = pci_cfgread(cfg, PCIR_IOBASE0_2, 4);
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p->iolimit0 = pci_cfgread(cfg, PCIR_IOLIMIT0_2, 4);
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p->iobase1 = pci_cfgread(cfg, PCIR_IOBASE1_2, 4);
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p->iolimit1 = pci_cfgread(cfg, PCIR_IOLIMIT1_2, 4);
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p->pccardif = pci_cfgread(cfg, PCIR_PCCARDIF_2, 4);
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return p;
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}
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/* extract header type specific config data */
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static void
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pci_hdrtypedata(pcicfgregs *cfg)
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{
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switch (cfg->hdrtype) {
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case 0:
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cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_0, 2);
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cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_0, 2);
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cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_0);
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break;
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case 1:
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cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_1, 2);
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cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_1, 2);
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cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_1, 1);
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cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_1, 1);
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cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_1);
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cfg->hdrspec = pci_readppb(cfg);
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break;
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case 2:
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cfg->subvendor = pci_cfgread(cfg, PCIR_SUBVEND_2, 2);
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cfg->subdevice = pci_cfgread(cfg, PCIR_SUBDEV_2, 2);
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cfg->secondarybus = pci_cfgread(cfg, PCIR_SECBUS_2, 1);
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cfg->subordinatebus = pci_cfgread(cfg, PCIR_SUBBUS_2, 1);
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cfg->map = pci_readmaps(cfg, PCI_MAXMAPS_2);
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cfg->hdrspec = pci_readpcb(cfg);
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break;
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}
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}
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/* read configuration header into pcicfgrect structure */
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static pcicfgregs *
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pci_readcfg(pcicfgregs *probe)
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{
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pcicfgregs *cfg = NULL;
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if (pci_cfgread(probe, PCIR_DEVVENDOR, 4) != -1) {
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cfg = malloc(sizeof (pcicfgregs), M_DEVBUF, M_WAITOK);
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if (cfg == NULL)
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return (cfg);
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bzero(cfg, sizeof *cfg);
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cfg->bus = probe->bus;
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cfg->slot = probe->slot;
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cfg->func = probe->func;
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cfg->parent = probe->parent;
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cfg->vendor = pci_cfgread(cfg, PCIR_VENDOR, 2);
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cfg->device = pci_cfgread(cfg, PCIR_DEVICE, 2);
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cfg->cmdreg = pci_cfgread(cfg, PCIR_COMMAND, 2);
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cfg->statreg = pci_cfgread(cfg, PCIR_STATUS, 2);
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cfg->class = pci_cfgread(cfg, PCIR_CLASS, 1);
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cfg->subclass = pci_cfgread(cfg, PCIR_SUBCLASS, 1);
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cfg->progif = pci_cfgread(cfg, PCIR_PROGIF, 1);
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cfg->revid = pci_cfgread(cfg, PCIR_REVID, 1);
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cfg->hdrtype = pci_cfgread(cfg, PCIR_HEADERTYPE, 1);
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cfg->cachelnsz = pci_cfgread(cfg, PCIR_CACHELNSZ, 1);
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cfg->lattimer = pci_cfgread(cfg, PCIR_LATTIMER, 1);
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cfg->intpin = pci_cfgread(cfg, PCIR_INTPIN, 1);
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cfg->intline = pci_cfgread(cfg, PCIR_INTLINE, 1);
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#ifdef APIC_IO
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if (cfg->intpin != 0) {
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int airq;
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airq = pci_apic_pin(cfg->bus, cfg->slot, cfg->intpin);
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if (airq >= 0) {
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/* PCI specific entry found in MP table */
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if (airq != cfg->intline) {
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undirect_pci_irq(cfg->intline);
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cfg->intline = airq;
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}
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} else {
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/*
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* PCI interrupts might be redirected to the
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* ISA bus according to some MP tables. Use the
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* same methods as used by the ISA devices
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* devices to find the proper IOAPIC int pin.
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*/
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airq = isa_apic_pin(cfg->intline);
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if ((airq >= 0) && (airq != cfg->intline)) {
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/* XXX: undirect_pci_irq() ? */
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undirect_isa_irq(cfg->intline);
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cfg->intline = airq;
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}
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}
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}
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#endif /* APIC_IO */
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cfg->mingnt = pci_cfgread(cfg, PCIR_MINGNT, 1);
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cfg->maxlat = pci_cfgread(cfg, PCIR_MAXLAT, 1);
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cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
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cfg->hdrtype &= ~PCIM_MFDEV;
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pci_fixancient(cfg);
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pci_hdrtypedata(cfg);
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}
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return (cfg);
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}
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#if 0
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/* free pcicfgregs structure and all depending data structures */
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static int
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pci_freecfg(pcicfgregs *cfg)
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{
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if (cfg->hdrspec != NULL)
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free(cfg->hdrspec, M_DEVBUF);
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if (cfg->map != NULL)
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free(cfg->map, M_DEVBUF);
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free(cfg, M_DEVBUF);
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return (0);
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}
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#endif
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static void
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pci_addcfg(pcicfgregs *cfg)
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{
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if (bootverbose) {
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int i;
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printf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
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cfg->vendor, cfg->device, cfg->revid);
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printf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
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cfg->class, cfg->subclass, cfg->progif, cfg->hdrtype, cfg->mfdev);
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#ifdef PCI_DEBUG
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printf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
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cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
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printf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
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cfg->lattimer, cfg->lattimer * 30,
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cfg->mingnt, cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
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#endif /* PCI_DEBUG */
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if (cfg->intpin > 0)
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printf("\tintpin=%c, irq=%d\n", cfg->intpin +'a' -1, cfg->intline);
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for (i = 0; i < cfg->nummaps; i++) {
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pcimap *m = &cfg->map[i];
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printf("\tmap[%d]: type %x, range %2d, base %08x, size %2d\n",
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i, m->type, m->ln2range, m->base, m->ln2size);
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}
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}
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pci_drvattach(cfg); /* XXX currently defined in pci_compat.c */
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}
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/* return pointer to device that is a bridge to this bus */
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static pcicfgregs *
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pci_bridgeto(int bus)
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{
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return (NULL); /* XXX not yet implemented */
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}
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/* scan one PCI bus for devices */
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static int
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pci_probebus(int bus)
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{
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pcicfgregs probe;
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int bushigh = bus;
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bzero(&probe, sizeof probe);
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probe.parent = pci_bridgeto(bus);
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probe.bus = bus;
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for (probe.slot = 0; probe.slot <= PCI_SLOTMAX; probe.slot++) {
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int pcifunchigh = 0;
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for (probe.func = 0; probe.func <= pcifunchigh; probe.func++) {
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pcicfgregs *cfg = pci_readcfg(&probe);
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if (cfg != NULL) {
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if (cfg->mfdev)
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pcifunchigh = 7;
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/*
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* XXX: Temporarily move pci_addcfg() up before
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* the use of cfg->subordinatebus. This is
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* necessary, since pci_addcfg() calls the
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* device's probe(), which may read the bus#
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* from some device dependent register of
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* some host to PCI bridges. The probe will
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* eventually be moved to pci_readcfg(), and
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* pci_addcfg() will then be moved back down
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* below the conditional statement ...
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*/
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pci_addcfg(cfg);
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if (bushigh < cfg->subordinatebus)
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bushigh = cfg->subordinatebus;
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cfg = NULL; /* we don't own this anymore ... */
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}
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}
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}
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return (bushigh);
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}
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/* scan a PCI bus tree reached through one PCI attachment point */
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int
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pci_probe(pciattach *parent)
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{
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int bushigh;
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int bus = 0;
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bushigh = pci_bushigh();
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while (bus <= bushigh) {
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int newbushigh;
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printf("Probing for devices on PCI bus %d:\n", bus);
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newbushigh = pci_probebus(bus);
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if (bushigh < newbushigh)
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|
bushigh = newbushigh;
|
|
bus++;
|
|
}
|
|
return (bushigh);
|
|
}
|
|
|
|
/*
|
|
* This is the user interface to PCI configuration space.
|
|
*/
|
|
|
|
static int
|
|
pci_open(dev_t dev, int oflags, int devtype, struct proc *p)
|
|
{
|
|
if ((oflags & FWRITE) && securelevel > 0) {
|
|
return EPERM;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
pci_close(dev_t dev, int flag, int devtype, struct proc *p)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
pci_ioctl(dev_t dev, int cmd, caddr_t data, int flag, struct proc *p)
|
|
{
|
|
struct pci_io *io;
|
|
int error;
|
|
|
|
if (cmd != PCIOCGETCONF && !(flag & FWRITE))
|
|
return EPERM;
|
|
|
|
switch(cmd) {
|
|
case PCIOCGETCONF:
|
|
#ifdef NOTYET
|
|
static struct pci_conf *pci_dev_list;
|
|
static unsigned pci_dev_list_count;
|
|
static unsigned pci_dev_list_size;
|
|
|
|
cio = (struct pci_conf_io *)data;
|
|
iolen = min(cio->pci_len,
|
|
pci_dev_list_count * sizeof(struct pci_conf));
|
|
cio->pci_len = pci_dev_list_count * sizeof(struct pci_conf);
|
|
|
|
error = copyout(pci_dev_list, cio->pci_buf, iolen);
|
|
#else
|
|
error = ENODEV;
|
|
#endif
|
|
break;
|
|
|
|
case PCIOCREAD:
|
|
io = (struct pci_io *)data;
|
|
switch(io->pi_width) {
|
|
pcicfgregs probe;
|
|
case 4:
|
|
case 2:
|
|
case 1:
|
|
probe.bus = io->pi_sel.pc_bus;
|
|
probe.slot = io->pi_sel.pc_dev;
|
|
probe.func = io->pi_sel.pc_func;
|
|
io->pi_data = pci_cfgread(&probe,
|
|
io->pi_reg, io->pi_width);
|
|
error = 0;
|
|
break;
|
|
default:
|
|
error = ENODEV;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
case PCIOCWRITE:
|
|
io = (struct pci_io *)data;
|
|
switch(io->pi_width) {
|
|
pcicfgregs probe;
|
|
case 4:
|
|
case 2:
|
|
case 1:
|
|
probe.bus = io->pi_sel.pc_bus;
|
|
probe.slot = io->pi_sel.pc_dev;
|
|
probe.func = io->pi_sel.pc_func;
|
|
pci_cfgwrite(&probe,
|
|
io->pi_reg, io->pi_data, io->pi_width);
|
|
error = 0;
|
|
break;
|
|
default:
|
|
error = ENODEV;
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default:
|
|
error = ENOTTY;
|
|
break;
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
#define PCI_CDEV 78
|
|
|
|
static struct cdevsw pcicdev = {
|
|
pci_open, pci_close, noread, nowrite, pci_ioctl, nostop, noreset,
|
|
nodevtotty, seltrue, nommap, nostrategy, "pci", 0, PCI_CDEV
|
|
};
|
|
|
|
#ifdef DEVFS
|
|
static void *pci_devfs_token;
|
|
#endif
|
|
|
|
static void
|
|
pci_cdevinit(void *dummy)
|
|
{
|
|
dev_t dev;
|
|
|
|
dev = makedev(PCI_CDEV, 0);
|
|
cdevsw_add(&dev, &pcicdev, NULL);
|
|
#ifdef DEVFS
|
|
pci_devfs_token = devfs_add_devswf(&pcicdev, 0, DV_CHR,
|
|
UID_ROOT, GID_WHEEL, 0644, "pci");
|
|
#endif
|
|
}
|
|
|
|
SYSINIT(pcidev, SI_SUB_DRIVERS, SI_ORDER_MIDDLE+PCI_CDEV, pci_cdevinit, NULL);
|
|
|
|
#endif /* NPCI > 0 */
|