104 lines
3.5 KiB
C
104 lines
3.5 KiB
C
/*-
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* Copyright (c) 1999 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* from: NetBSD: ofw_pci.h,v 1.5 2003/10/22 09:04:39 mjl Exp
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*
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* $FreeBSD$
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*/
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#ifndef _DEV_OFW_OFW_PCI_H_
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#define _DEV_OFW_OFW_PCI_H_
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/*
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* PCI Bus Binding to:
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*
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* IEEE Std 1275-1994
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* Standard for Boot (Initialization Configuration) Firmware
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*
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* Revision 2.1
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*/
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/*
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* Section 2.2.1. Physical Address Formats
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*
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* A PCI physical address is represented by 3 address cells:
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*
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* phys.hi cell: npt000ss bbbbbbbb dddddfff rrrrrrrr
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* phys.mid cell: hhhhhhhh hhhhhhhh hhhhhhhh hhhhhhhh
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* phys.lo cell: llllllll llllllll llllllll llllllll
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*
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* n nonrelocatable
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* p prefetchable
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* t aliased below 1MB (memory) or 64k (i/o)
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* ss space code
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* b bus number
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* d device number
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* f function number
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* r register number
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* h high 32-bits of PCI address
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* l low 32-bits of PCI address
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*/
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#define OFW_PCI_PHYS_HI_NONRELOCATABLE 0x80000000
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#define OFW_PCI_PHYS_HI_PREFETCHABLE 0x40000000
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#define OFW_PCI_PHYS_HI_ALIASED 0x20000000
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#define OFW_PCI_PHYS_HI_SPACEMASK 0x03000000
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#define OFW_PCI_PHYS_HI_BUSMASK 0x00ff0000
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#define OFW_PCI_PHYS_HI_BUSSHIFT 16
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#define OFW_PCI_PHYS_HI_DEVICEMASK 0x0000f800
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#define OFW_PCI_PHYS_HI_DEVICESHIFT 11
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#define OFW_PCI_PHYS_HI_FUNCTIONMASK 0x00000700
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#define OFW_PCI_PHYS_HI_FUNCTIONSHIFT 8
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#define OFW_PCI_PHYS_HI_REGISTERMASK 0x000000ff
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#define OFW_PCI_PHYS_HI_SPACE_CONFIG 0x00000000
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#define OFW_PCI_PHYS_HI_SPACE_IO 0x01000000
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#define OFW_PCI_PHYS_HI_SPACE_MEM32 0x02000000
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#define OFW_PCI_PHYS_HI_SPACE_MEM64 0x03000000
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#define OFW_PCI_PHYS_HI_BUS(hi) \
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(((hi) & OFW_PCI_PHYS_HI_BUSMASK) >> OFW_PCI_PHYS_HI_BUSSHIFT)
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#define OFW_PCI_PHYS_HI_DEVICE(hi) \
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(((hi) & OFW_PCI_PHYS_HI_DEVICEMASK) >> OFW_PCI_PHYS_HI_DEVICESHIFT)
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#define OFW_PCI_PHYS_HI_FUNCTION(hi) \
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(((hi) & OFW_PCI_PHYS_HI_FUNCTIONMASK) >> OFW_PCI_PHYS_HI_FUNCTIONSHIFT)
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/*
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* This has the 3 32bit cell values, plus 2 more to make up a 64-bit size.
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*/
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struct ofw_pci_register {
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u_int32_t phys_hi;
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u_int32_t phys_mid;
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u_int32_t phys_lo;
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u_int32_t size_hi;
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u_int32_t size_lo;
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};
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#endif /* _DEV_OFW_OFW_PCI_H_ */
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