354 lines
11 KiB
C
354 lines
11 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_ata.h"
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_ali_chipinit(device_t dev);
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static int ata_ali_chipdeinit(device_t dev);
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static int ata_ali_ch_attach(device_t dev);
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static int ata_ali_sata_ch_attach(device_t dev);
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static void ata_ali_reset(device_t dev);
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static int ata_ali_setmode(device_t dev, int target, int mode);
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/* misc defines */
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#define ALI_OLD 0x01
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#define ALI_NEW 0x02
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#define ALI_SATA 0x04
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struct ali_sata_resources {
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struct resource *bars[4];
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};
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/*
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* Acer Labs Inc (ALI) chipset support functions
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*/
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static int
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ata_ali_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static const struct ata_chip_id const ids[] =
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{{ ATA_ALI_5289, 0x00, 2, ALI_SATA, ATA_SA150, "M5289" },
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{ ATA_ALI_5288, 0x00, 4, ALI_SATA, ATA_SA300, "M5288" },
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{ ATA_ALI_5287, 0x00, 4, ALI_SATA, ATA_SA150, "M5287" },
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{ ATA_ALI_5281, 0x00, 2, ALI_SATA, ATA_SA150, "M5281" },
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{ ATA_ALI_5228, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5228" },
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{ ATA_ALI_5229, 0xc5, 0, ALI_NEW, ATA_UDMA6, "M5229" },
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{ ATA_ALI_5229, 0xc4, 0, ALI_NEW, ATA_UDMA5, "M5229" },
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{ ATA_ALI_5229, 0xc2, 0, ALI_NEW, ATA_UDMA4, "M5229" },
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{ ATA_ALI_5229, 0x20, 0, ALI_OLD, ATA_UDMA2, "M5229" },
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{ ATA_ALI_5229, 0x00, 0, ALI_OLD, ATA_WDMA2, "M5229" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_ACER_LABS_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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ctlr->chipinit = ata_ali_chipinit;
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ctlr->chipdeinit = ata_ali_chipdeinit;
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return (BUS_PROBE_DEFAULT);
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}
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static int
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ata_ali_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ali_sata_resources *res;
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int i, rid;
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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switch (ctlr->chip->cfg2) {
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case ALI_SATA:
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ctlr->channels = ctlr->chip->cfg1;
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ctlr->ch_attach = ata_ali_sata_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->setmode = ata_sata_setmode;
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ctlr->getrev = ata_sata_getrev;
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/* AHCI mode is correctly supported only on the ALi 5288. */
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if ((ctlr->chip->chipid == ATA_ALI_5288) &&
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(ata_ahci_chipinit(dev) != ENXIO))
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return 0;
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/* Allocate resources for later use by channel attach routines. */
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res = malloc(sizeof(struct ali_sata_resources), M_ATAPCI, M_WAITOK);
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for (i = 0; i < 4; i++) {
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rid = PCIR_BAR(i);
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res->bars[i] = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
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RF_ACTIVE);
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if (res->bars[i] == NULL) {
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device_printf(dev, "Failed to allocate BAR %d\n", i);
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for (i--; i >=0; i--)
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bus_release_resource(dev, SYS_RES_IOPORT,
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PCIR_BAR(i), res->bars[i]);
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free(res, M_TEMP);
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return ENXIO;
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}
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}
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ctlr->chipset_data = res;
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break;
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case ALI_NEW:
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/* use device interrupt as byte count end */
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pci_write_config(dev, 0x4a, pci_read_config(dev, 0x4a, 1) | 0x20, 1);
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/* enable cable detection and UDMA support on revisions < 0xc7 */
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if (ctlr->chip->chiprev < 0xc7)
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pci_write_config(dev, 0x4b, pci_read_config(dev, 0x4b, 1) |
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0x09, 1);
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/* enable ATAPI UDMA mode (even if we are going to do PIO) */
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pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) |
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(ctlr->chip->chiprev >= 0xc7 ? 0x03 : 0x01), 1);
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/* only chips with revision > 0xc4 can do 48bit DMA */
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if (ctlr->chip->chiprev <= 0xc4)
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device_printf(dev,
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"using PIO transfers above 137GB as workaround for "
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"48bit DMA access bug, expect reduced performance\n");
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ctlr->ch_attach = ata_ali_ch_attach;
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ctlr->ch_detach = ata_pci_ch_detach;
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ctlr->reset = ata_ali_reset;
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ctlr->setmode = ata_ali_setmode;
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break;
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case ALI_OLD:
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/* deactivate the ATAPI FIFO and enable ATAPI UDMA */
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pci_write_config(dev, 0x53, pci_read_config(dev, 0x53, 1) | 0x03, 1);
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ctlr->setmode = ata_ali_setmode;
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break;
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}
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return 0;
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}
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static int
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ata_ali_chipdeinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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struct ali_sata_resources *res;
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int i;
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if (ctlr->chip->cfg2 == ALI_SATA) {
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res = ctlr->chipset_data;
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for (i = 0; i < 4; i++) {
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if (res->bars[i] != NULL) {
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bus_release_resource(dev, SYS_RES_IOPORT,
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PCIR_BAR(i), res->bars[i]);
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}
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}
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free(res, M_ATAPCI);
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ctlr->chipset_data = NULL;
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}
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return (0);
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}
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static int
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ata_ali_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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/* setup the usual register normal pci style */
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if (ata_pci_ch_attach(dev))
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return ENXIO;
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if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7)
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ch->flags |= ATA_CHECKS_CABLE;
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/* older chips can't do 48bit DMA transfers */
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if (ctlr->chip->chiprev <= 0xc4) {
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ch->flags |= ATA_NO_48BIT_DMA;
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if (ch->dma.max_iosize > 256 * 512)
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ch->dma.max_iosize = 256 * 512;
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}
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#ifdef ATA_CAM
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if (ctlr->chip->cfg2 & ALI_NEW)
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ch->flags |= ATA_NO_ATAPI_DMA;
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#endif
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return 0;
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}
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static int
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ata_ali_sata_ch_attach(device_t dev)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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struct ali_sata_resources *res;
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struct resource *io = NULL, *ctlio = NULL;
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int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
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int i;
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res = ctlr->chipset_data;
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if (unit01) {
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io = res->bars[2];
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ctlio = res->bars[3];
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} else {
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io = res->bars[0];
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ctlio = res->bars[1];
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}
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ata_pci_dmainit(dev);
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for (i = ATA_DATA; i <= ATA_COMMAND; i ++) {
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ch->r_io[i].res = io;
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ch->r_io[i].offset = i + (unit10 ? 8 : 0);
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}
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ch->r_io[ATA_CONTROL].res = ctlio;
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ch->r_io[ATA_CONTROL].offset = 2 + (unit10 ? 4 : 0);
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ch->r_io[ATA_IDX_ADDR].res = io;
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ata_default_registers(dev);
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if (ctlr->r_res1) {
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for (i = ATA_BMCMD_PORT; i <= ATA_BMDTP_PORT; i++) {
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ch->r_io[i].res = ctlr->r_res1;
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ch->r_io[i].offset = (i - ATA_BMCMD_PORT)+(ch->unit * ATA_BMIOSIZE);
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}
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}
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ch->flags |= ATA_NO_SLAVE;
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ch->flags |= ATA_SATA;
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/* XXX SOS PHY handling awkward in ALI chip not supported yet */
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ata_pci_hw(dev);
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return 0;
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}
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static void
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ata_ali_reset(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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device_t *children;
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int nchildren, i;
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ata_generic_reset(dev);
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/*
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* workaround for datacorruption bug found on at least SUN Blade-100
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* find the ISA function on the southbridge and disable then enable
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* the ATA channel tristate buffer
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*/
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if (ctlr->chip->chiprev == 0xc3 || ctlr->chip->chiprev == 0xc2) {
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if (!device_get_children(GRANDPARENT(dev), &children, &nchildren)) {
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for (i = 0; i < nchildren; i++) {
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if (pci_get_devid(children[i]) == ATA_ALI_1533) {
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pci_write_config(children[i], 0x58,
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pci_read_config(children[i], 0x58, 1) &
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~(0x04 << ch->unit), 1);
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pci_write_config(children[i], 0x58,
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pci_read_config(children[i], 0x58, 1) |
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(0x04 << ch->unit), 1);
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break;
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}
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}
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free(children, M_TEMP);
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}
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}
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}
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static int
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ata_ali_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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int piomode;
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static const uint32_t piotimings[] =
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{ 0x006d0003, 0x00580002, 0x00440001, 0x00330001,
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0x00310001, 0x006d0003, 0x00330001, 0x00310001 };
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static const uint8_t udma[] = {0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x0f,
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0x0d};
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uint32_t word54;
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mode = min(mode, ctlr->chip->max_dma);
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if (ctlr->chip->cfg2 & ALI_NEW && ctlr->chip->chiprev < 0xc7) {
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if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
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pci_read_config(parent, 0x4a, 1) & (1 << ch->unit)) {
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ata_print_cable(dev, "controller");
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mode = ATA_UDMA2;
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}
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}
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if (ctlr->chip->cfg2 & ALI_OLD) {
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/* doesn't support ATAPI DMA on write */
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ch->flags |= ATA_ATAPI_DMA_RO;
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if (ch->devices & ATA_ATAPI_MASTER &&
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ch->devices & ATA_ATAPI_SLAVE) {
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/* doesn't support ATAPI DMA on two ATAPI devices */
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device_printf(dev, "two atapi devices on this channel,"
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" no DMA\n");
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mode = min(mode, ATA_PIO_MAX);
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}
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}
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/* Set UDMA mode */
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word54 = pci_read_config(parent, 0x54, 4);
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if (mode >= ATA_UDMA0) {
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word54 &= ~(0x000f000f << (devno << 2));
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word54 |= (((udma[mode&ATA_MODE_MASK]<<16)|0x05)<<(devno<<2));
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piomode = ATA_PIO4;
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}
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else {
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word54 &= ~(0x0008000f << (devno << 2));
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piomode = mode;
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}
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pci_write_config(parent, 0x54, word54, 4);
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/* Set PIO/WDMA mode */
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pci_write_config(parent, 0x58 + (ch->unit << 2),
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piotimings[ata_mode2idx(piomode)], 4);
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return (mode);
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}
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ATA_DECLARE_DRIVER(ata_ali);
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MODULE_DEPEND(ata_ali, ata_ahci, 1, 1, 1);
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