301 lines
8.3 KiB
C
301 lines
8.3 KiB
C
/*
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* FreeBSD, PCI product support functions
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*
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* Copyright (c) 1995-2001 Justin T. Gibbs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU Public License ("GPL").
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: ahd_pci.c,v 1.8 2003/05/03 23:27:57 gibbs Exp $
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <dev/aic7xxx/aic79xx_osm.h>
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#define AHD_PCI_IOADDR0 PCIR_BAR(0) /* Primary I/O BAR */
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#define AHD_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
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#define AHD_PCI_IOADDR1 PCIR_BAR(3) /* Secondary I/O BAR */
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static int ahd_pci_probe(device_t dev);
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static int ahd_pci_attach(device_t dev);
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static device_method_t ahd_pci_device_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ahd_pci_probe),
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DEVMETHOD(device_attach, ahd_pci_attach),
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DEVMETHOD(device_detach, ahd_detach),
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{ 0, 0 }
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};
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static driver_t ahd_pci_driver = {
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"ahd",
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ahd_pci_device_methods,
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sizeof(struct ahd_softc)
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};
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static devclass_t ahd_devclass;
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DRIVER_MODULE(ahd, pci, ahd_pci_driver, ahd_devclass, 0, 0);
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DRIVER_MODULE(ahd, cardbus, ahd_pci_driver, ahd_devclass, 0, 0);
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MODULE_DEPEND(ahd_pci, ahd, 1, 1, 1);
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MODULE_VERSION(ahd_pci, 1);
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static int
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ahd_pci_probe(device_t dev)
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{
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struct ahd_pci_identity *entry;
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entry = ahd_find_pci_device(dev);
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if (entry != NULL) {
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device_set_desc(dev, entry->name);
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return (0);
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}
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return (ENXIO);
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}
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static int
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ahd_pci_attach(device_t dev)
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{
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struct ahd_pci_identity *entry;
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struct ahd_softc *ahd;
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char *name;
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int error;
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entry = ahd_find_pci_device(dev);
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if (entry == NULL)
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return (ENXIO);
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/*
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* Allocate a softc for this card and
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* set it up for attachment by our
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* common detect routine.
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*/
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name = malloc(strlen(device_get_nameunit(dev)) + 1, M_DEVBUF, M_NOWAIT);
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if (name == NULL)
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return (ENOMEM);
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strcpy(name, device_get_nameunit(dev));
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ahd = ahd_alloc(dev, name);
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if (ahd == NULL)
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return (ENOMEM);
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ahd_set_unit(ahd, device_get_unit(dev));
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/*
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* Should we bother disabling 39Bit addressing
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* based on installed memory?
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*/
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if (sizeof(bus_addr_t) > 4)
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ahd->flags |= AHD_39BIT_ADDRESSING;
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/* Allocate a dmatag for our SCB DMA maps */
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/* XXX Should be a child of the PCI bus dma tag */
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error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/1,
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/*boundary*/0,
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(ahd->flags & AHD_39BIT_ADDRESSING)
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? 0x7FFFFFFFFFLL
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: BUS_SPACE_MAXADDR_32BIT,
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/*highaddr*/BUS_SPACE_MAXADDR,
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/*filter*/NULL, /*filterarg*/NULL,
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/*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
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/*nsegments*/AHD_NSEG,
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/*maxsegsz*/AHD_MAXTRANSFER_SIZE,
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/*flags*/0,
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/*lockfunc*/busdma_lock_mutex,
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/*lockarg*/&Giant,
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&ahd->parent_dmat);
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if (error != 0) {
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printf("ahd_pci_attach: Could not allocate DMA tag "
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"- error %d\n", error);
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ahd_free(ahd);
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return (ENOMEM);
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}
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ahd->dev_softc = dev;
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error = ahd_pci_config(ahd, entry);
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if (error != 0) {
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ahd_free(ahd);
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return (error);
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}
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ahd_attach(ahd);
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return (0);
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}
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int
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ahd_pci_map_registers(struct ahd_softc *ahd)
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{
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struct resource *regs;
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struct resource *regs2;
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u_int command;
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int regs_type;
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int regs_id;
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int regs_id2;
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int allow_memio;
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command = ahd_pci_read_config(ahd->dev_softc, PCIR_COMMAND, /*bytes*/1);
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regs = NULL;
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regs2 = NULL;
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regs_type = 0;
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regs_id = 0;
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/* Retrieve the per-device 'allow_memio' hint */
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if (resource_int_value(device_get_name(ahd->dev_softc),
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device_get_unit(ahd->dev_softc),
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"allow_memio", &allow_memio) != 0) {
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if (bootverbose)
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device_printf(ahd->dev_softc,
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"Defaulting to MEMIO on\n");
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}
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if ((command & PCIM_CMD_MEMEN) != 0
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&& (ahd->bugs & AHD_PCIX_MMAPIO_BUG) == 0
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&& allow_memio != 0) {
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regs_type = SYS_RES_MEMORY;
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regs_id = AHD_PCI_MEMADDR;
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regs = bus_alloc_resource(ahd->dev_softc, regs_type,
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®s_id, 0, ~0, 1, RF_ACTIVE);
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if (regs != NULL) {
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int error;
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ahd->tags[0] = rman_get_bustag(regs);
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ahd->bshs[0] = rman_get_bushandle(regs);
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ahd->tags[1] = ahd->tags[0];
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error = bus_space_subregion(ahd->tags[0], ahd->bshs[0],
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/*offset*/0x100,
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/*size*/0x100,
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&ahd->bshs[1]);
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/*
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* Do a quick test to see if memory mapped
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* I/O is functioning correctly.
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*/
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if (error != 0
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|| ahd_pci_test_register_access(ahd) != 0) {
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device_printf(ahd->dev_softc,
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"PCI Device %d:%d:%d failed memory "
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"mapped test. Using PIO.\n",
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ahd_get_pci_bus(ahd->dev_softc),
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ahd_get_pci_slot(ahd->dev_softc),
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ahd_get_pci_function(ahd->dev_softc));
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bus_release_resource(ahd->dev_softc, regs_type,
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regs_id, regs);
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regs = NULL;
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} else {
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command &= ~PCIM_CMD_PORTEN;
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ahd_pci_write_config(ahd->dev_softc,
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PCIR_COMMAND,
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command, /*bytes*/1);
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}
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}
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}
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if (regs == NULL && (command & PCIM_CMD_PORTEN) != 0) {
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regs_type = SYS_RES_IOPORT;
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regs_id = AHD_PCI_IOADDR0;
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regs = bus_alloc_resource(ahd->dev_softc, regs_type,
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®s_id, 0, ~0, 1, RF_ACTIVE);
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if (regs == NULL) {
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device_printf(ahd->dev_softc,
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"can't allocate register resources\n");
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return (ENOMEM);
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}
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ahd->tags[0] = rman_get_bustag(regs);
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ahd->bshs[0] = rman_get_bushandle(regs);
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/* And now the second BAR */
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regs_id2 = AHD_PCI_IOADDR1;
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regs2 = bus_alloc_resource(ahd->dev_softc, regs_type,
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®s_id2, 0, ~0, 1, RF_ACTIVE);
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if (regs2 == NULL) {
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device_printf(ahd->dev_softc,
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"can't allocate register resources\n");
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return (ENOMEM);
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}
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ahd->tags[1] = rman_get_bustag(regs2);
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ahd->bshs[1] = rman_get_bushandle(regs2);
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command &= ~PCIM_CMD_MEMEN;
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ahd_pci_write_config(ahd->dev_softc, PCIR_COMMAND,
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command, /*bytes*/1);
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ahd->platform_data->regs_res_type[1] = regs_type;
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ahd->platform_data->regs_res_id[1] = regs_id2;
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ahd->platform_data->regs[1] = regs2;
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}
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ahd->platform_data->regs_res_type[0] = regs_type;
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ahd->platform_data->regs_res_id[0] = regs_id;
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ahd->platform_data->regs[0] = regs;
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return (0);
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}
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int
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ahd_pci_map_int(struct ahd_softc *ahd)
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{
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int zero;
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zero = 0;
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ahd->platform_data->irq =
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bus_alloc_resource(ahd->dev_softc, SYS_RES_IRQ, &zero,
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0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
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if (ahd->platform_data->irq == NULL)
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return (ENOMEM);
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ahd->platform_data->irq_res_type = SYS_RES_IRQ;
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return (ahd_map_int(ahd));
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}
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void
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ahd_power_state_change(struct ahd_softc *ahd, ahd_power_state new_state)
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{
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uint32_t cap;
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u_int cap_offset;
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/*
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* Traverse the capability list looking for
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* the power management capability.
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*/
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cap = 0;
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cap_offset = ahd_pci_read_config(ahd->dev_softc,
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PCIR_CAP_PTR, /*bytes*/1);
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while (cap_offset != 0) {
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cap = ahd_pci_read_config(ahd->dev_softc,
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cap_offset, /*bytes*/4);
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if ((cap & 0xFF) == 1
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&& ((cap >> 16) & 0x3) > 0) {
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uint32_t pm_control;
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pm_control = ahd_pci_read_config(ahd->dev_softc,
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cap_offset + 4,
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/*bytes*/2);
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pm_control &= ~0x3;
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pm_control |= new_state;
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ahd_pci_write_config(ahd->dev_softc,
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cap_offset + 4,
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pm_control, /*bytes*/2);
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break;
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}
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cap_offset = (cap >> 8) & 0xFF;
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}
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}
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