1277 lines
34 KiB
Plaintext
1277 lines
34 KiB
Plaintext
/*
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* sama5d3.dtsi - Device Tree Include file for SAMA5D3 family SoC
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* applies to SAMA5D31, SAMA5D33, SAMA5D34, SAMA5D35, SAMA5D36 SoC
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*
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* Copyright (C) 2013 Atmel,
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* 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
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*
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* Licensed under GPLv2 or later.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/dma/at91.h>
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#include <dt-bindings/pinctrl/at91.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/clk/at91.h>
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/ {
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model = "Atmel SAMA5D3 family SoC";
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compatible = "atmel,sama5d3", "atmel,sama5";
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interrupt-parent = <&aic>;
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aliases {
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serial0 = &dbgu;
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serial1 = &usart0;
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serial2 = &usart1;
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serial3 = &usart2;
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serial4 = &usart3;
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gpio0 = &pioA;
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gpio1 = &pioB;
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gpio2 = &pioC;
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gpio3 = &pioD;
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gpio4 = &pioE;
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tcb0 = &tcb0;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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ssc0 = &ssc0;
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ssc1 = &ssc1;
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pwm0 = &pwm0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0x0>;
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};
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};
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pmu {
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compatible = "arm,cortex-a5-pmu";
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interrupts = <46 IRQ_TYPE_LEVEL_HIGH 0>;
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};
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memory {
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reg = <0x20000000 0x8000000>;
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};
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clocks {
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adc_op_clk: adc_op_clk{
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <20000000>;
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};
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};
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ahb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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mmc0: mmc@f0000000 {
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compatible = "atmel,hsmci";
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reg = <0xf0000000 0x600>;
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interrupts = <21 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(0)>;
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dma-names = "rxtx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3 &pinctrl_mmc0_dat4_7>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mci0_clk>;
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clock-names = "mci_clk";
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};
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spi0: spi@f0004000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,at91rm9200-spi";
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reg = <0xf0004000 0x100>;
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interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
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dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(1)>,
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<&dma0 2 AT91_DMA_CFG_PER_ID(2)>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi0>;
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clocks = <&spi0_clk>;
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clock-names = "spi_clk";
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status = "disabled";
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};
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ssc0: ssc@f0008000 {
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compatible = "atmel,at91sam9g45-ssc";
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reg = <0xf0008000 0x4000>;
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interrupts = <38 IRQ_TYPE_LEVEL_HIGH 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
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clocks = <&ssc0_clk>;
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clock-names = "pclk";
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status = "disabled";
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};
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tcb0: timer@f0010000 {
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compatible = "atmel,at91sam9x5-tcb";
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reg = <0xf0010000 0x100>;
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interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&tcb0_clk>;
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clock-names = "t0_clk";
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};
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i2c0: i2c@f0014000 {
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compatible = "atmel,at91sam9x5-i2c";
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reg = <0xf0014000 0x4000>;
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interrupts = <18 IRQ_TYPE_LEVEL_HIGH 6>;
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dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(7)>,
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<&dma0 2 AT91_DMA_CFG_PER_ID(8)>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&twi0_clk>;
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status = "disabled";
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};
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i2c1: i2c@f0018000 {
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compatible = "atmel,at91sam9x5-i2c";
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reg = <0xf0018000 0x4000>;
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interrupts = <19 IRQ_TYPE_LEVEL_HIGH 6>;
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dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(9)>,
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<&dma0 2 AT91_DMA_CFG_PER_ID(10)>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&twi1_clk>;
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status = "disabled";
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};
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usart0: serial@f001c000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf001c000 0x100>;
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interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usart0>;
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clocks = <&usart0_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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usart1: serial@f0020000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf0020000 0x100>;
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interrupts = <13 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usart1>;
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clocks = <&usart1_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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pwm0: pwm@f002c000 {
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compatible = "atmel,sama5d3-pwm";
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reg = <0xf002c000 0x300>;
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interrupts = <28 IRQ_TYPE_LEVEL_HIGH 4>;
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#pwm-cells = <3>;
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clocks = <&pwm_clk>;
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status = "disabled";
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};
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isi: isi@f0034000 {
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compatible = "atmel,at91sam9g45-isi";
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reg = <0xf0034000 0x4000>;
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interrupts = <37 IRQ_TYPE_LEVEL_HIGH 5>;
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status = "disabled";
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};
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mmc1: mmc@f8000000 {
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compatible = "atmel,hsmci";
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reg = <0xf8000000 0x600>;
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interrupts = <22 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(0)>;
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dma-names = "rxtx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_mmc1_clk_cmd_dat0 &pinctrl_mmc1_dat1_3>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&mci1_clk>;
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clock-names = "mci_clk";
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};
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spi1: spi@f8008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "atmel,at91rm9200-spi";
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reg = <0xf8008000 0x100>;
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interrupts = <25 IRQ_TYPE_LEVEL_HIGH 3>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(15)>,
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<&dma1 2 AT91_DMA_CFG_PER_ID(16)>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi1>;
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clocks = <&spi1_clk>;
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clock-names = "spi_clk";
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status = "disabled";
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};
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ssc1: ssc@f800c000 {
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compatible = "atmel,at91sam9g45-ssc";
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reg = <0xf800c000 0x4000>;
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interrupts = <39 IRQ_TYPE_LEVEL_HIGH 4>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
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clocks = <&ssc1_clk>;
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clock-names = "pclk";
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status = "disabled";
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};
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adc0: adc@f8018000 {
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compatible = "atmel,at91sam9260-adc";
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reg = <0xf8018000 0x100>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <
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&pinctrl_adc0_adtrg
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&pinctrl_adc0_ad0
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&pinctrl_adc0_ad1
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&pinctrl_adc0_ad2
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&pinctrl_adc0_ad3
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&pinctrl_adc0_ad4
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&pinctrl_adc0_ad5
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&pinctrl_adc0_ad6
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&pinctrl_adc0_ad7
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&pinctrl_adc0_ad8
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&pinctrl_adc0_ad9
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&pinctrl_adc0_ad10
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&pinctrl_adc0_ad11
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>;
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clocks = <&adc_clk>,
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<&adc_op_clk>;
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clock-names = "adc_clk", "adc_op_clk";
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atmel,adc-channel-base = <0x50>;
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atmel,adc-channels-used = <0xfff>;
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atmel,adc-drdy-mask = <0x1000000>;
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atmel,adc-num-channels = <12>;
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atmel,adc-startup-time = <40>;
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atmel,adc-status-register = <0x30>;
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atmel,adc-trigger-register = <0xc0>;
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atmel,adc-use-external;
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atmel,adc-vref = <3000>;
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atmel,adc-res = <10 12>;
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atmel,adc-res-names = "lowres", "highres";
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status = "disabled";
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trigger@0 {
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trigger-name = "external-rising";
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trigger-value = <0x1>;
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trigger-external;
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};
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trigger@1 {
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trigger-name = "external-falling";
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trigger-value = <0x2>;
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trigger-external;
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};
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trigger@2 {
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trigger-name = "external-any";
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trigger-value = <0x3>;
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trigger-external;
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};
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trigger@3 {
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trigger-name = "continuous";
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trigger-value = <0x6>;
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};
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};
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tsadcc: tsadcc@f8018000 {
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compatible = "atmel,at91sam9x5-tsadcc";
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reg = <0xf8018000 0x4000>;
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interrupts = <29 IRQ_TYPE_LEVEL_HIGH 5>;
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atmel,tsadcc_clock = <300000>;
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atmel,filtering_average = <0x03>;
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atmel,pendet_debounce = <0x08>;
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atmel,pendet_sensitivity = <0x02>;
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atmel,ts_sample_hold_time = <0x0a>;
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status = "disabled";
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};
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i2c2: i2c@f801c000 {
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compatible = "atmel,at91sam9x5-i2c";
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reg = <0xf801c000 0x4000>;
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interrupts = <20 IRQ_TYPE_LEVEL_HIGH 6>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(11)>,
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<&dma1 2 AT91_DMA_CFG_PER_ID(12)>;
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dma-names = "tx", "rx";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&twi2_clk>;
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status = "disabled";
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};
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usart2: serial@f8020000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8020000 0x100>;
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interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usart2>;
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clocks = <&usart2_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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usart3: serial@f8024000 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xf8024000 0x100>;
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interrupts = <15 IRQ_TYPE_LEVEL_HIGH 5>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_usart3>;
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clocks = <&usart3_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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sha@f8034000 {
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compatible = "atmel,at91sam9g46-sha";
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reg = <0xf8034000 0x100>;
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interrupts = <42 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(17)>;
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dma-names = "tx";
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clocks = <&sha_clk>;
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clock-names = "sha_clk";
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};
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aes@f8038000 {
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compatible = "atmel,at91sam9g46-aes";
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reg = <0xf8038000 0x100>;
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interrupts = <43 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(18)>,
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<&dma1 2 AT91_DMA_CFG_PER_ID(19)>;
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dma-names = "tx", "rx";
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clocks = <&aes_clk>;
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clock-names = "aes_clk";
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};
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tdes@f803c000 {
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compatible = "atmel,at91sam9g46-tdes";
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reg = <0xf803c000 0x100>;
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interrupts = <44 IRQ_TYPE_LEVEL_HIGH 0>;
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dmas = <&dma1 2 AT91_DMA_CFG_PER_ID(20)>,
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<&dma1 2 AT91_DMA_CFG_PER_ID(21)>;
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dma-names = "tx", "rx";
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clocks = <&tdes_clk>;
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clock-names = "tdes_clk";
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};
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dma0: dma-controller@ffffe600 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffe600 0x200>;
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interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <2>;
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clocks = <&dma0_clk>;
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clock-names = "dma_clk";
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};
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dma1: dma-controller@ffffe800 {
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compatible = "atmel,at91sam9g45-dma";
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reg = <0xffffe800 0x200>;
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interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
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#dma-cells = <2>;
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clocks = <&dma1_clk>;
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clock-names = "dma_clk";
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};
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ramc0: ramc@ffffea00 {
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compatible = "atmel,at91sam9g45-ddramc";
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reg = <0xffffea00 0x200>;
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};
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dbgu: serial@ffffee00 {
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compatible = "atmel,at91sam9260-usart";
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reg = <0xffffee00 0x200>;
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interrupts = <2 IRQ_TYPE_LEVEL_HIGH 7>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dbgu>;
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clocks = <&dbgu_clk>;
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clock-names = "usart";
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status = "disabled";
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};
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aic: interrupt-controller@fffff000 {
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#interrupt-cells = <3>;
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compatible = "atmel,sama5d3-aic";
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interrupt-controller;
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reg = <0xfffff000 0x200>;
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atmel,external-irqs = <47>;
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};
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pinctrl@fffff200 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "atmel,at91sam9x5-pinctrl", "atmel,at91rm9200-pinctrl", "simple-bus";
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ranges = <0xfffff200 0xfffff200 0xa00>;
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atmel,mux-mask = <
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/* A B C */
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0xffffffff 0xc0fc0000 0xc0ff0000 /* pioA */
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0xffffffff 0x0ff8ffff 0x00000000 /* pioB */
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0xffffffff 0xbc00f1ff 0x7c00fc00 /* pioC */
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0xffffffff 0xc001c0e0 0x0001c1e0 /* pioD */
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0xffffffff 0xbf9f8000 0x18000000 /* pioE */
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>;
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/* shared pinctrl settings */
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adc0 {
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pinctrl_adc0_adtrg: adc0_adtrg {
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atmel,pins =
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<AT91_PIOD 19 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD19 periph A ADTRG */
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};
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pinctrl_adc0_ad0: adc0_ad0 {
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atmel,pins =
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<AT91_PIOD 20 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD20 periph A AD0 */
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};
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pinctrl_adc0_ad1: adc0_ad1 {
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atmel,pins =
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<AT91_PIOD 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD21 periph A AD1 */
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};
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pinctrl_adc0_ad2: adc0_ad2 {
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atmel,pins =
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<AT91_PIOD 22 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD22 periph A AD2 */
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};
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pinctrl_adc0_ad3: adc0_ad3 {
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atmel,pins =
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<AT91_PIOD 23 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD23 periph A AD3 */
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};
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pinctrl_adc0_ad4: adc0_ad4 {
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atmel,pins =
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<AT91_PIOD 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD24 periph A AD4 */
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};
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pinctrl_adc0_ad5: adc0_ad5 {
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atmel,pins =
|
|
<AT91_PIOD 25 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD25 periph A AD5 */
|
|
};
|
|
pinctrl_adc0_ad6: adc0_ad6 {
|
|
atmel,pins =
|
|
<AT91_PIOD 26 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD26 periph A AD6 */
|
|
};
|
|
pinctrl_adc0_ad7: adc0_ad7 {
|
|
atmel,pins =
|
|
<AT91_PIOD 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD27 periph A AD7 */
|
|
};
|
|
pinctrl_adc0_ad8: adc0_ad8 {
|
|
atmel,pins =
|
|
<AT91_PIOD 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD28 periph A AD8 */
|
|
};
|
|
pinctrl_adc0_ad9: adc0_ad9 {
|
|
atmel,pins =
|
|
<AT91_PIOD 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD29 periph A AD9 */
|
|
};
|
|
pinctrl_adc0_ad10: adc0_ad10 {
|
|
atmel,pins =
|
|
<AT91_PIOD 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD30 periph A AD10, conflicts with PCK0 */
|
|
};
|
|
pinctrl_adc0_ad11: adc0_ad11 {
|
|
atmel,pins =
|
|
<AT91_PIOD 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD31 periph A AD11, conflicts with PCK1 */
|
|
};
|
|
};
|
|
|
|
dbgu {
|
|
pinctrl_dbgu: dbgu-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB30 periph A */
|
|
AT91_PIOB 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB31 periph A with pullup */
|
|
};
|
|
};
|
|
|
|
i2c0 {
|
|
pinctrl_i2c0: i2c0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PA30 periph A TWD0 pin, conflicts with URXD1, ISI_VSYNC */
|
|
AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA31 periph A TWCK0 pin, conflicts with UTXD1, ISI_HSYNC */
|
|
};
|
|
};
|
|
|
|
i2c1 {
|
|
pinctrl_i2c1: i2c1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 26 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC26 periph B TWD1 pin, conflicts with SPI1_NPCS1, ISI_D11 */
|
|
AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PC27 periph B TWCK1 pin, conflicts with SPI1_NPCS2, ISI_D10 */
|
|
};
|
|
};
|
|
|
|
i2c2 {
|
|
pinctrl_i2c2: i2c2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* TWD2 pin, conflicts with LCDDAT18, ISI_D2 */
|
|
AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* TWCK2 pin, conflicts with LCDDAT19, ISI_D3 */
|
|
};
|
|
};
|
|
|
|
isi {
|
|
pinctrl_isi: isi-0 {
|
|
atmel,pins =
|
|
<AT91_PIOA 16 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA16 periph C ISI_D0, conflicts with LCDDAT16 */
|
|
AT91_PIOA 17 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA17 periph C ISI_D1, conflicts with LCDDAT17 */
|
|
AT91_PIOA 18 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA18 periph C ISI_D2, conflicts with LCDDAT18, TWD2 */
|
|
AT91_PIOA 19 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA19 periph C ISI_D3, conflicts with LCDDAT19, TWCK2 */
|
|
AT91_PIOA 20 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA20 periph C ISI_D4, conflicts with LCDDAT20, PWMH0 */
|
|
AT91_PIOA 21 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA21 periph C ISI_D5, conflicts with LCDDAT21, PWML0 */
|
|
AT91_PIOA 22 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA22 periph C ISI_D6, conflicts with LCDDAT22, PWMH1 */
|
|
AT91_PIOA 23 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA23 periph C ISI_D7, conflicts with LCDDAT23, PWML1 */
|
|
AT91_PIOC 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC30 periph C ISI_PCK, conflicts with UTXD0 */
|
|
AT91_PIOA 31 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA31 periph C ISI_HSYNC, conflicts with TWCK0, UTXD1 */
|
|
AT91_PIOA 30 AT91_PERIPH_C AT91_PINCTRL_NONE /* PA30 periph C ISI_VSYNC, conflicts with TWD0, URXD1 */
|
|
AT91_PIOC 29 AT91_PERIPH_C AT91_PINCTRL_NONE /* PC29 periph C ISI_PD8, conflicts with URXD0, PWMFI2 */
|
|
AT91_PIOC 28 AT91_PERIPH_C AT91_PINCTRL_NONE>; /* PC28 periph C ISI_PD9, conflicts with SPI1_NPCS3, PWMFI0 */
|
|
};
|
|
pinctrl_isi_pck_as_mck: isi_pck_as_mck-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 31 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD31 periph B ISI_MCK */
|
|
};
|
|
};
|
|
|
|
mmc0 {
|
|
pinctrl_mmc0_clk_cmd_dat0: mmc0_clk_cmd_dat0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD9 periph A MCI0_CK */
|
|
AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A MCI0_CDA with pullup */
|
|
AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD1 periph A MCI0_DA0 with pullup */
|
|
};
|
|
pinctrl_mmc0_dat1_3: mmc0_dat1_3 {
|
|
atmel,pins =
|
|
<AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A MCI0_DA1 with pullup */
|
|
AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD3 periph A MCI0_DA2 with pullup */
|
|
AT91_PIOD 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD4 periph A MCI0_DA3 with pullup */
|
|
};
|
|
pinctrl_mmc0_dat4_7: mmc0_dat4_7 {
|
|
atmel,pins =
|
|
<AT91_PIOD 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD5 periph A MCI0_DA4 with pullup, conflicts with TIOA0, PWMH2 */
|
|
AT91_PIOD 6 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD6 periph A MCI0_DA5 with pullup, conflicts with TIOB0, PWML2 */
|
|
AT91_PIOD 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD7 periph A MCI0_DA6 with pullup, conlicts with TCLK0, PWMH3 */
|
|
AT91_PIOD 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD8 periph A MCI0_DA7 with pullup, conflicts with PWML3 */
|
|
};
|
|
};
|
|
|
|
mmc1 {
|
|
pinctrl_mmc1_clk_cmd_dat0: mmc1_clk_cmd_dat0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB24 periph A MCI1_CK, conflicts with GRX5 */
|
|
AT91_PIOB 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB19 periph A MCI1_CDA with pullup, conflicts with GTX4 */
|
|
AT91_PIOB 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB20 periph A MCI1_DA0 with pullup, conflicts with GTX5 */
|
|
};
|
|
pinctrl_mmc1_dat1_3: mmc1_dat1_3 {
|
|
atmel,pins =
|
|
<AT91_PIOB 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB21 periph A MCI1_DA1 with pullup, conflicts with GTX6 */
|
|
AT91_PIOB 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PB22 periph A MCI1_DA2 with pullup, conflicts with GTX7 */
|
|
AT91_PIOB 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB23 periph A MCI1_DA3 with pullup, conflicts with GRX4 */
|
|
};
|
|
};
|
|
|
|
nand0 {
|
|
pinctrl_nand0_ale_cle: nand0_ale_cle-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PE21 periph A with pullup */
|
|
AT91_PIOE 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PE22 periph A with pullup */
|
|
};
|
|
};
|
|
|
|
spi0 {
|
|
pinctrl_spi0: spi0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD10 periph A SPI0_MISO pin */
|
|
AT91_PIOD 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD11 periph A SPI0_MOSI pin */
|
|
AT91_PIOD 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD12 periph A SPI0_SPCK pin */
|
|
};
|
|
};
|
|
|
|
spi1 {
|
|
pinctrl_spi1: spi1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A SPI1_MISO pin */
|
|
AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A SPI1_MOSI pin */
|
|
AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC24 periph A SPI1_SPCK pin */
|
|
};
|
|
};
|
|
|
|
ssc0 {
|
|
pinctrl_ssc0_tx: ssc0_tx {
|
|
atmel,pins =
|
|
<AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A TK0 */
|
|
AT91_PIOC 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC17 periph A TF0 */
|
|
AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC18 periph A TD0 */
|
|
};
|
|
|
|
pinctrl_ssc0_rx: ssc0_rx {
|
|
atmel,pins =
|
|
<AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A RK0 */
|
|
AT91_PIOC 20 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC20 periph A RF0 */
|
|
AT91_PIOC 21 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC21 periph A RD0 */
|
|
};
|
|
};
|
|
|
|
ssc1 {
|
|
pinctrl_ssc1_tx: ssc1_tx {
|
|
atmel,pins =
|
|
<AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB2 periph B TK1, conflicts with GTX2 */
|
|
AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B TF1, conflicts with GTX3 */
|
|
AT91_PIOB 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB6 periph B TD1, conflicts with TD1 */
|
|
};
|
|
|
|
pinctrl_ssc1_rx: ssc1_rx {
|
|
atmel,pins =
|
|
<AT91_PIOB 7 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB7 periph B RK1, conflicts with EREFCK */
|
|
AT91_PIOB 10 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB10 periph B RF1, conflicts with GTXER */
|
|
AT91_PIOB 11 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB11 periph B RD1, conflicts with GRXCK */
|
|
};
|
|
};
|
|
|
|
usart0 {
|
|
pinctrl_usart0: usart0-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 17 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD17 periph A */
|
|
AT91_PIOD 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PD18 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_usart0_rts_cts: usart0_rts_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOD 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PD15 periph A, conflicts with SPI0_NPCS2, CANTX0 */
|
|
AT91_PIOD 16 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD16 periph A, conflicts with SPI0_NPCS3, PWMFI3 */
|
|
};
|
|
};
|
|
|
|
usart1 {
|
|
pinctrl_usart1: usart1-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB28 periph A */
|
|
AT91_PIOB 29 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PB29 periph A with pullup */
|
|
};
|
|
|
|
pinctrl_usart1_rts_cts: usart1_rts_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOB 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB26 periph A, conflicts with GRX7 */
|
|
AT91_PIOB 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB27 periph A, conflicts with G125CKO */
|
|
};
|
|
};
|
|
|
|
usart2 {
|
|
pinctrl_usart2: usart2-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE25 periph B, conflicts with A25 */
|
|
AT91_PIOE 26 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE26 periph B with pullup, conflicts NCS0 */
|
|
};
|
|
|
|
pinctrl_usart2_rts_cts: usart2_rts_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE23 periph B, conflicts with A23 */
|
|
AT91_PIOE 24 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE24 periph B, conflicts with A24 */
|
|
};
|
|
};
|
|
|
|
usart3 {
|
|
pinctrl_usart3: usart3-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE18 periph B, conflicts with A18 */
|
|
AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>; /* PE19 periph B with pullup, conflicts with A19 */
|
|
};
|
|
|
|
pinctrl_usart3_rts_cts: usart3_rts_cts-0 {
|
|
atmel,pins =
|
|
<AT91_PIOE 16 AT91_PERIPH_B AT91_PINCTRL_NONE /* PE16 periph B, conflicts with A16 */
|
|
AT91_PIOE 17 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE17 periph B, conflicts with A17 */
|
|
};
|
|
};
|
|
|
|
|
|
pioA: gpio@fffff200 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff200 0x100>;
|
|
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioA_clk>;
|
|
};
|
|
|
|
pioB: gpio@fffff400 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff400 0x100>;
|
|
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioB_clk>;
|
|
};
|
|
|
|
pioC: gpio@fffff600 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff600 0x100>;
|
|
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioC_clk>;
|
|
};
|
|
|
|
pioD: gpio@fffff800 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffff800 0x100>;
|
|
interrupts = <9 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioD_clk>;
|
|
};
|
|
|
|
pioE: gpio@fffffa00 {
|
|
compatible = "atmel,at91sam9x5-gpio", "atmel,at91rm9200-gpio";
|
|
reg = <0xfffffa00 0x100>;
|
|
interrupts = <10 IRQ_TYPE_LEVEL_HIGH 1>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
clocks = <&pioE_clk>;
|
|
};
|
|
};
|
|
|
|
pmc: pmc@fffffc00 {
|
|
compatible = "atmel,sama5d3-pmc";
|
|
reg = <0xfffffc00 0x120>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
interrupt-controller;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
|
|
clk32k: slck {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
main: mainck {
|
|
compatible = "atmel,at91rm9200-clk-main";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_MOSCS>;
|
|
clocks = <&clk32k>;
|
|
};
|
|
|
|
plla: pllack {
|
|
compatible = "atmel,sama5d3-clk-pll";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_LOCKA>;
|
|
clocks = <&main>;
|
|
reg = <0>;
|
|
atmel,clk-input-range = <8000000 50000000>;
|
|
#atmel,pll-clk-output-range-cells = <4>;
|
|
atmel,pll-clk-output-ranges = <400000000 1000000000 0 0>;
|
|
};
|
|
|
|
plladiv: plladivck {
|
|
compatible = "atmel,at91sam9x5-clk-plldiv";
|
|
#clock-cells = <0>;
|
|
clocks = <&plla>;
|
|
};
|
|
|
|
utmi: utmick {
|
|
compatible = "atmel,at91sam9x5-clk-utmi";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_LOCKU>;
|
|
clocks = <&main>;
|
|
};
|
|
|
|
mck: masterck {
|
|
compatible = "atmel,at91sam9x5-clk-master";
|
|
#clock-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
interrupts = <AT91_PMC_MCKRDY>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
|
|
atmel,clk-output-range = <0 166000000>;
|
|
atmel,clk-divisors = <1 2 4 3>;
|
|
};
|
|
|
|
usb: usbck {
|
|
compatible = "atmel,at91sam9x5-clk-usb";
|
|
#clock-cells = <0>;
|
|
clocks = <&plladiv>, <&utmi>;
|
|
};
|
|
|
|
prog: progck {
|
|
compatible = "atmel,at91sam9x5-clk-programmable";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
interrupt-parent = <&pmc>;
|
|
clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
|
|
|
|
prog0: prog0 {
|
|
#clock-cells = <0>;
|
|
reg = <0>;
|
|
interrupts = <AT91_PMC_PCKRDY(0)>;
|
|
};
|
|
|
|
prog1: prog1 {
|
|
#clock-cells = <0>;
|
|
reg = <1>;
|
|
interrupts = <AT91_PMC_PCKRDY(1)>;
|
|
};
|
|
|
|
prog2: prog2 {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
interrupts = <AT91_PMC_PCKRDY(2)>;
|
|
};
|
|
};
|
|
|
|
smd: smdclk {
|
|
compatible = "atmel,at91sam9x5-clk-smd";
|
|
#clock-cells = <0>;
|
|
clocks = <&plladiv>, <&utmi>;
|
|
};
|
|
|
|
systemck {
|
|
compatible = "atmel,at91rm9200-clk-system";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
ddrck: ddrck {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
smdck: smdck {
|
|
#clock-cells = <0>;
|
|
reg = <4>;
|
|
clocks = <&smd>;
|
|
};
|
|
|
|
uhpck: uhpck {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
udpck: udpck {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
clocks = <&usb>;
|
|
};
|
|
|
|
pck0: pck0 {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
clocks = <&prog0>;
|
|
};
|
|
|
|
pck1: pck1 {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
clocks = <&prog1>;
|
|
};
|
|
|
|
pck2: pck2 {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
clocks = <&prog2>;
|
|
};
|
|
};
|
|
|
|
periphck {
|
|
compatible = "atmel,at91sam9x5-clk-peripheral";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
clocks = <&mck>;
|
|
|
|
dbgu_clk: dbgu_clk {
|
|
#clock-cells = <0>;
|
|
reg = <2>;
|
|
};
|
|
|
|
pioA_clk: pioA_clk {
|
|
#clock-cells = <0>;
|
|
reg = <6>;
|
|
};
|
|
|
|
pioB_clk: pioB_clk {
|
|
#clock-cells = <0>;
|
|
reg = <7>;
|
|
};
|
|
|
|
pioC_clk: pioC_clk {
|
|
#clock-cells = <0>;
|
|
reg = <8>;
|
|
};
|
|
|
|
pioD_clk: pioD_clk {
|
|
#clock-cells = <0>;
|
|
reg = <9>;
|
|
};
|
|
|
|
pioE_clk: pioE_clk {
|
|
#clock-cells = <0>;
|
|
reg = <10>;
|
|
};
|
|
|
|
usart0_clk: usart0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <12>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
usart1_clk: usart1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <13>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
usart2_clk: usart2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <14>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
usart3_clk: usart3_clk {
|
|
#clock-cells = <0>;
|
|
reg = <15>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
twi0_clk: twi0_clk {
|
|
reg = <18>;
|
|
#clock-cells = <0>;
|
|
atmel,clk-output-range = <0 16625000>;
|
|
};
|
|
|
|
twi1_clk: twi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <19>;
|
|
atmel,clk-output-range = <0 16625000>;
|
|
};
|
|
|
|
twi2_clk: twi2_clk {
|
|
#clock-cells = <0>;
|
|
reg = <20>;
|
|
atmel,clk-output-range = <0 16625000>;
|
|
};
|
|
|
|
mci0_clk: mci0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <21>;
|
|
};
|
|
|
|
mci1_clk: mci1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <22>;
|
|
};
|
|
|
|
spi0_clk: spi0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <24>;
|
|
atmel,clk-output-range = <0 133000000>;
|
|
};
|
|
|
|
spi1_clk: spi1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <25>;
|
|
atmel,clk-output-range = <0 133000000>;
|
|
};
|
|
|
|
tcb0_clk: tcb0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <26>;
|
|
atmel,clk-output-range = <0 133000000>;
|
|
};
|
|
|
|
pwm_clk: pwm_clk {
|
|
#clock-cells = <0>;
|
|
reg = <28>;
|
|
};
|
|
|
|
adc_clk: adc_clk {
|
|
#clock-cells = <0>;
|
|
reg = <29>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
dma0_clk: dma0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <30>;
|
|
};
|
|
|
|
dma1_clk: dma1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <31>;
|
|
};
|
|
|
|
uhphs_clk: uhphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <32>;
|
|
};
|
|
|
|
udphs_clk: udphs_clk {
|
|
#clock-cells = <0>;
|
|
reg = <33>;
|
|
};
|
|
|
|
isi_clk: isi_clk {
|
|
#clock-cells = <0>;
|
|
reg = <37>;
|
|
};
|
|
|
|
ssc0_clk: ssc0_clk {
|
|
#clock-cells = <0>;
|
|
reg = <38>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
ssc1_clk: ssc1_clk {
|
|
#clock-cells = <0>;
|
|
reg = <39>;
|
|
atmel,clk-output-range = <0 66000000>;
|
|
};
|
|
|
|
sha_clk: sha_clk {
|
|
#clock-cells = <0>;
|
|
reg = <42>;
|
|
};
|
|
|
|
aes_clk: aes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <43>;
|
|
};
|
|
|
|
tdes_clk: tdes_clk {
|
|
#clock-cells = <0>;
|
|
reg = <44>;
|
|
};
|
|
|
|
trng_clk: trng_clk {
|
|
#clock-cells = <0>;
|
|
reg = <45>;
|
|
};
|
|
|
|
fuse_clk: fuse_clk {
|
|
#clock-cells = <0>;
|
|
reg = <48>;
|
|
};
|
|
};
|
|
};
|
|
|
|
rstc@fffffe00 {
|
|
compatible = "atmel,at91sam9g45-rstc";
|
|
reg = <0xfffffe00 0x10>;
|
|
};
|
|
|
|
pit: timer@fffffe30 {
|
|
compatible = "atmel,at91sam9260-pit";
|
|
reg = <0xfffffe30 0xf>;
|
|
interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
|
|
clocks = <&mck>;
|
|
};
|
|
|
|
watchdog@fffffe40 {
|
|
compatible = "atmel,at91sam9260-wdt";
|
|
reg = <0xfffffe40 0x10>;
|
|
interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
atmel,watchdog-type = "hardware";
|
|
atmel,reset-type = "all";
|
|
atmel,dbg-halt;
|
|
atmel,idle-halt;
|
|
status = "disabled";
|
|
};
|
|
|
|
rtc@fffffeb0 {
|
|
compatible = "atmel,at91rm9200-rtc";
|
|
reg = <0xfffffeb0 0x30>;
|
|
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
|
|
};
|
|
};
|
|
|
|
usb0: gadget@00500000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "atmel,at91sam9rl-udc";
|
|
reg = <0x00500000 0x100000
|
|
0xf8030000 0x4000>;
|
|
interrupts = <33 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&udphs_clk>, <&utmi>;
|
|
clock-names = "pclk", "hclk";
|
|
status = "disabled";
|
|
|
|
ep0 {
|
|
reg = <0>;
|
|
atmel,fifo-size = <64>;
|
|
atmel,nb-banks = <1>;
|
|
};
|
|
|
|
ep1 {
|
|
reg = <1>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <3>;
|
|
atmel,can-dma;
|
|
atmel,can-isoc;
|
|
};
|
|
|
|
ep2 {
|
|
reg = <2>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <3>;
|
|
atmel,can-dma;
|
|
atmel,can-isoc;
|
|
};
|
|
|
|
ep3 {
|
|
reg = <3>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep4 {
|
|
reg = <4>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep5 {
|
|
reg = <5>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep6 {
|
|
reg = <6>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep7 {
|
|
reg = <7>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
atmel,can-dma;
|
|
};
|
|
|
|
ep8 {
|
|
reg = <8>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep9 {
|
|
reg = <9>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep10 {
|
|
reg = <10>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep11 {
|
|
reg = <11>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep12 {
|
|
reg = <12>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep13 {
|
|
reg = <13>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep14 {
|
|
reg = <14>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
|
|
ep15 {
|
|
reg = <15>;
|
|
atmel,fifo-size = <1024>;
|
|
atmel,nb-banks = <2>;
|
|
};
|
|
};
|
|
|
|
usb1: ohci@00600000 {
|
|
compatible = "atmel,at91rm9200-ohci", "usb-ohci";
|
|
reg = <0x00600000 0x100000>;
|
|
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&usb>, <&uhphs_clk>, <&uhphs_clk>,
|
|
<&uhpck>;
|
|
clock-names = "usb_clk", "ohci_clk", "hclk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2: ehci@00700000 {
|
|
compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
|
|
reg = <0x00700000 0x100000>;
|
|
interrupts = <32 IRQ_TYPE_LEVEL_HIGH 2>;
|
|
clocks = <&usb>, <&uhphs_clk>, <&uhpck>;
|
|
clock-names = "usb_clk", "ehci_clk", "uhpck";
|
|
status = "disabled";
|
|
};
|
|
|
|
nand0: nand@60000000 {
|
|
compatible = "atmel,at91rm9200-nand";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
reg = < 0x60000000 0x01000000 /* EBI CS3 */
|
|
0xffffc070 0x00000490 /* SMC PMECC regs */
|
|
0xffffc500 0x00000100 /* SMC PMECC Error Location regs */
|
|
0x00110000 0x00018000 /* ROM code */
|
|
>;
|
|
interrupts = <5 IRQ_TYPE_LEVEL_HIGH 6>;
|
|
atmel,nand-addr-offset = <21>;
|
|
atmel,nand-cmd-offset = <22>;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_nand0_ale_cle>;
|
|
atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
|
|
status = "disabled";
|
|
|
|
nfc@70000000 {
|
|
compatible = "atmel,sama5d3-nfc";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <
|
|
0x70000000 0x10000000 /* NFC Command Registers */
|
|
0xffffc000 0x00000070 /* NFC HSMC regs */
|
|
0x00200000 0x00100000 /* NFC SRAM banks */
|
|
>;
|
|
};
|
|
};
|
|
};
|
|
};
|