247 lines
7.6 KiB
C
247 lines
7.6 KiB
C
/*-
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* Copyright (c) 1997 Nicolas Souchu
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef __PPCREG_H
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#define __PPCREG_H
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/*
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* Parallel Port Chipset type.
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*/
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#define SMC_LIKE 0
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#define SMC_37C665GT 1
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#define SMC_37C666GT 2
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#define NS_PC87332 3
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#define NS_PC87306 4
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#define INTEL_820191AA 5 /* XXX not implemented */
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#define GENERIC 6
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#define WINB_W83877F 7
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#define WINB_W83877AF 8
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#define WINB_UNKNOWN 9
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#define NS_PC87334 10
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/*
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* Parallel Port Chipset Type. SMC versus GENERIC (others)
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*/
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#define PPC_TYPE_SMCLIKE 0
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#define PPC_TYPE_GENERIC 1
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/*
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* Generic structure to hold parallel port chipset info.
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*/
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struct ppc_data {
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int ppc_unit;
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int ppc_model; /* chipset model if detected */
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int ppc_type; /* generic or smclike chipset type */
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int ppc_mode; /* chipset current mode */
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int ppc_avm; /* chipset available modes */
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#define PPC_IRQ_NONE 0x0
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#define PPC_IRQ_nACK 0x1
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#define PPC_IRQ_DMA 0x2
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#define PPC_IRQ_FIFO 0x4
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#define PPC_IRQ_nFAULT 0x8
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int ppc_irqstat; /* remind irq settings */
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#define PPC_DMA_INIT 0x01
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#define PPC_DMA_STARTED 0x02
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#define PPC_DMA_COMPLETE 0x03
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#define PPC_DMA_INTERRUPTED 0x04
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#define PPC_DMA_ERROR 0x05
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int ppc_dmastat; /* dma state */
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int ppc_dmachan; /* dma channel */
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int ppc_dmaflags; /* dma transfer flags */
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caddr_t ppc_dmaddr; /* buffer address */
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u_int ppc_dmacnt; /* count of bytes sent with dma */
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#define PPC_PWORD_MASK 0x30
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#define PPC_PWORD_16 0x00
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#define PPC_PWORD_8 0x10
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#define PPC_PWORD_32 0x20
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char ppc_pword; /* PWord size */
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short ppc_fifo; /* FIFO threshold */
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short ppc_wthr; /* writeIntrThresold */
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short ppc_rthr; /* readIntrThresold */
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char *ppc_ptr; /* microseq current pointer */
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int ppc_accum; /* microseq accumulator */
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int ppc_base; /* parallel port base address */
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int ppc_epp; /* EPP mode (1.7 or 1.9) */
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int ppc_irq;
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unsigned char ppc_flags;
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device_t ppbus; /* parallel port chipset corresponding ppbus */
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int rid_irq, rid_drq, rid_ioport;
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struct resource *res_irq, *res_drq, *res_ioport;
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void *intr_cookie;
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int ppc_registered; /* 1 if ppcintr() is the registered interrupt */
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};
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/*
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* Parallel Port Chipset registers.
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*/
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#define PPC_SPP_DTR 0 /* SPP data register */
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#define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */
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#define PPC_SPP_STR 1 /* SPP status register */
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#define PPC_SPP_CTR 2 /* SPP control register */
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#define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */
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#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */
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#ifdef PC98
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#define PPC_1284_ENABLE 0x09 /* IEEE STD 1284 Enable register */
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#define PPC_ECP_D_FIFO 0x0c /* ECP Data fifo register */
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#define PPC_ECP_CNFGA 0x0c /* Configuration register A */
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#define PPC_ECP_CNFGB 0x0d /* Configuration register B */
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#define PPC_ECP_ECR 0x0e /* ECP extended control register */
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#else
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#define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */
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#define PPC_ECP_CNFGA 0x400 /* Configuration register A */
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#define PPC_ECP_CNFGB 0x401 /* Configuration register B */
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#define PPC_ECP_ECR 0x402 /* ECP extended control register */
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#endif
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#define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */
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#define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */
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#define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */
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#define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */
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#define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */
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#define PPC_ECR_STD 0x0
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#define PPC_ECR_PS2 0x20
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#define PPC_ECR_FIFO 0x40
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#define PPC_ECR_ECP 0x60
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#define PPC_ECR_EPP 0x80
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#define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR)
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#define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR)
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#define r_dtr(ppc) (inb((ppc)->ppc_base + PPC_SPP_DTR))
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#define r_str(ppc) (inb((ppc)->ppc_base + PPC_SPP_STR))
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#define r_ctr(ppc) (inb((ppc)->ppc_base + PPC_SPP_CTR))
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#define r_epp_A(ppc) (inb((ppc)->ppc_base + PPC_EPP_ADDR))
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#define r_epp_D(ppc) (inb((ppc)->ppc_base + PPC_EPP_DATA))
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#define r_cnfgA(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGA))
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#define r_cnfgB(ppc) (inb((ppc)->ppc_base + PPC_ECP_CNFGB))
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#define r_ecr(ppc) (inb((ppc)->ppc_base + PPC_ECP_ECR))
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#define r_fifo(ppc) (inb((ppc)->ppc_base + PPC_ECP_D_FIFO))
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#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte)
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#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte)
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#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte)
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#define w_epp_A(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_ADDR, byte)
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#define w_epp_D(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte)
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#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte)
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#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_D_FIFO, byte)
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/*
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* Register defines for the PC873xx parts
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*/
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#define PC873_FER 0x00
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#define PC873_PPENABLE (1<<0)
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#define PC873_FAR 0x01
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#define PC873_PTR 0x02
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#define PC873_CFGLOCK (1<<6)
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#define PC873_EPPRDIR (1<<7)
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#define PC873_EXTENDED (1<<7)
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#define PC873_LPTBIRQ7 (1<<3)
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#define PC873_FCR 0x03
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#define PC873_ZWS (1<<5)
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#define PC873_ZWSPWDN (1<<6)
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#define PC873_PCR 0x04
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#define PC873_EPPEN (1<<0)
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#define PC873_EPP19 (1<<1)
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#define PC873_ECPEN (1<<2)
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#define PC873_ECPCLK (1<<3)
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#define PC873_PMC 0x06
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#define PC873_TUP 0x07
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#define PC873_SID 0x08
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#define PC873_PNP0 0x1b
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#define PC873_PNP1 0x1c
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#define PC873_LPTBA 0x19
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/*
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* Register defines for the SMC FDC37C66xGT parts
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*/
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/* Init codes */
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#define SMC665_iCODE 0x55
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#define SMC666_iCODE 0x44
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/* Base configuration ports */
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#define SMC66x_CSR 0x3F0
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#define SMC666_CSR 0x370 /* hard-configured value for 666 */
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/* Bits */
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#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */
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#define SMC_CR1_MODE (1<<3) /* bit 3 */
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#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */
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#define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */
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/* Extended modes */
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#define SMC_SPP 0x0 /* SPP */
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#define SMC_EPPSPP 0x1 /* EPP and SPP */
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#define SMC_ECP 0x2 /* ECP */
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#define SMC_ECPEPP 0x3 /* ECP and EPP */
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/*
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* Register defines for the Winbond W83877F parts
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*/
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#define WINB_W83877F_ID 0xa
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#define WINB_W83877AF_ID 0xb
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/* Configuration bits */
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#define WINB_HEFERE (1<<5) /* CROC bit 5 */
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#define WINB_HEFRAS (1<<0) /* CR16 bit 0 */
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#define WINB_PNPCVS (1<<2) /* CR16 bit 2 */
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#define WINB_CHIPID 0xf /* CR9 bits 0-3 */
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#define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */
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#define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */
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#define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */
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/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
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#define WINB_W83757 0x0
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#define WINB_EXTFDC 0x4
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#define WINB_EXTADP 0x8
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#define WINB_EXT2FDD 0xc
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#define WINB_JOYSTICK 0x80
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#define WINB_PARALLEL 0x80
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#define WINB_EPP_SPP 0x4
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#define WINB_ECP 0x8
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#define WINB_ECP_EPP 0xc
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#endif
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