d/freebsd-skq
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
ce91e745ec
freebsd-skq/sys/powerpc/aim
History
jhibbits 96915338d5 Add hypervisor trap handling, using HSRR0/HSRR1 
Summary:
Some hypervisor exceptions on POWER architecture only save state to HSRR0/HSRR1.
Until we have bhyve on POWER, use a lightweight exception frontend which copies
HSRR0/HSRR1 into SRR0/SRR1, and run the normal trap handler.

The first user of this is the Hypervisor Virtualization Interrupt, which targets
the XIVE interrupt controller on POWER9.

Reviewed By: nwhitehorn
Differential Revision: https://reviews.freebsd.org/D15487
2018-05-19 04:21:50 +00:00
..
aim_machdep.c Add hypervisor trap handling, using HSRR0/HSRR1 2018-05-19 04:21:50 +00:00
locore32.S Rename assym.s to assym.inc 2018-03-20 17:58:51 +00:00
locore64.S Rename assym.s to assym.inc 2018-03-20 17:58:51 +00:00
locore.S
mmu_oea64.c Final fix for alignment issues with the page table first patched with 2018-05-14 04:00:52 +00:00
mmu_oea64.h Final fix for alignment issues with the page table first patched with 2018-05-14 04:00:52 +00:00
mmu_oea.c vm_wait() rework. 2018-02-20 10:13:13 +00:00
moea64_if.m
moea64_native.c Final fix for alignment issues with the page table first patched with 2018-05-14 04:00:52 +00:00
mp_cpudep.c Add POWER9 to the POWER8 bootstrap case blocks 2018-05-05 15:42:58 +00:00
slb.c Move the powerpc64 direct map base address from zero to high memory. This 2018-03-07 17:08:07 +00:00
trap_subr32.S Use the explicit expanded form of cmp. 2017-01-18 03:42:21 +00:00
trap_subr64.S Add hypervisor trap handling, using HSRR0/HSRR1 2018-05-19 04:21:50 +00:00