b2b734e771
o Eliminate tlb0[] (a s/w copy of TLB0)
- The table contents cannot be maintained reliably in multiple MMU
environments, where asynchronous events (invalidations from other cores)
can change our local TLB0 contents underneath.
- Simplify and optimize TLB flushing: system wide invalidations are
performed using tlbivax instruction (propagates to other cores), for
local MMU invalidations a new optimized routine (assembly) is introduced.
o Improve and simplify TID allocation and management.
- Let each core keep track of its TID allocations.
- Simplify TID recycling, eliminate dead code.
- Drop the now unused powerpc/booke/support.S file.
o Improve page tables management logic.
o Simplify TLB1 manipulation routines.
o Other improvements and polishing.
Obtained from: Freescale, Semihalf
152 lines
4.6 KiB
C
152 lines
4.6 KiB
C
/*-
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* Copyright (C) 2006 Semihalf, Marian Balakowicz <m8@semihalf.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
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* TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_TLB_H_
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#define _MACHINE_TLB_H_
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/* PowerPC E500 MAS registers */
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#define MAS0_TLBSEL(x) ((x << 28) & 0x10000000)
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#define MAS0_ESEL(x) ((x << 16) & 0x000F0000)
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#define MAS0_TLBSEL1 0x10000000
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#define MAS0_TLBSEL0 0x00000000
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#define MAS0_ESEL_TLB1MASK 0x000F0000
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#define MAS0_ESEL_TLB0MASK 0x00030000
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#define MAS0_ESEL_SHIFT 16
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#define MAS0_NV_MASK 0x00000003
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#define MAS0_NV_SHIFT 0
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#define MAS1_VALID 0x80000000
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#define MAS1_IPROT 0x40000000
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#define MAS1_TID_MASK 0x00FF0000
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#define MAS1_TID_SHIFT 16
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#define MAS1_TS_MASK 0x00001000
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#define MAS1_TS_SHIFT 12
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#define MAS1_TSIZE_MASK 0x00000F00
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#define MAS1_TSIZE_SHIFT 8
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#define TLB_SIZE_4K 1
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#define TLB_SIZE_16K 2
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#define TLB_SIZE_64K 3
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#define TLB_SIZE_256K 4
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#define TLB_SIZE_1M 5
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#define TLB_SIZE_4M 6
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#define TLB_SIZE_16M 7
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#define TLB_SIZE_64M 8
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#define TLB_SIZE_256M 9
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#define TLB_SIZE_1G 10
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#define TLB_SIZE_4G 11
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#define MAS2_EPN_MASK 0xFFFFF000
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#define MAS2_EPN_SHIFT 12
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#define MAS2_X0 0x00000040
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#define MAS2_X1 0x00000020
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#define MAS2_W 0x00000010
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#define MAS2_I 0x00000008
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#define MAS2_M 0x00000004
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#define MAS2_G 0x00000002
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#define MAS2_E 0x00000001
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#define MAS3_RPN 0xFFFFF000
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#define MAS3_RPN_SHIFT 12
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#define MAS3_U0 0x00000200
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#define MAS3_U1 0x00000100
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#define MAS3_U2 0x00000080
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#define MAS3_U3 0x00000040
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#define MAS3_UX 0x00000020
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#define MAS3_SX 0x00000010
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#define MAS3_UW 0x00000008
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#define MAS3_SW 0x00000004
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#define MAS3_UR 0x00000002
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#define MAS3_SR 0x00000001
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#define MAS4_TLBSELD1 0x10000000
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#define MAS4_TLBSELD0 0x00000000
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#define MAS4_TIDSELD_MASK 0x00030000
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#define MAS4_TIDSELD_SHIFT 16
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#define MAS4_TSIZED_MASK 0x00000F00
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#define MAS4_TSIZED_SHIFT 8
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#define MAS4_X0D 0x00000040
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#define MAS4_X1D 0x00000020
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#define MAS4_WD 0x00000010
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#define MAS4_ID 0x00000008
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#define MAS4_MD 0x00000004
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#define MAS4_GD 0x00000002
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#define MAS4_ED 0x00000001
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#define MAS6_SPID0_MASK 0x00FF0000
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#define MAS6_SPID0_SHIFT 16
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#define MAS6_SAS 0x00000001
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#define MAS1_GETTID(mas1) (((mas1) & MAS1_TID_MASK) >> MAS1_TID_SHIFT)
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#define MAS2_TLB0_ENTRY_IDX_MASK 0x0007f000
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#define MAS2_TLB0_ENTRY_IDX_SHIFT 12
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/*
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* Maximum number of TLB1 entries used for a permanent mapping of kernel
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* region (kernel image plus statically allocated data).
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*/
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#define KERNEL_REGION_MAX_TLB_ENTRIES 4
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#define _TLB_ENTRY_IO (MAS2_I | MAS2_G)
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#ifdef SMP
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#define _TLB_ENTRY_MEM (MAS2_M)
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#else
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#define _TLB_ENTRY_MEM (0)
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#endif
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#define TID_KERNEL 0 /* TLB TID to use for kernel (shared) translations */
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#define TID_KRESERVED 1 /* Number of TIDs reserved for kernel */
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#define TID_URESERVED 0 /* Number of TIDs reserved for user */
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#define TID_MIN (TID_KRESERVED + TID_URESERVED)
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#define TID_MAX 255
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#define TID_NONE -1
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#if !defined(LOCORE)
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typedef struct tlb_entry {
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uint32_t mas1;
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uint32_t mas2;
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uint32_t mas3;
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} tlb_entry_t;
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typedef int tlbtid_t;
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struct pmap;
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void tlb0_print_tlbentries(void);
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void tlb1_inval_entry(unsigned int);
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void tlb1_init(vm_offset_t);
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void tlb1_print_entries(void);
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void tlb1_print_tlbentries(void);
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#endif /* !LOCORE */
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#endif /* _MACHINE_TLB_H_ */
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