59c3cb81c1
independent code that needs to know about INTRNG such as PCI drivers. Obtained from: ABT Systems Ltd Sponsored by: The FreeBSD Foundation
1333 lines
32 KiB
C
1333 lines
32 KiB
C
/*-
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* Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
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* Copyright (c) 2014 Luiz Otavio O Souza <loos@FreeBSD.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* Beware that the OMAP4 datasheet(s) lists GPIO banks 1-6, whereas the code
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* here uses 0-5.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_platform.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <sys/interrupt.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <arm/ti/ti_cpuid.h>
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#include <arm/ti/ti_gpio.h>
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#include <arm/ti/ti_scm.h>
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#include <arm/ti/ti_prcm.h>
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#include <arm/ti/ti_hwmods.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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#include "ti_gpio_if.h"
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#ifdef INTRNG
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#include "pic_if.h"
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#endif
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#if !defined(SOC_OMAP4) && !defined(SOC_TI_AM335X)
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#error "Unknown SoC"
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#endif
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/* Register definitions */
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#define TI_GPIO_REVISION 0x0000
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#define TI_GPIO_SYSCONFIG 0x0010
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#define TI_GPIO_IRQSTATUS_RAW_0 0x0024
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#define TI_GPIO_IRQSTATUS_RAW_1 0x0028
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#define TI_GPIO_IRQSTATUS_0 0x002C /* writing a 0 has no effect */
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#define TI_GPIO_IRQSTATUS_1 0x0030 /* writing a 0 has no effect */
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#define TI_GPIO_IRQSTATUS_SET_0 0x0034 /* writing a 0 has no effect */
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#define TI_GPIO_IRQSTATUS_SET_1 0x0038 /* writing a 0 has no effect */
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#define TI_GPIO_IRQSTATUS_CLR_0 0x003C /* writing a 0 has no effect */
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#define TI_GPIO_IRQSTATUS_CLR_1 0x0040 /* writing a 0 has no effect */
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#define TI_GPIO_IRQWAKEN_0 0x0044
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#define TI_GPIO_IRQWAKEN_1 0x0048
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#define TI_GPIO_SYSSTATUS 0x0114
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#define TI_GPIO_IRQSTATUS1 0x0118
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#define TI_GPIO_IRQENABLE1 0x011C
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#define TI_GPIO_WAKEUPENABLE 0x0120
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#define TI_GPIO_IRQSTATUS2 0x0128
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#define TI_GPIO_IRQENABLE2 0x012C
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#define TI_GPIO_CTRL 0x0130
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#define TI_GPIO_OE 0x0134
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#define TI_GPIO_DATAIN 0x0138
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#define TI_GPIO_DATAOUT 0x013C
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#define TI_GPIO_LEVELDETECT0 0x0140 /* RW register */
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#define TI_GPIO_LEVELDETECT1 0x0144 /* RW register */
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#define TI_GPIO_RISINGDETECT 0x0148 /* RW register */
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#define TI_GPIO_FALLINGDETECT 0x014C /* RW register */
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#define TI_GPIO_DEBOUNCENABLE 0x0150
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#define TI_GPIO_DEBOUNCINGTIME 0x0154
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#define TI_GPIO_CLEARWKUPENA 0x0180
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#define TI_GPIO_SETWKUENA 0x0184
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#define TI_GPIO_CLEARDATAOUT 0x0190
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#define TI_GPIO_SETDATAOUT 0x0194
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/* Other SoC Specific definitions */
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#define OMAP4_FIRST_GPIO_BANK 1
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#define OMAP4_INTR_PER_BANK 1
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#define OMAP4_GPIO_REV 0x50600801
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#define AM335X_FIRST_GPIO_BANK 0
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#define AM335X_INTR_PER_BANK 2
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#define AM335X_GPIO_REV 0x50600801
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#define PINS_PER_BANK 32
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#define TI_GPIO_MASK(p) (1U << ((p) % PINS_PER_BANK))
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static int ti_gpio_intr(void *arg);
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static int ti_gpio_detach(device_t);
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#ifdef INTRNG
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static int ti_gpio_pic_attach(struct ti_gpio_softc *sc);
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static int ti_gpio_pic_detach(struct ti_gpio_softc *sc);
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#endif
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static u_int
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ti_first_gpio_bank(void)
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{
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switch(ti_chip()) {
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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return (OMAP4_FIRST_GPIO_BANK);
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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return (AM335X_FIRST_GPIO_BANK);
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#endif
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}
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return (0);
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}
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static uint32_t
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ti_gpio_rev(void)
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{
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switch(ti_chip()) {
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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return (OMAP4_GPIO_REV);
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#endif
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#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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return (AM335X_GPIO_REV);
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#endif
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}
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return (0);
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}
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/**
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* Macros for driver mutex locking
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*/
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#define TI_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx)
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#define TI_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx)
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#define TI_GPIO_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit((_sc)->sc_dev), \
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"ti_gpio", MTX_SPIN)
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#define TI_GPIO_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->sc_mtx)
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#define TI_GPIO_ASSERT_LOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED)
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#define TI_GPIO_ASSERT_UNLOCKED(_sc) mtx_assert(&(_sc)->sc_mtx, MA_NOTOWNED)
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/**
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* ti_gpio_read_4 - reads a 32-bit value from one of the GPIO registers
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* @sc: GPIO device context
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* @bank: The bank to read from
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* @off: The offset of a register from the GPIO register address range
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*
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*
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* RETURNS:
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* 32-bit value read from the register.
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*/
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static inline uint32_t
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ti_gpio_read_4(struct ti_gpio_softc *sc, bus_size_t off)
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{
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return (bus_read_4(sc->sc_mem_res, off));
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}
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/**
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* ti_gpio_write_4 - writes a 32-bit value to one of the GPIO registers
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* @sc: GPIO device context
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* @bank: The bank to write to
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* @off: The offset of a register from the GPIO register address range
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* @val: The value to write into the register
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*
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* RETURNS:
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* nothing
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*/
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static inline void
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ti_gpio_write_4(struct ti_gpio_softc *sc, bus_size_t off,
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uint32_t val)
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{
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bus_write_4(sc->sc_mem_res, off, val);
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}
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static inline void
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ti_gpio_intr_clr(struct ti_gpio_softc *sc, uint32_t mask)
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{
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/* We clear both set of registers. */
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ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_0, mask);
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ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_CLR_1, mask);
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}
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static inline void
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ti_gpio_intr_set(struct ti_gpio_softc *sc, uint32_t mask)
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{
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/*
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* On OMAP4 we unmask only the MPU interrupt and on AM335x we
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* also activate only the first interrupt.
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*/
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ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_SET_0, mask);
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}
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static inline void
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ti_gpio_intr_ack(struct ti_gpio_softc *sc, uint32_t mask)
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{
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/*
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* Acknowledge the interrupt on both registers even if we use only
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* the first one.
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*/
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ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_0, mask);
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ti_gpio_write_4(sc, TI_GPIO_IRQSTATUS_1, mask);
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}
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static inline uint32_t
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ti_gpio_intr_status(struct ti_gpio_softc *sc)
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{
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uint32_t reg;
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/* Get the status from both registers. */
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reg = ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_0);
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reg |= ti_gpio_read_4(sc, TI_GPIO_IRQSTATUS_1);
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return (reg);
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}
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static device_t
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ti_gpio_get_bus(device_t dev)
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{
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struct ti_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->sc_busdev);
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}
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/**
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* ti_gpio_pin_max - Returns the maximum number of GPIO pins
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* @dev: gpio device handle
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* @maxpin: pointer to a value that upon return will contain the maximum number
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* of pins in the device.
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*
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*
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* LOCKING:
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* No locking required, returns static data.
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_max(device_t dev, int *maxpin)
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{
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*maxpin = PINS_PER_BANK - 1;
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return (0);
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}
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static int
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ti_gpio_valid_pin(struct ti_gpio_softc *sc, int pin)
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{
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if (pin >= sc->sc_maxpin || sc->sc_mem_res == NULL)
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return (EINVAL);
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return (0);
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}
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/**
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* ti_gpio_pin_getcaps - Gets the capabilties of a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @caps: pointer to a value that upon return will contain the capabilities
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*
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* Currently all pins have the same capability, notably:
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* - GPIO_PIN_INPUT
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* - GPIO_PIN_OUTPUT
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* - GPIO_PIN_PULLUP
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* - GPIO_PIN_PULLDOWN
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*
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* LOCKING:
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* No locking required, returns static data.
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct ti_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (ti_gpio_valid_pin(sc, pin) != 0)
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return (EINVAL);
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*caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_PULLUP |
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GPIO_PIN_PULLDOWN);
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return (0);
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}
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/**
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* ti_gpio_pin_getflags - Gets the current flags of a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @flags: upon return will contain the current flags of the pin
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*
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* Reads the current flags of a given pin, here we actually read the H/W
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* registers to determine the flags, rather than storing the value in the
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* setflags call.
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct ti_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (ti_gpio_valid_pin(sc, pin) != 0)
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return (EINVAL);
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/* Get the current pin state */
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TI_GPIO_LOCK(sc);
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TI_GPIO_GET_FLAGS(dev, pin, flags);
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TI_GPIO_UNLOCK(sc);
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return (0);
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}
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/**
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* ti_gpio_pin_getname - Gets the name of a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @name: buffer to put the name in
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*
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* The driver simply calls the pins gpio_n, where 'n' is obviously the number
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* of the pin.
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*
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* LOCKING:
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* No locking required, returns static data.
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct ti_gpio_softc *sc;
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sc = device_get_softc(dev);
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if (ti_gpio_valid_pin(sc, pin) != 0)
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return (EINVAL);
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/* Set a very simple name */
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snprintf(name, GPIOMAXNAME, "gpio_%u", pin);
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name[GPIOMAXNAME - 1] = '\0';
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return (0);
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}
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/**
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* ti_gpio_pin_setflags - Sets the flags for a given pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @flags: the flags to set
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*
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* The flags of the pin correspond to things like input/output mode, pull-ups,
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* pull-downs, etc. This driver doesn't support all flags, only the following:
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* - GPIO_PIN_INPUT
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* - GPIO_PIN_OUTPUT
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* - GPIO_PIN_PULLUP
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* - GPIO_PIN_PULLDOWN
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise an error code
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*/
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static int
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ti_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct ti_gpio_softc *sc;
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uint32_t oe;
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sc = device_get_softc(dev);
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if (ti_gpio_valid_pin(sc, pin) != 0)
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return (EINVAL);
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/* Set the GPIO mode and state */
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TI_GPIO_LOCK(sc);
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if (TI_GPIO_SET_FLAGS(dev, pin, flags) != 0) {
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TI_GPIO_UNLOCK(sc);
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return (EINVAL);
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}
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/* If configuring as an output set the "output enable" bit */
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oe = ti_gpio_read_4(sc, TI_GPIO_OE);
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if (flags & GPIO_PIN_INPUT)
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oe |= TI_GPIO_MASK(pin);
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else
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oe &= ~TI_GPIO_MASK(pin);
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ti_gpio_write_4(sc, TI_GPIO_OE, oe);
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TI_GPIO_UNLOCK(sc);
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return (0);
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}
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/**
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* ti_gpio_pin_set - Sets the current level on a GPIO pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @value: non-zero value will drive the pin high, otherwise the pin is
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* driven low.
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*
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise a error code
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*/
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static int
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ti_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct ti_gpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (ti_gpio_valid_pin(sc, pin) != 0)
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return (EINVAL);
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TI_GPIO_LOCK(sc);
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if (value == GPIO_PIN_LOW)
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reg = TI_GPIO_CLEARDATAOUT;
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else
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reg = TI_GPIO_SETDATAOUT;
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ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
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TI_GPIO_UNLOCK(sc);
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return (0);
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}
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/**
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* ti_gpio_pin_get - Gets the current level on a GPIO pin
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* @dev: gpio device handle
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* @pin: the number of the pin
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* @value: pointer to a value that upond return will contain the pin value
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*
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* The pin must be configured as an input pin beforehand, otherwise this
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* function will fail.
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*
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* LOCKING:
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* Internally locks the context
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*
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* RETURNS:
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* Returns 0 on success otherwise a error code
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*/
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static int
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ti_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
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{
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struct ti_gpio_softc *sc;
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uint32_t oe, reg, val;
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sc = device_get_softc(dev);
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if (ti_gpio_valid_pin(sc, pin) != 0)
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return (EINVAL);
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/*
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* Return data from output latch when set as output and from the
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* input register otherwise.
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*/
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TI_GPIO_LOCK(sc);
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oe = ti_gpio_read_4(sc, TI_GPIO_OE);
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if (oe & TI_GPIO_MASK(pin))
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reg = TI_GPIO_DATAIN;
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else
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reg = TI_GPIO_DATAOUT;
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val = ti_gpio_read_4(sc, reg);
|
|
*value = (val & TI_GPIO_MASK(pin)) ? 1 : 0;
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_pin_toggle - Toggles a given GPIO pin
|
|
* @dev: gpio device handle
|
|
* @pin: the number of the pin
|
|
*
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
* RETURNS:
|
|
* Returns 0 on success otherwise a error code
|
|
*/
|
|
static int
|
|
ti_gpio_pin_toggle(device_t dev, uint32_t pin)
|
|
{
|
|
struct ti_gpio_softc *sc;
|
|
uint32_t reg, val;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (ti_gpio_valid_pin(sc, pin) != 0)
|
|
return (EINVAL);
|
|
|
|
/* Toggle the pin */
|
|
TI_GPIO_LOCK(sc);
|
|
val = ti_gpio_read_4(sc, TI_GPIO_DATAOUT);
|
|
if (val & TI_GPIO_MASK(pin))
|
|
reg = TI_GPIO_CLEARDATAOUT;
|
|
else
|
|
reg = TI_GPIO_SETDATAOUT;
|
|
ti_gpio_write_4(sc, reg, TI_GPIO_MASK(pin));
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
#ifndef INTRNG
|
|
/**
|
|
* ti_gpio_intr - ISR for all GPIO modules
|
|
* @arg: the soft context pointer
|
|
*
|
|
* LOCKING:
|
|
* Internally locks the context
|
|
*
|
|
*/
|
|
static int
|
|
ti_gpio_intr(void *arg)
|
|
{
|
|
int bank_last, irq;
|
|
struct intr_event *event;
|
|
struct ti_gpio_softc *sc;
|
|
uint32_t reg;
|
|
|
|
sc = (struct ti_gpio_softc *)arg;
|
|
bank_last = -1;
|
|
reg = 0; /* squelch bogus gcc warning */
|
|
reg = ti_gpio_intr_status(sc);
|
|
for (irq = 0; irq < sc->sc_maxpin; irq++) {
|
|
if ((reg & TI_GPIO_MASK(irq)) == 0)
|
|
continue;
|
|
event = sc->sc_events[irq];
|
|
if (event != NULL && !TAILQ_EMPTY(&event->ie_handlers))
|
|
intr_event_handle(event, NULL);
|
|
else
|
|
device_printf(sc->sc_dev, "Stray IRQ %d\n", irq);
|
|
/* Ack the IRQ Status bit. */
|
|
ti_gpio_intr_ack(sc, TI_GPIO_MASK(irq));
|
|
}
|
|
|
|
return (FILTER_HANDLED);
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
ti_gpio_bank_init(device_t dev)
|
|
{
|
|
int pin;
|
|
struct ti_gpio_softc *sc;
|
|
uint32_t flags, reg_oe, reg_set, rev;
|
|
clk_ident_t clk;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
/* Enable the interface and functional clocks for the module. */
|
|
clk = ti_hwmods_get_clock(dev);
|
|
if (clk == INVALID_CLK_IDENT) {
|
|
device_printf(dev, "failed to get device id based on ti,hwmods\n");
|
|
return (EINVAL);
|
|
}
|
|
|
|
sc->sc_bank = clk - GPIO1_CLK + ti_first_gpio_bank();
|
|
ti_prcm_clk_enable(clk);
|
|
|
|
/*
|
|
* Read the revision number of the module. TI don't publish the
|
|
* actual revision numbers, so instead the values have been
|
|
* determined by experimentation.
|
|
*/
|
|
rev = ti_gpio_read_4(sc, TI_GPIO_REVISION);
|
|
|
|
/* Check the revision. */
|
|
if (rev != ti_gpio_rev()) {
|
|
device_printf(dev, "Warning: could not determine the revision "
|
|
"of GPIO module (revision:0x%08x)\n", rev);
|
|
return (EINVAL);
|
|
}
|
|
|
|
/* Disable interrupts for all pins. */
|
|
ti_gpio_intr_clr(sc, 0xffffffff);
|
|
|
|
/* Init OE register based on pads configuration. */
|
|
reg_oe = 0xffffffff;
|
|
reg_set = 0;
|
|
for (pin = 0; pin < PINS_PER_BANK; pin++) {
|
|
TI_GPIO_GET_FLAGS(dev, pin, &flags);
|
|
if (flags & GPIO_PIN_OUTPUT) {
|
|
reg_oe &= ~(1UL << pin);
|
|
if (flags & GPIO_PIN_PULLUP)
|
|
reg_set |= (1UL << pin);
|
|
}
|
|
}
|
|
ti_gpio_write_4(sc, TI_GPIO_OE, reg_oe);
|
|
if (reg_set)
|
|
ti_gpio_write_4(sc, TI_GPIO_SETDATAOUT, reg_set);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_attach - attach function for the driver
|
|
* @dev: gpio device handle
|
|
*
|
|
* Allocates and sets up the driver context for all GPIO banks. This function
|
|
* expects the memory ranges and IRQs to already be allocated to the driver.
|
|
*
|
|
* LOCKING:
|
|
* None
|
|
*
|
|
* RETURNS:
|
|
* Always returns 0
|
|
*/
|
|
static int
|
|
ti_gpio_attach(device_t dev)
|
|
{
|
|
struct ti_gpio_softc *sc;
|
|
#ifndef INTRNG
|
|
unsigned int i;
|
|
#endif
|
|
int err;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
TI_GPIO_LOCK_INIT(sc);
|
|
ti_gpio_pin_max(dev, &sc->sc_maxpin);
|
|
sc->sc_maxpin++;
|
|
|
|
sc->sc_mem_rid = 0;
|
|
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&sc->sc_mem_rid, RF_ACTIVE);
|
|
if (!sc->sc_mem_res) {
|
|
device_printf(dev, "Error: could not allocate mem resources\n");
|
|
ti_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
sc->sc_irq_rid = 0;
|
|
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
|
|
&sc->sc_irq_rid, RF_ACTIVE);
|
|
if (!sc->sc_irq_res) {
|
|
device_printf(dev, "Error: could not allocate irq resources\n");
|
|
ti_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/*
|
|
* Register our interrupt filter for each of the IRQ resources.
|
|
*/
|
|
if (bus_setup_intr(dev, sc->sc_irq_res,
|
|
INTR_TYPE_MISC | INTR_MPSAFE, ti_gpio_intr, NULL, sc,
|
|
&sc->sc_irq_hdl) != 0) {
|
|
device_printf(dev,
|
|
"WARNING: unable to register interrupt filter\n");
|
|
ti_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
#ifdef INTRNG
|
|
if (ti_gpio_pic_attach(sc) != 0) {
|
|
device_printf(dev, "WARNING: unable to attach PIC\n");
|
|
ti_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
#else
|
|
/*
|
|
* Initialize the interrupt settings. The default is active-low
|
|
* interrupts.
|
|
*/
|
|
sc->sc_irq_trigger = malloc(
|
|
sizeof(*sc->sc_irq_trigger) * sc->sc_maxpin,
|
|
M_DEVBUF, M_WAITOK | M_ZERO);
|
|
sc->sc_irq_polarity = malloc(
|
|
sizeof(*sc->sc_irq_polarity) * sc->sc_maxpin,
|
|
M_DEVBUF, M_WAITOK | M_ZERO);
|
|
for (i = 0; i < sc->sc_maxpin; i++) {
|
|
sc->sc_irq_trigger[i] = INTR_TRIGGER_LEVEL;
|
|
sc->sc_irq_polarity[i] = INTR_POLARITY_LOW;
|
|
}
|
|
|
|
sc->sc_events = malloc(sizeof(struct intr_event *) * sc->sc_maxpin,
|
|
M_DEVBUF, M_WAITOK | M_ZERO);
|
|
|
|
sc->sc_mask_args = malloc(sizeof(struct ti_gpio_mask_arg) * sc->sc_maxpin,
|
|
M_DEVBUF, M_WAITOK | M_ZERO);
|
|
#endif
|
|
/* We need to go through each block and ensure the clocks are running and
|
|
* the module is enabled. It might be better to do this only when the
|
|
* pins are configured which would result in less power used if the GPIO
|
|
* pins weren't used ...
|
|
*/
|
|
if (sc->sc_mem_res != NULL) {
|
|
/* Initialize the GPIO module. */
|
|
err = ti_gpio_bank_init(dev);
|
|
if (err != 0) {
|
|
ti_gpio_detach(dev);
|
|
return (err);
|
|
}
|
|
}
|
|
|
|
sc->sc_busdev = gpiobus_attach_bus(dev);
|
|
if (sc->sc_busdev == NULL) {
|
|
ti_gpio_detach(dev);
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
/**
|
|
* ti_gpio_detach - detach function for the driver
|
|
* @dev: scm device handle
|
|
*
|
|
* Allocates and sets up the driver context, this simply entails creating a
|
|
* bus mappings for the SCM register set.
|
|
*
|
|
* LOCKING:
|
|
* None
|
|
*
|
|
* RETURNS:
|
|
* Always returns 0
|
|
*/
|
|
static int
|
|
ti_gpio_detach(device_t dev)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
|
|
KASSERT(mtx_initialized(&sc->sc_mtx), ("gpio mutex not initialized"));
|
|
|
|
/* Disable all interrupts */
|
|
if (sc->sc_mem_res != NULL)
|
|
ti_gpio_intr_clr(sc, 0xffffffff);
|
|
gpiobus_detach_bus(dev);
|
|
#ifdef INTRNG
|
|
if (sc->sc_isrcs != NULL)
|
|
ti_gpio_pic_detach(sc);
|
|
#else
|
|
if (sc->sc_events)
|
|
free(sc->sc_events, M_DEVBUF);
|
|
if (sc->sc_mask_args)
|
|
free(sc->sc_mask_args, M_DEVBUF);
|
|
if (sc->sc_irq_polarity)
|
|
free(sc->sc_irq_polarity, M_DEVBUF);
|
|
if (sc->sc_irq_trigger)
|
|
free(sc->sc_irq_trigger, M_DEVBUF);
|
|
#endif
|
|
/* Release the memory and IRQ resources. */
|
|
if (sc->sc_irq_hdl) {
|
|
bus_teardown_intr(dev, sc->sc_irq_res,
|
|
sc->sc_irq_hdl);
|
|
}
|
|
bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
|
|
sc->sc_irq_res);
|
|
bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
|
|
sc->sc_mem_res);
|
|
TI_GPIO_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
#ifdef INTRNG
|
|
static inline void
|
|
ti_gpio_rwreg_set(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask)
|
|
{
|
|
|
|
ti_gpio_write_4(sc, reg, ti_gpio_read_4(sc, reg) | mask);
|
|
}
|
|
|
|
static inline void
|
|
ti_gpio_rwreg_clr(struct ti_gpio_softc *sc, uint32_t reg, uint32_t mask)
|
|
{
|
|
|
|
ti_gpio_write_4(sc, reg, ti_gpio_read_4(sc, reg) & ~mask);
|
|
}
|
|
|
|
static inline void
|
|
ti_gpio_isrc_mask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
|
|
{
|
|
|
|
/* Writing a 0 has no effect. */
|
|
ti_gpio_intr_clr(sc, tgi->tgi_mask);
|
|
}
|
|
|
|
static inline void
|
|
ti_gpio_isrc_unmask(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
|
|
{
|
|
|
|
/* Writing a 0 has no effect. */
|
|
ti_gpio_intr_set(sc, tgi->tgi_mask);
|
|
}
|
|
|
|
static inline void
|
|
ti_gpio_isrc_eoi(struct ti_gpio_softc *sc, struct ti_gpio_irqsrc *tgi)
|
|
{
|
|
|
|
/* Writing a 0 has no effect. */
|
|
ti_gpio_intr_ack(sc, tgi->tgi_mask);
|
|
}
|
|
|
|
static inline bool
|
|
ti_gpio_isrc_is_level(struct ti_gpio_irqsrc *tgi)
|
|
{
|
|
|
|
return (tgi->tgi_cfgreg == TI_GPIO_LEVELDETECT0 ||
|
|
tgi->tgi_cfgreg == TI_GPIO_LEVELDETECT1);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_intr(void *arg)
|
|
{
|
|
u_int irq;
|
|
uint32_t reg;
|
|
struct ti_gpio_softc *sc;
|
|
struct trapframe *tf;
|
|
struct ti_gpio_irqsrc *tgi;
|
|
|
|
sc = (struct ti_gpio_softc *)arg;
|
|
tf = curthread->td_intr_frame;
|
|
|
|
reg = ti_gpio_intr_status(sc);
|
|
for (irq = 0; irq < sc->sc_maxpin; irq++) {
|
|
tgi = &sc->sc_isrcs[irq];
|
|
if ((reg & tgi->tgi_mask) == 0)
|
|
continue;
|
|
if (!ti_gpio_isrc_is_level(tgi))
|
|
ti_gpio_isrc_eoi(sc, tgi);
|
|
if (intr_isrc_dispatch(&tgi->tgi_isrc, tf) != 0) {
|
|
ti_gpio_isrc_mask(sc, tgi);
|
|
if (ti_gpio_isrc_is_level(tgi))
|
|
ti_gpio_isrc_eoi(sc, tgi);
|
|
device_printf(sc->sc_dev, "Stray irq %u disabled\n",
|
|
irq);
|
|
}
|
|
}
|
|
return (FILTER_HANDLED);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_pic_attach(struct ti_gpio_softc *sc)
|
|
{
|
|
int error;
|
|
uint32_t irq;
|
|
const char *name;
|
|
|
|
sc->sc_isrcs = malloc(sizeof(*sc->sc_isrcs) * sc->sc_maxpin, M_DEVBUF,
|
|
M_WAITOK | M_ZERO);
|
|
|
|
name = device_get_nameunit(sc->sc_dev);
|
|
for (irq = 0; irq < sc->sc_maxpin; irq++) {
|
|
sc->sc_isrcs[irq].tgi_irq = irq;
|
|
sc->sc_isrcs[irq].tgi_mask = TI_GPIO_MASK(irq);
|
|
sc->sc_isrcs[irq].tgi_cfgreg = 0;
|
|
|
|
error = intr_isrc_register(&sc->sc_isrcs[irq].tgi_isrc,
|
|
sc->sc_dev, 0, "%s,%u", name, irq);
|
|
if (error != 0)
|
|
return (error); /* XXX deregister ISRCs */
|
|
}
|
|
return (intr_pic_register(sc->sc_dev,
|
|
OF_xref_from_node(ofw_bus_get_node(sc->sc_dev))));
|
|
}
|
|
|
|
static int
|
|
ti_gpio_pic_detach(struct ti_gpio_softc *sc)
|
|
{
|
|
|
|
/*
|
|
* There has not been established any procedure yet
|
|
* how to detach PIC from living system correctly.
|
|
*/
|
|
device_printf(sc->sc_dev, "%s: not implemented yet\n", __func__);
|
|
return (EBUSY);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
|
|
|
|
ti_gpio_isrc_mask(sc, tgi);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
|
|
|
|
arm_irq_memory_barrier(tgi->tgi_irq);
|
|
ti_gpio_isrc_unmask(sc, tgi);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_pic_map_fdt(struct ti_gpio_softc *sc, u_int ncells, pcell_t *cells,
|
|
u_int *irqp, uint32_t *regp)
|
|
{
|
|
uint32_t reg;
|
|
|
|
/*
|
|
* The first cell is the interrupt number.
|
|
* The second cell is used to specify flags:
|
|
* bits[3:0] trigger type and level flags:
|
|
* 1 = low-to-high edge triggered.
|
|
* 2 = high-to-low edge triggered.
|
|
* 4 = active high level-sensitive.
|
|
* 8 = active low level-sensitive.
|
|
*/
|
|
if (ncells != 2 || cells[0] >= sc->sc_maxpin)
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* All interrupt types could be set for an interrupt at one moment.
|
|
* At least, the combination of 'low-to-high' and 'high-to-low' edge
|
|
* triggered interrupt types can make a sense. However, no combo is
|
|
* supported now.
|
|
*/
|
|
if (cells[1] == 1)
|
|
reg = TI_GPIO_RISINGDETECT;
|
|
else if (cells[1] == 2)
|
|
reg = TI_GPIO_FALLINGDETECT;
|
|
else if (cells[1] == 4)
|
|
reg = TI_GPIO_LEVELDETECT1;
|
|
else if (cells[1] == 8)
|
|
reg = TI_GPIO_LEVELDETECT0;
|
|
else
|
|
return (EINVAL);
|
|
|
|
*irqp = cells[0];
|
|
if (regp != NULL)
|
|
*regp = reg;
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
|
|
struct intr_irqsrc **isrcp)
|
|
{
|
|
int error;
|
|
u_int irq;
|
|
struct ti_gpio_softc *sc;
|
|
|
|
if (data->type != INTR_MAP_DATA_FDT)
|
|
return (ENOTSUP);
|
|
|
|
sc = device_get_softc(dev);
|
|
error = ti_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells, &irq,
|
|
NULL);
|
|
if (error == 0)
|
|
*isrcp = &sc->sc_isrcs[irq].tgi_isrc;
|
|
return (error);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
|
|
|
|
if (ti_gpio_isrc_is_level(tgi))
|
|
ti_gpio_isrc_eoi(sc, tgi);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
|
|
ti_gpio_pic_enable_intr(dev, isrc);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
|
|
|
|
ti_gpio_isrc_mask(sc, tgi);
|
|
if (ti_gpio_isrc_is_level(tgi))
|
|
ti_gpio_isrc_eoi(sc, tgi);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
u_int irq;
|
|
uint32_t cfgreg;
|
|
struct ti_gpio_softc *sc;
|
|
struct ti_gpio_irqsrc *tgi;
|
|
|
|
if (data == NULL || data->type != INTR_MAP_DATA_FDT)
|
|
return (ENOTSUP);
|
|
|
|
sc = device_get_softc(dev);
|
|
tgi = (struct ti_gpio_irqsrc *)isrc;
|
|
|
|
/* Get and check config for an interrupt. */
|
|
if (ti_gpio_pic_map_fdt(sc, data->fdt.ncells, data->fdt.cells, &irq,
|
|
&cfgreg) != 0 || tgi->tgi_irq != irq)
|
|
return (EINVAL);
|
|
|
|
/*
|
|
* If this is a setup for another handler,
|
|
* only check that its configuration match.
|
|
*/
|
|
if (isrc->isrc_handlers != 0)
|
|
return (tgi->tgi_cfgreg == cfgreg ? 0 : EINVAL);
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
ti_gpio_rwreg_clr(sc, TI_GPIO_RISINGDETECT, tgi->tgi_mask);
|
|
ti_gpio_rwreg_clr(sc, TI_GPIO_FALLINGDETECT, tgi->tgi_mask);
|
|
ti_gpio_rwreg_clr(sc, TI_GPIO_LEVELDETECT1, tgi->tgi_mask);
|
|
ti_gpio_rwreg_clr(sc, TI_GPIO_LEVELDETECT0, tgi->tgi_mask);
|
|
tgi->tgi_cfgreg = cfgreg;
|
|
ti_gpio_rwreg_set(sc, cfgreg, tgi->tgi_mask);
|
|
TI_GPIO_UNLOCK(sc);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
|
|
struct resource *res, struct intr_map_data *data)
|
|
{
|
|
struct ti_gpio_softc *sc = device_get_softc(dev);
|
|
struct ti_gpio_irqsrc *tgi = (struct ti_gpio_irqsrc *)isrc;
|
|
|
|
if (isrc->isrc_handlers == 0) {
|
|
TI_GPIO_LOCK(sc);
|
|
ti_gpio_rwreg_clr(sc, tgi->tgi_cfgreg, tgi->tgi_mask);
|
|
tgi->tgi_cfgreg = 0;
|
|
TI_GPIO_UNLOCK(sc);
|
|
}
|
|
return (0);
|
|
}
|
|
|
|
#else
|
|
static uint32_t
|
|
ti_gpio_intr_reg(struct ti_gpio_softc *sc, int irq)
|
|
{
|
|
|
|
if (ti_gpio_valid_pin(sc, irq) != 0)
|
|
return (0);
|
|
|
|
if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_LEVEL) {
|
|
if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
|
|
return (TI_GPIO_LEVELDETECT0);
|
|
else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
|
|
return (TI_GPIO_LEVELDETECT1);
|
|
} else if (sc->sc_irq_trigger[irq] == INTR_TRIGGER_EDGE) {
|
|
if (sc->sc_irq_polarity[irq] == INTR_POLARITY_LOW)
|
|
return (TI_GPIO_FALLINGDETECT);
|
|
else if (sc->sc_irq_polarity[irq] == INTR_POLARITY_HIGH)
|
|
return (TI_GPIO_RISINGDETECT);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_mask_irq_internal(struct ti_gpio_softc *sc, int irq)
|
|
{
|
|
uint32_t reg, val;
|
|
|
|
if (ti_gpio_valid_pin(sc, irq) != 0)
|
|
return;
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
ti_gpio_intr_clr(sc, TI_GPIO_MASK(irq));
|
|
reg = ti_gpio_intr_reg(sc, irq);
|
|
if (reg != 0) {
|
|
val = ti_gpio_read_4(sc, reg);
|
|
val &= ~TI_GPIO_MASK(irq);
|
|
ti_gpio_write_4(sc, reg, val);
|
|
}
|
|
TI_GPIO_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_unmask_irq_internal(struct ti_gpio_softc *sc, int irq)
|
|
{
|
|
uint32_t reg, val;
|
|
|
|
if (ti_gpio_valid_pin(sc, irq) != 0)
|
|
return;
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
reg = ti_gpio_intr_reg(sc, irq);
|
|
if (reg != 0) {
|
|
val = ti_gpio_read_4(sc, reg);
|
|
val |= TI_GPIO_MASK(irq);
|
|
ti_gpio_write_4(sc, reg, val);
|
|
ti_gpio_intr_set(sc, TI_GPIO_MASK(irq));
|
|
}
|
|
TI_GPIO_UNLOCK(sc);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_mask_irq(void *source)
|
|
{
|
|
struct ti_gpio_mask_arg *arg = source;
|
|
|
|
ti_gpio_mask_irq_internal(arg->softc, arg->pin);
|
|
}
|
|
|
|
static void
|
|
ti_gpio_unmask_irq(void *source)
|
|
{
|
|
struct ti_gpio_mask_arg *arg = source;
|
|
|
|
ti_gpio_unmask_irq_internal(arg->softc, arg->pin);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_activate_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *res)
|
|
{
|
|
struct ti_gpio_mask_arg mask_arg;
|
|
|
|
if (type != SYS_RES_IRQ)
|
|
return (ENXIO);
|
|
|
|
/* Unmask the interrupt. */
|
|
mask_arg.pin = rman_get_start(res);
|
|
mask_arg.softc = device_get_softc(dev);
|
|
|
|
ti_gpio_unmask_irq((void *)&mask_arg);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_deactivate_resource(device_t dev, device_t child, int type, int rid,
|
|
struct resource *res)
|
|
{
|
|
int pin;
|
|
|
|
if (type != SYS_RES_IRQ)
|
|
return (ENXIO);
|
|
|
|
/* Mask the interrupt. */
|
|
pin = rman_get_start(res);
|
|
ti_gpio_mask_irq((void *)(uintptr_t)pin);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_config_intr(device_t dev, int irq, enum intr_trigger trig,
|
|
enum intr_polarity pol)
|
|
{
|
|
struct ti_gpio_softc *sc;
|
|
uint32_t oldreg, reg, val;
|
|
|
|
sc = device_get_softc(dev);
|
|
if (ti_gpio_valid_pin(sc, irq) != 0)
|
|
return (EINVAL);
|
|
|
|
/* There is no standard trigger or polarity. */
|
|
if (trig == INTR_TRIGGER_CONFORM || pol == INTR_POLARITY_CONFORM)
|
|
return (EINVAL);
|
|
|
|
TI_GPIO_LOCK(sc);
|
|
/*
|
|
* TRM recommends add the new event before remove the old one to
|
|
* avoid losing interrupts.
|
|
*/
|
|
oldreg = ti_gpio_intr_reg(sc, irq);
|
|
sc->sc_irq_trigger[irq] = trig;
|
|
sc->sc_irq_polarity[irq] = pol;
|
|
reg = ti_gpio_intr_reg(sc, irq);
|
|
if (reg != 0) {
|
|
/* Apply the new settings. */
|
|
val = ti_gpio_read_4(sc, reg);
|
|
val |= TI_GPIO_MASK(irq);
|
|
ti_gpio_write_4(sc, reg, val);
|
|
}
|
|
if (reg != oldreg && oldreg != 0) {
|
|
/* Remove the old settings. */
|
|
val = ti_gpio_read_4(sc, oldreg);
|
|
val &= ~TI_GPIO_MASK(irq);
|
|
ti_gpio_write_4(sc, oldreg, val);
|
|
}
|
|
TI_GPIO_UNLOCK(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_setup_intr(device_t dev, device_t child, struct resource *ires,
|
|
int flags, driver_filter_t *filt, driver_intr_t *handler,
|
|
void *arg, void **cookiep)
|
|
{
|
|
struct ti_gpio_softc *sc;
|
|
struct intr_event *event;
|
|
int pin, error;
|
|
|
|
sc = device_get_softc(dev);
|
|
pin = rman_get_start(ires);
|
|
if (ti_gpio_valid_pin(sc, pin) != 0)
|
|
panic("%s: bad pin %d", __func__, pin);
|
|
|
|
event = sc->sc_events[pin];
|
|
if (event == NULL) {
|
|
sc->sc_mask_args[pin].softc = sc;
|
|
sc->sc_mask_args[pin].pin = pin;
|
|
error = intr_event_create(&event, (void *)&sc->sc_mask_args[pin], 0,
|
|
pin, ti_gpio_mask_irq, ti_gpio_unmask_irq, NULL, NULL,
|
|
"gpio%d pin%d:", device_get_unit(dev), pin);
|
|
if (error != 0)
|
|
return (error);
|
|
sc->sc_events[pin] = event;
|
|
}
|
|
intr_event_add_handler(event, device_get_nameunit(child), filt,
|
|
handler, arg, intr_priority(flags), flags, cookiep);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_gpio_teardown_intr(device_t dev, device_t child, struct resource *ires,
|
|
void *cookie)
|
|
{
|
|
struct ti_gpio_softc *sc;
|
|
int pin, err;
|
|
|
|
sc = device_get_softc(dev);
|
|
pin = rman_get_start(ires);
|
|
if (ti_gpio_valid_pin(sc, pin) != 0)
|
|
panic("%s: bad pin %d", __func__, pin);
|
|
if (sc->sc_events[pin] == NULL)
|
|
panic("Trying to teardown unoccupied IRQ");
|
|
err = intr_event_remove_handler(cookie);
|
|
if (!err)
|
|
sc->sc_events[pin] = NULL;
|
|
|
|
return (err);
|
|
}
|
|
#endif
|
|
|
|
static phandle_t
|
|
ti_gpio_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/* We only have one child, the GPIO bus, which needs our own node. */
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static device_method_t ti_gpio_methods[] = {
|
|
DEVMETHOD(device_attach, ti_gpio_attach),
|
|
DEVMETHOD(device_detach, ti_gpio_detach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, ti_gpio_get_bus),
|
|
DEVMETHOD(gpio_pin_max, ti_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, ti_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, ti_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, ti_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, ti_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, ti_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, ti_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, ti_gpio_pin_toggle),
|
|
|
|
#ifdef INTRNG
|
|
/* Interrupt controller interface */
|
|
DEVMETHOD(pic_disable_intr, ti_gpio_pic_disable_intr),
|
|
DEVMETHOD(pic_enable_intr, ti_gpio_pic_enable_intr),
|
|
DEVMETHOD(pic_map_intr, ti_gpio_pic_map_intr),
|
|
DEVMETHOD(pic_setup_intr, ti_gpio_pic_setup_intr),
|
|
DEVMETHOD(pic_teardown_intr, ti_gpio_pic_teardown_intr),
|
|
DEVMETHOD(pic_post_filter, ti_gpio_pic_post_filter),
|
|
DEVMETHOD(pic_post_ithread, ti_gpio_pic_post_ithread),
|
|
DEVMETHOD(pic_pre_ithread, ti_gpio_pic_pre_ithread),
|
|
#else
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_activate_resource, ti_gpio_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, ti_gpio_deactivate_resource),
|
|
DEVMETHOD(bus_config_intr, ti_gpio_config_intr),
|
|
DEVMETHOD(bus_setup_intr, ti_gpio_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, ti_gpio_teardown_intr),
|
|
#endif
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, ti_gpio_get_node),
|
|
|
|
{0, 0},
|
|
};
|
|
|
|
driver_t ti_gpio_driver = {
|
|
"gpio",
|
|
ti_gpio_methods,
|
|
sizeof(struct ti_gpio_softc),
|
|
};
|