94bc2117b4
- Add CCM driver and clocks implementations for i.MX 8M - Add GPC driver for iMX8 - Add clock tree for i.MX 8M Quad - Add clocks support and new compat strings (where required) for existing i.MX 6 UART, I2C, and GPIO drivers - Enable aarch64-compatible drivers form i.MX 6 in arm64 GENERIC kernel config - Add dtb/imx8 kernel module with DTBs for Nitrogen8M and iMX8MQ EVK With this patch both Nitrogen8M and iMX8MQ EVK boot with NFS root up to multiuser login prompt Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D25274
264 lines
6.7 KiB
C
264 lines
6.7 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/proc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "pic_if.h"
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struct imx7gpc_softc {
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device_t dev;
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struct resource *memres;
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device_t parent;
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};
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static struct ofw_compat_data compat_data[] = {
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{ "fsl,imx7gpc", 1},
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{ "fsl,imx8mq-gpc", 1},
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{ NULL, 0}
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};
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static inline uint32_t
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imx7gpc_read_4(struct imx7gpc_softc *sc, int reg)
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{
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return (bus_read_4(sc->memres, reg));
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}
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static inline void
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imx7gpc_write_4(struct imx7gpc_softc *sc, int reg, uint32_t val)
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{
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bus_write_4(sc->memres, reg, val);
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}
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static int
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imx7gpc_activate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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return (PIC_ACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static void
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imx7gpc_disable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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PIC_DISABLE_INTR(sc->parent, isrc);
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}
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static void
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imx7gpc_enable_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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PIC_ENABLE_INTR(sc->parent, isrc);
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}
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static int
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imx7gpc_map_intr(device_t dev, struct intr_map_data *data,
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struct intr_irqsrc **isrcp)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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return (PIC_MAP_INTR(sc->parent, data, isrcp));
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}
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static int
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imx7gpc_deactivate_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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return (PIC_DEACTIVATE_INTR(sc->parent, isrc, res, data));
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}
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static int
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imx7gpc_setup_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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return (PIC_SETUP_INTR(sc->parent, isrc, res, data));
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}
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static int
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imx7gpc_teardown_intr(device_t dev, struct intr_irqsrc *isrc,
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struct resource *res, struct intr_map_data *data)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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return (PIC_TEARDOWN_INTR(sc->parent, isrc, res, data));
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}
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static void
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imx7gpc_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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PIC_PRE_ITHREAD(sc->parent, isrc);
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}
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static void
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imx7gpc_post_ithread(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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PIC_POST_ITHREAD(sc->parent, isrc);
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}
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static void
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imx7gpc_post_filter(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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PIC_POST_FILTER(sc->parent, isrc);
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}
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#ifdef SMP
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static int
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imx7gpc_bind_intr(device_t dev, struct intr_irqsrc *isrc)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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return (PIC_BIND_INTR(sc->parent, isrc));
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}
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#endif
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static int
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imx7gpc_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "General Power Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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imx7gpc_attach(device_t dev)
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{
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struct imx7gpc_softc *sc = device_get_softc(dev);
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phandle_t node;
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phandle_t parent_xref;
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int i, rv;
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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rv = OF_getencprop(node, "interrupt-parent", &parent_xref,
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sizeof(parent_xref));
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if (rv <= 0) {
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device_printf(dev, "Can't read parent node property\n");
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return (ENXIO);
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}
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sc->parent = OF_device_from_xref(parent_xref);
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if (sc->parent == NULL) {
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device_printf(dev, "Can't find parent controller\n");
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return (ENXIO);
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}
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i = 0;
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sc->memres = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &i,
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RF_ACTIVE);
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if (sc->memres == NULL) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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/* TODO: power up OTG domain and unmask all interrupts */
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if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
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bus_release_resource(dev, SYS_RES_MEMORY, i, sc->memres);
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device_printf(dev, "Cannot register PIC\n");
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return (ENXIO);
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}
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return (0);
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}
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static device_method_t imx7gpc_methods[] = {
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DEVMETHOD(device_probe, imx7gpc_probe),
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DEVMETHOD(device_attach, imx7gpc_attach),
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/* Interrupt controller interface */
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DEVMETHOD(pic_activate_intr, imx7gpc_activate_intr),
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DEVMETHOD(pic_disable_intr, imx7gpc_disable_intr),
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DEVMETHOD(pic_enable_intr, imx7gpc_enable_intr),
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DEVMETHOD(pic_map_intr, imx7gpc_map_intr),
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DEVMETHOD(pic_deactivate_intr, imx7gpc_deactivate_intr),
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DEVMETHOD(pic_setup_intr, imx7gpc_setup_intr),
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DEVMETHOD(pic_teardown_intr, imx7gpc_teardown_intr),
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DEVMETHOD(pic_pre_ithread, imx7gpc_pre_ithread),
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DEVMETHOD(pic_post_ithread, imx7gpc_post_ithread),
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DEVMETHOD(pic_post_filter, imx7gpc_post_filter),
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#ifdef SMP
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DEVMETHOD(pic_bind_intr, imx7gpc_bind_intr),
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#endif
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DEVMETHOD_END
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};
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static driver_t imx7gpc_driver = {
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"imx7gpc",
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imx7gpc_methods,
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sizeof(struct imx7gpc_softc),
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};
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static devclass_t imx7gpc_devclass;
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EARLY_DRIVER_MODULE(imx7gpc, ofwbus, imx7gpc_driver, imx7gpc_devclass, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
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EARLY_DRIVER_MODULE(imx7gpc, simplebus, imx7gpc_driver, imx7gpc_devclass, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE);
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