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is that the JBus to EBus bridges share the interrupt controller of a sibling JBus to PCIe bridge (at least as far as the OFW device tree is concerned, in reality they are part of the same chip) so we have to probe and attach the latter first. That happens to be also the case due to the fact that the JBus to PCIe bridges appear first in the OFW device tree but it doesn't hurt to ensure the right order. |
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|---|---|---|
| .. | ||
| apb.c | ||
| ofw_pci.h | ||
| ofw_pcib_subr.c | ||
| ofw_pcib_subr.h | ||
| ofw_pcib.c | ||
| ofw_pcibus.c | ||
| psycho.c | ||
| psychoreg.h | ||
| psychovar.h | ||
| schizo.c | ||
| schizoreg.h | ||
| schizovar.h | ||