328 lines
8.0 KiB
C
328 lines
8.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2019 Michal Meloun <mmel@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* Armada 8k DesignWare PCIe driver */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/devmap.h>
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#include <sys/proc.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <machine/intr.h>
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#include <machine/resource.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/ofw/ofw_pci.h>
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#include <dev/ofw/ofwpci.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcib_private.h>
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#include <dev/pci/pci_dw.h>
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#include "pcib_if.h"
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#include "pci_dw_if.h"
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#define MV_GLOBAL_CONTROL_REG 0x8000
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#define PCIE_APP_LTSSM_EN (1 << 2)
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//#define PCIE_DEVICE_TYPE_SHIFT 4
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//#define PCIE_DEVICE_TYPE_MASK 0xF
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//#define PCIE_DEVICE_TYPE_RC 0x4/
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#define MV_GLOBAL_STATUS_REG 0x8008
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#define MV_STATUS_RDLH_LINK_UP (1 << 1)
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#define MV_STATUS_PHY_LINK_UP (1 << 9)
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#define MV_INT_CAUSE1 0x801C
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#define MV_INT_MASK1 0x8020
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#define INT_A_ASSERT_MASK (1 << 9)
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#define INT_B_ASSERT_MASK (1 << 10)
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#define INT_C_ASSERT_MASK (1 << 11)
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#define INT_D_ASSERT_MASK (1 << 12)
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#define MV_INT_CAUSE2 0x8024
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#define MV_INT_MASK2 0x8028
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#define MV_ERR_INT_CAUSE 0x802C
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#define MV_ERR_INT_MASK 0x8030
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#define MV_ARCACHE_TRC_REG 0x8050
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#define MV_AWCACHE_TRC_REG 0x8054
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#define MV_ARUSER_REG 0x805C
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#define MV_AWUSER_REG 0x8060
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#define MV_MAX_LANES 8
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struct pci_mv_softc {
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struct pci_dw_softc dw_sc;
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device_t dev;
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phandle_t node;
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struct resource *irq_res;
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void *intr_cookie;
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phy_t phy[MV_MAX_LANES];
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clk_t clk_core;
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clk_t clk_reg;
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};
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/* Compatible devices. */
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static struct ofw_compat_data compat_data[] = {
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{"marvell,armada8k-pcie", 1},
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{NULL, 0},
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};
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static int
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pci_mv_phy_init(struct pci_mv_softc *sc)
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{
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int i, rv;
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for (i = 0; i < MV_MAX_LANES; i++) {
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rv = phy_get_by_ofw_idx(sc->dev, sc->node, i, &(sc->phy[i]));
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if (rv != 0 && rv != ENOENT) {
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device_printf(sc->dev, "Cannot get phy[%d]\n", i);
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goto fail;
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}
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if (sc->phy[i] == NULL)
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continue;
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rv = phy_enable(sc->phy[i]);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot enable phy[%d]\n", i);
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goto fail;
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}
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}
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return (0);
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fail:
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for (i = 0; i < MV_MAX_LANES; i++) {
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if (sc->phy[i] == NULL)
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continue;
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phy_release(sc->phy[i]);
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}
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return (rv);
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}
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static void
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pci_mv_init(struct pci_mv_softc *sc)
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{
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uint32_t reg;
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/* Set device configuration to RC */
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reg = pci_dw_dbi_rd4(sc->dev, MV_GLOBAL_CONTROL_REG);
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reg &= ~0x000000F0;
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reg |= 0x000000040;
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pci_dw_dbi_wr4(sc->dev, MV_GLOBAL_CONTROL_REG, reg);
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/* AxCache master transaction attribures */
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pci_dw_dbi_wr4(sc->dev, MV_ARCACHE_TRC_REG, 0x3511);
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pci_dw_dbi_wr4(sc->dev, MV_AWCACHE_TRC_REG, 0x5311);
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/* AxDomain master transaction attribures */
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pci_dw_dbi_wr4(sc->dev, MV_ARUSER_REG, 0x0002);
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pci_dw_dbi_wr4(sc->dev, MV_AWUSER_REG, 0x0002);
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/* Enable all INTx interrupt (virtuual) pins */
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reg = pci_dw_dbi_rd4(sc->dev, MV_INT_MASK1);
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reg |= INT_A_ASSERT_MASK | INT_B_ASSERT_MASK |
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INT_C_ASSERT_MASK | INT_D_ASSERT_MASK;
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pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, reg);
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/* Enable local interrupts */
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pci_dw_dbi_wr4(sc->dev, DW_MSI_INTR0_MASK, 0xFFFFFFFF);
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pci_dw_dbi_wr4(sc->dev, MV_INT_MASK1, 0xFFFFFFFF);
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pci_dw_dbi_wr4(sc->dev, MV_INT_MASK2, 0xFFFFFFFF);
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pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, 0xFFFFFFFF);
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pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, 0xFFFFFFFF);
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/* Errors have own interrupt, not yet populated in DTt */
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pci_dw_dbi_wr4(sc->dev, MV_ERR_INT_MASK, 0);
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}
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static int pci_mv_intr(void *arg)
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{
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struct pci_mv_softc *sc = arg;
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uint32_t cause1, cause2;
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/* Ack all interrups */
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cause1 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE1);
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cause2 = pci_dw_dbi_rd4(sc->dev, MV_INT_CAUSE2);
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if (cause1 == 0 || cause2 == 0)
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return(FILTER_STRAY);
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pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE1, cause1);
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pci_dw_dbi_wr4(sc->dev, MV_INT_CAUSE2, cause2);
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return (FILTER_HANDLED);
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}
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static int
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pci_mv_get_link(device_t dev, bool *status)
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{
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uint32_t reg;
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reg = pci_dw_dbi_rd4(dev, MV_GLOBAL_STATUS_REG);
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if ((reg & (MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP)) ==
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(MV_STATUS_RDLH_LINK_UP | MV_STATUS_PHY_LINK_UP))
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*status = true;
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else
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*status = false;
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return (0);
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}
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static int
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pci_mv_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell Armada8K PCI-E Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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pci_mv_attach(device_t dev)
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{
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struct pci_mv_softc *sc;
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phandle_t node;
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int rv;
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int rid;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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sc->dev = dev;
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sc->node = node;
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rid = 0;
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sc->dw_sc.dbi_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (sc->dw_sc.dbi_res == NULL) {
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device_printf(dev, "Cannot allocate DBI memory\n");
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rv = ENXIO;
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goto out;
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}
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/* PCI interrupt */
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rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Cannot allocate IRQ resources\n");
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rv = ENXIO;
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goto out;
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}
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/* Clocks */
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rv = clk_get_by_ofw_name(sc->dev, 0, "core", &sc->clk_core);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'core' clock\n");
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rv = ENXIO;
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goto out;
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}
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rv = clk_get_by_ofw_name(sc->dev, 0, "reg", &sc->clk_reg);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'reg' clock\n");
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rv = ENXIO;
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goto out;
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}
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rv = clk_enable(sc->clk_core);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot enable 'core' clock\n");
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rv = ENXIO;
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goto out;
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}
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rv = clk_enable(sc->clk_reg);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot enable 'reg' clock\n");
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rv = ENXIO;
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goto out;
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}
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rv = pci_mv_phy_init(sc);
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if (rv)
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goto out;
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rv = pci_dw_init(dev);
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if (rv != 0)
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goto out;
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pci_mv_init(sc);
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/* Setup interrupt */
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if (bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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pci_mv_intr, NULL, sc, &sc->intr_cookie)) {
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device_printf(dev, "cannot setup interrupt handler\n");
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rv = ENXIO;
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goto out;
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}
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return (bus_generic_attach(dev));
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out:
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/* XXX Cleanup */
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return (rv);
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}
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static device_method_t pci_mv_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, pci_mv_probe),
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DEVMETHOD(device_attach, pci_mv_attach),
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DEVMETHOD(pci_dw_get_link, pci_mv_get_link),
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DEVMETHOD_END
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};
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DEFINE_CLASS_1(pcib, pci_mv_driver, pci_mv_methods,
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sizeof(struct pci_mv_softc), pci_dw_driver);
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static devclass_t pci_mv_devclass;
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DRIVER_MODULE( pci_mv, simplebus, pci_mv_driver, pci_mv_devclass,
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NULL, NULL); |