506 lines
12 KiB
C
506 lines
12 KiB
C
/*-
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* ----------------------------------------------------------------------------
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* "THE BEER-WARE LICENSE" (Revision 42):
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* <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
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* can do whatever you want with this stuff. If we meet some day, and you think
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* this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
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* ----------------------------------------------------------------------------
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*
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*
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* The AMD Elan sc520 is a system-on-chip gadget which is used in embedded
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* kind of things, see www.soekris.com for instance, and it has a few quirks
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* we need to deal with.
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* Unfortunately we cannot identify the gadget by CPUID output because it
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* depends on strapping options and only the stepping field may be useful
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* and those are undocumented from AMDs side.
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*
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* So instead we recognize the on-chip host-PCI bridge and call back from
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* sys/i386/pci/pci_bus.c to here if we find it.
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*
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* #ifdef CPU_ELAN_PPS
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* The Elan has three general purpose counters, and when two of these
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* are used just right they can hardware timestamp external events with
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* approx 125 nsec resolution and +/- 125 nsec precision.
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*
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* Connect the signal to TMR1IN and a GPIO pin, and configure the GPIO pin
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* with a 'P' in sysctl machdep.elan_gpio_config.
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*
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* The rising edge of the signal will start timer 1 counting up from
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* zero, and when the timecounter polls for PPS, both counter 1 & 2 is
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* read, as well as the GPIO bit. If a rising edge has happened, the
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* contents of timer 1 which is how long time ago the edge happened,
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* is subtracted from timer 2 to give us a "true time stamp".
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*
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* Echoing the PPS signal on any GPIO pin is supported (set it to 'e'
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* or 'E' (inverted) in the sysctl) The echo signal should only be
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* used as a visual indication, not for calibration since it suffers
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* from 1/hz (or more) jitter which the timestamps are compensated for.
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* #endif CPU_ELAN_PPS
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/conf.h>
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#include <sys/sysctl.h>
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#include <sys/syslog.h>
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#include <sys/timetc.h>
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#include <sys/proc.h>
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#include <sys/uio.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/malloc.h>
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#include <sys/sysctl.h>
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#include <sys/timepps.h>
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#include <sys/watchdog.h>
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#include <dev/led/led.h>
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#include <machine/md_var.h>
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#include <machine/elan_mmcr.h>
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#include <machine/pc/bios.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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static char gpio_config[33];
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static volatile uint16_t *mmcrptr;
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volatile struct elan_mmcr *elan_mmcr;
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#ifdef CPU_ELAN_PPS
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static struct pps_state elan_pps;
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static volatile uint16_t *pps_ap[3];
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static u_int pps_a, pps_d;
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static u_int echo_a, echo_d;
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#endif /* CPU_ELAN_PPS */
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#ifdef CPU_SOEKRIS
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static struct bios_oem bios_soekris = {
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{ 0xf0000, 0xf1000 },
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{
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{ "Soekris", 0, 8 }, /* Soekris Engineering. */
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{ "net4", 0, 8 }, /* net45xx */
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{ "comBIOS", 0, 54 }, /* comBIOS ver. 1.26a 20040819 ... */
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{ NULL, 0, 0 },
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}
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};
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#endif
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static u_int led_cookie[32];
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static struct cdev *led_dev[32];
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static void
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gpio_led(void *cookie, int state)
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{
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u_int u, v;
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u = *(int *)cookie;
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v = u & 0xffff;
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u >>= 16;
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if (!state)
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v ^= 0xc;
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mmcrptr[v / 2] = u;
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}
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static int
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sysctl_machdep_elan_gpio_config(SYSCTL_HANDLER_ARGS)
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{
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u_int u, v;
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int i, np, ne;
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int error;
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char buf[32];
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char tmp[10];
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error = SYSCTL_OUT(req, gpio_config, 33);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (req->newlen != 32)
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return (EINVAL);
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error = SYSCTL_IN(req, buf, 32);
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if (error != 0)
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return (error);
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/* Disallow any disabled pins and count pps and echo */
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np = ne = 0;
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for (i = 0; i < 32; i++) {
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if (gpio_config[i] == '-' && buf[i] == '.')
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buf[i] = gpio_config[i];
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if (gpio_config[i] == '-' && buf[i] != '-')
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return (EPERM);
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if (buf[i] == 'P') {
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np++;
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if (np > 1)
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return (EINVAL);
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}
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if (buf[i] == 'e' || buf[i] == 'E') {
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ne++;
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if (ne > 1)
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return (EINVAL);
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}
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if (buf[i] != 'L' && buf[i] != 'l'
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#ifdef CPU_ELAN_PPS
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&& buf[i] != 'P' && buf[i] != 'E' && buf[i] != 'e'
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#endif /* CPU_ELAN_PPS */
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&& buf[i] != '.' && buf[i] != '-')
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return (EINVAL);
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}
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#ifdef CPU_ELAN_PPS
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if (np == 0)
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pps_a = pps_d = 0;
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if (ne == 0)
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echo_a = echo_d = 0;
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#endif
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for (i = 0; i < 32; i++) {
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u = 1 << (i & 0xf);
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if (i >= 16)
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v = 2;
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else
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v = 0;
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#ifdef CPU_SOEKRIS
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if (i == 9)
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;
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else
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#endif
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if (buf[i] != 'l' && buf[i] != 'L' && led_dev[i] != NULL) {
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led_destroy(led_dev[i]);
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led_dev[i] = NULL;
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mmcrptr[(0xc2a + v) / 2] &= ~u;
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}
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switch (buf[i]) {
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#ifdef CPU_ELAN_PPS
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case 'P':
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pps_d = u;
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pps_a = 0xc30 + v;
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pps_ap[0] = &mmcrptr[pps_a / 2];
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pps_ap[1] = &elan_mmcr->GPTMR2CNT;
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pps_ap[2] = &elan_mmcr->GPTMR1CNT;
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mmcrptr[(0xc2a + v) / 2] &= ~u;
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gpio_config[i] = buf[i];
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break;
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case 'e':
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case 'E':
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echo_d = u;
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if (buf[i] == 'E')
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echo_a = 0xc34 + v;
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else
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echo_a = 0xc38 + v;
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mmcrptr[(0xc2a + v) / 2] |= u;
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gpio_config[i] = buf[i];
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break;
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#endif /* CPU_ELAN_PPS */
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case 'l':
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case 'L':
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if (buf[i] == 'L')
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led_cookie[i] = (0xc34 + v) | (u << 16);
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else
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led_cookie[i] = (0xc38 + v) | (u << 16);
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if (led_dev[i])
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break;
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sprintf(tmp, "gpio%d", i);
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mmcrptr[(0xc2a + v) / 2] |= u;
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gpio_config[i] = buf[i];
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led_dev[i] =
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led_create(gpio_led, &led_cookie[i], tmp);
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break;
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case '.':
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gpio_config[i] = buf[i];
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break;
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case '-':
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default:
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break;
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}
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}
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return (0);
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}
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SYSCTL_OID(_machdep, OID_AUTO, elan_gpio_config, CTLTYPE_STRING | CTLFLAG_RW,
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NULL, 0, sysctl_machdep_elan_gpio_config, "A", "Elan CPU GPIO pin config");
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#ifdef CPU_ELAN_PPS
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static void
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elan_poll_pps(struct timecounter *tc)
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{
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static int state;
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int i;
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uint16_t u, x, y, z;
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register_t saveintr;
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/*
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* Grab the HW state as quickly and compactly as we can. Disable
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* interrupts to avoid measuring our interrupt service time on
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* hw with quality clock sources.
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*/
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saveintr = intr_disable();
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x = *pps_ap[0]; /* state, must be first, see below */
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y = *pps_ap[1]; /* timer2 */
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z = *pps_ap[2]; /* timer1 */
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intr_restore(saveintr);
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/*
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* Order is important here. We need to check the state of the GPIO
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* pin first, in order to avoid reading timer 1 right before the
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* state change. Technically pps_a may be zero in which case we
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* harmlessly read the REVID register and the contents of pps_d is
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* of no concern.
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*/
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i = x & pps_d;
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/* If state did not change or we don't have a GPIO pin, return */
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if (i == state || pps_a == 0)
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return;
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state = i;
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/* If the state is "low", flip the echo GPIO and return. */
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if (!i) {
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if (echo_a)
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mmcrptr[(echo_a ^ 0xc) / 2] = echo_d;
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return;
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}
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/*
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* Subtract timer1 from timer2 to compensate for time from the
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* edge until we read the counters.
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*/
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u = y - z;
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pps_capture(&elan_pps);
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elan_pps.capcount = u;
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pps_event(&elan_pps, PPS_CAPTUREASSERT);
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/* Twiddle echo bit */
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if (echo_a)
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mmcrptr[echo_a / 2] = echo_d;
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}
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#endif /* CPU_ELAN_PPS */
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static unsigned
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elan_get_timecount(struct timecounter *tc)
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{
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/* Read timer2, end of story */
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return (elan_mmcr->GPTMR2CNT);
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}
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/*
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* The Elan CPU can be run from a number of clock frequencies, this
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* allows you to override the default 33.3 MHZ.
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*/
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#ifndef CPU_ELAN_XTAL
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#define CPU_ELAN_XTAL 33333333
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#endif
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static struct timecounter elan_timecounter = {
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elan_get_timecount,
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NULL,
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0xffff,
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CPU_ELAN_XTAL / 4,
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"ELAN",
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1000
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};
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static int
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sysctl_machdep_elan_freq(SYSCTL_HANDLER_ARGS)
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{
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u_int f;
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int error;
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f = elan_timecounter.tc_frequency * 4;
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error = sysctl_handle_int(oidp, &f, 0, req);
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if (error == 0 && req->newptr != NULL)
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elan_timecounter.tc_frequency = (f + 3) / 4;
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return (error);
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}
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SYSCTL_PROC(_machdep, OID_AUTO, elan_freq, CTLTYPE_UINT | CTLFLAG_RW,
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0, sizeof (u_int), sysctl_machdep_elan_freq, "IU", "");
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/*
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* Positively identifying the Elan can only be done through the PCI id of
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* the host-bridge, this function is called from i386/pci/pci_bus.c.
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*/
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void
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init_AMD_Elan_sc520(void)
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{
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u_int new;
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int i;
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mmcrptr = pmap_mapdev(0xfffef000, 0x1000);
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elan_mmcr = (volatile struct elan_mmcr *)mmcrptr;
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/*-
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* The i8254 is driven with a nonstandard frequency which is
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* derived thusly:
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* f = 32768 * 45 * 25 / 31 = 1189161.29...
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* We use the sysctl to get the i8254 (timecounter etc) into whack.
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*/
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new = 1189161;
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i = kernel_sysctlbyname(&thread0, "machdep.i8254_freq",
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NULL, 0, &new, sizeof new, NULL, 0);
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if (bootverbose || 1)
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printf("sysctl machdep.i8254_freq=%d returns %d\n", new, i);
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/* Start GP timer #2 and use it as timecounter, hz permitting */
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elan_mmcr->GPTMR2MAXCMPA = 0;
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elan_mmcr->GPTMR2CTL = 0xc001;
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#ifdef CPU_ELAN_PPS
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/* Set up GP timer #1 as pps counter */
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elan_mmcr->CSPFS &= ~0x10;
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elan_mmcr->GPTMR1CTL = 0x8000 | 0x4000 | 0x10 | 0x1;
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elan_mmcr->GPTMR1MAXCMPA = 0x0;
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elan_mmcr->GPTMR1MAXCMPB = 0x0;
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elan_pps.ppscap |= PPS_CAPTUREASSERT;
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pps_init(&elan_pps);
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#endif
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tc_init(&elan_timecounter);
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}
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static void
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elan_watchdog(void *foo __unused, u_int spec, int *error)
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{
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u_int u, v, w;
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static u_int cur;
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u = spec & WD_INTERVAL;
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if (u > 0 && u <= 35) {
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u = imax(u - 5, 24);
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v = 2 << (u - 24);
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v |= 0xc000;
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/*
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* There is a bug in some silicon which prevents us from
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* writing to the WDTMRCTL register if the GP echo mode is
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* enabled. GP echo mode on the other hand is desirable
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* for other reasons. Save and restore the GP echo mode
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* around our hardware tom-foolery.
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*/
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w = elan_mmcr->GPECHO;
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elan_mmcr->GPECHO = 0;
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if (v != cur) {
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/* Clear the ENB bit */
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elan_mmcr->WDTMRCTL = 0x3333;
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elan_mmcr->WDTMRCTL = 0xcccc;
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elan_mmcr->WDTMRCTL = 0;
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/* Set new value */
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elan_mmcr->WDTMRCTL = 0x3333;
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elan_mmcr->WDTMRCTL = 0xcccc;
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elan_mmcr->WDTMRCTL = v;
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cur = v;
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} else {
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/* Just reset timer */
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elan_mmcr->WDTMRCTL = 0xaaaa;
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elan_mmcr->WDTMRCTL = 0x5555;
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}
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elan_mmcr->GPECHO = w;
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*error = 0;
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} else {
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w = elan_mmcr->GPECHO;
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elan_mmcr->GPECHO = 0;
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elan_mmcr->WDTMRCTL = 0x3333;
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elan_mmcr->WDTMRCTL = 0xcccc;
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elan_mmcr->WDTMRCTL = 0x4080;
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elan_mmcr->WDTMRCTL = w; /* XXX What does this statement do? */
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elan_mmcr->GPECHO = w;
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cur = 0;
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}
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}
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static int
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elan_mmap(struct cdev *dev, vm_ooffset_t offset, vm_paddr_t *paddr,
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int nprot, vm_memattr_t *memattr)
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{
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if (offset >= 0x1000)
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return (-1);
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*paddr = 0xfffef000;
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return (0);
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}
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static int
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elan_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag, struct thread *tdr)
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{
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int error;
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error = ENOIOCTL;
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#ifdef CPU_ELAN_PPS
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if (pps_a != 0)
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error = pps_ioctl(cmd, arg, &elan_pps);
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/*
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* We only want to incur the overhead of the PPS polling if we
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* are actually asked to timestamp.
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*/
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if (elan_pps.ppsparam.mode & PPS_CAPTUREASSERT) {
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elan_timecounter.tc_poll_pps = elan_poll_pps;
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} else {
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elan_timecounter.tc_poll_pps = NULL;
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}
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if (error != ENOIOCTL)
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return (error);
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#endif
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return(error);
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}
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static struct cdevsw elan_cdevsw = {
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.d_version = D_VERSION,
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.d_flags = D_NEEDGIANT,
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.d_ioctl = elan_ioctl,
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.d_mmap = elan_mmap,
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.d_name = "elan",
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};
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static void
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elan_drvinit(void)
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{
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#ifdef CPU_SOEKRIS
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#define BIOS_OEM_MAXLEN 72
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static u_char bios_oem[BIOS_OEM_MAXLEN] = "\0";
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#endif /* CPU_SOEKRIS */
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/* If no elan found, just return */
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if (mmcrptr == NULL)
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return;
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printf("Elan-mmcr driver: MMCR at %p.%s\n",
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mmcrptr,
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#ifdef CPU_ELAN_PPS
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" PPS support."
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#else
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""
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#endif
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);
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make_dev(&elan_cdevsw, 0,
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UID_ROOT, GID_WHEEL, 0600, "elan-mmcr");
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#ifdef CPU_SOEKRIS
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if ( bios_oem_strings(&bios_soekris, bios_oem, BIOS_OEM_MAXLEN) > 0 )
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printf("Elan-mmcr %s\n", bios_oem);
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/* Create the error LED on GPIO9 */
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led_cookie[9] = 0x02000c34;
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led_dev[9] = led_create(gpio_led, &led_cookie[9], "error");
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/* Disable the unavailable GPIO pins */
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strcpy(gpio_config, "-----....--..--------..---------");
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#else /* !CPU_SOEKRIS */
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/* We don't know which pins are available so enable them all */
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strcpy(gpio_config, "................................");
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#endif /* CPU_SOEKRIS */
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EVENTHANDLER_REGISTER(watchdog_list, elan_watchdog, NULL, 0);
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}
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SYSINIT(elan, SI_SUB_PSEUDO, SI_ORDER_MIDDLE, elan_drvinit, NULL);
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