366 lines
11 KiB
C
366 lines
11 KiB
C
/*-
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* Copyright (c) 2007 Sepherosa Ziehau. All rights reserved.
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*
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* This code is derived from software contributed to The DragonFly Project
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* by Sepherosa Ziehau <sepherosa@gmail.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name of The DragonFly Project nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific, prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
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* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $DragonFly: src/sys/dev/netif/et/if_etreg.h,v 1.3 2007/10/23 14:28:42 sephe Exp $
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* $FreeBSD$
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*/
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#ifndef _IF_ETREG_H
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#define _IF_ETREG_H
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#define ET_MEM_TXSIZE_EX 182
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#define ET_MEM_RXSIZE_MIN 608
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#define ET_MEM_RXSIZE_DEFAULT 11216
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#define ET_MEM_SIZE 16384
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#define ET_MEM_UNIT 16
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/*
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* PCI registers
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*
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* ET_PCIV_ACK_LATENCY_{128,256} are from
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* PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-5
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*
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* ET_PCIV_REPLAY_TIMER_{128,256} are from
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* PCI EXPRESS BASE SPECIFICATION, REV. 1.0a, Table 3-4
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*/
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#define ET_PCIR_BAR PCIR_BAR(0)
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#define ET_PCIR_DEVICE_CAPS 0x4c
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#define ET_PCIM_DEVICE_CAPS_MAX_PLSZ 0x7 /* Max playload size */
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#define ET_PCIV_DEVICE_CAPS_PLSZ_128 0x0
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#define ET_PCIV_DEVICE_CAPS_PLSZ_256 0x1
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#define ET_PCIR_DEVICE_CTRL 0x50
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#define ET_PCIM_DEVICE_CTRL_MAX_RRSZ 0x7000 /* Max read request size */
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#define ET_PCIV_DEVICE_CTRL_RRSZ_2K 0x4000
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#define ET_PCIR_MAC_ADDR0 0xa4
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#define ET_PCIR_MAC_ADDR1 0xa8
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#define ET_PCIR_EEPROM_STATUS 0xb2 /* XXX undocumented */
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#define ET_PCIM_EEPROM_STATUS_ERROR 0x4c
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#define ET_PCIR_ACK_LATENCY 0xc0
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#define ET_PCIV_ACK_LATENCY_128 237
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#define ET_PCIV_ACK_LATENCY_256 416
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#define ET_PCIR_REPLAY_TIMER 0xc2
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#define ET_REPLAY_TIMER_RX_L0S_ADJ 250 /* XXX infered from default */
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#define ET_PCIV_REPLAY_TIMER_128 (711 + ET_REPLAY_TIMER_RX_L0S_ADJ)
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#define ET_PCIV_REPLAY_TIMER_256 (1248 + ET_REPLAY_TIMER_RX_L0S_ADJ)
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#define ET_PCIR_L0S_L1_LATENCY 0xcf
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/*
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* CSR
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*/
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#define ET_TXQUEUE_START 0x0000
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#define ET_TXQUEUE_END 0x0004
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#define ET_RXQUEUE_START 0x0008
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#define ET_RXQUEUE_END 0x000c
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#define ET_QUEUE_ADDR(addr) (((addr) / ET_MEM_UNIT) - 1)
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#define ET_QUEUE_ADDR_START 0
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#define ET_QUEUE_ADDR_END ET_QUEUE_ADDR(ET_MEM_SIZE)
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#define ET_PM 0x0010
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#define ET_PM_SYSCLK_GATE 0x00000008
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#define ET_PM_TXCLK_GATE 0x00000010
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#define ET_PM_RXCLK_GATE 0x00000020
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#define ET_INTR_STATUS 0x0018
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#define ET_INTR_MASK 0x001c
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#define ET_SWRST 0x0028
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#define ET_SWRST_TXDMA 0x00000001
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#define ET_SWRST_RXDMA 0x00000002
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#define ET_SWRST_TXMAC 0x00000004
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#define ET_SWRST_RXMAC 0x00000008
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#define ET_SWRST_MAC 0x00000010
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#define ET_SWRST_MAC_STAT 0x00000020
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#define ET_SWRST_MMC 0x00000040
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#define ET_SWRST_SELFCLR_DISABLE 0x80000000
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#define ET_MSI_CFG 0x0030
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#define ET_LOOPBACK 0x0034
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#define ET_TIMER 0x0038
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#define ET_TXDMA_CTRL 0x1000
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#define ET_TXDMA_CTRL_HALT 0x00000001
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#define ET_TXDMA_CTRL_CACHE_THR_MASK 0x000000F0
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#define ET_TXDMA_CTRL_SINGLE_EPKT 0x00000100 /* ??? */
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#define ET_TX_RING_HI 0x1004
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#define ET_TX_RING_LO 0x1008
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#define ET_TX_RING_CNT 0x100c
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#define ET_TX_STATUS_HI 0x101c
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#define ET_TX_STATUS_LO 0x1020
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#define ET_TX_READY_POS 0x1024
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#define ET_TX_READY_POS_INDEX_MASK 0x000003FF
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#define ET_TX_READY_POS_WRAP 0x00000400
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#define ET_TX_DONE_POS 0x1060
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#define ET_TX_DONE_POS_INDEX_MASK 0x0000003FF
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#define ET_TX_DONE_POS_WRAP 0x000000400
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#define ET_RXDMA_CTRL 0x2000
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#define ET_RXDMA_CTRL_HALT 0x00000001
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#define ET_RXDMA_CTRL_RING0_SIZE_MASK 0x00000300
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#define ET_RXDMA_CTRL_RING0_128 0x00000000 /* 127 */
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#define ET_RXDMA_CTRL_RING0_256 0x00000100 /* 255 */
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#define ET_RXDMA_CTRL_RING0_512 0x00000200 /* 511 */
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#define ET_RXDMA_CTRL_RING0_1024 0x00000300 /* 1023 */
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#define ET_RXDMA_CTRL_RING0_ENABLE 0x00000400
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#define ET_RXDMA_CTRL_RING1_SIZE_MASK 0x00001800
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#define ET_RXDMA_CTRL_RING1_2048 0x00000000 /* 2047 */
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#define ET_RXDMA_CTRL_RING1_4096 0x00000800 /* 4095 */
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#define ET_RXDMA_CTRL_RING1_8192 0x00001000 /* 8191 */
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#define ET_RXDMA_CTRL_RING1_16384 0x00001800 /* 16383 (9022?) */
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#define ET_RXDMA_CTRL_RING1_ENABLE 0x00002000
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#define ET_RXDMA_CTRL_HALTED 0x00020000
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#define ET_RX_STATUS_LO 0x2004
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#define ET_RX_STATUS_HI 0x2008
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#define ET_RX_INTR_NPKTS 0x200c
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#define ET_RX_INTR_DELAY 0x2010
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#define ET_RXSTAT_LO 0x2020
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#define ET_RXSTAT_HI 0x2024
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#define ET_RXSTAT_CNT 0x2028
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#define ET_RXSTAT_POS 0x2030
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#define ET_RXSTAT_POS_INDEX_MASK 0x00000FFF
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#define ET_RXSTAT_POS_WRAP 0x00001000
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#define ET_RXSTAT_MINCNT 0x2038
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#define ET_RX_RING0_LO 0x203c
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#define ET_RX_RING0_HI 0x2040
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#define ET_RX_RING0_CNT 0x2044
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#define ET_RX_RING0_POS 0x204c
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#define ET_RX_RING0_POS_INDEX_MASK 0x000003FF
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#define ET_RX_RING0_POS_WRAP 0x00000400
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#define ET_RX_RING0_MINCNT 0x2054
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#define ET_RX_RING1_LO 0x2058
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#define ET_RX_RING1_HI 0x205c
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#define ET_RX_RING1_CNT 0x2060
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#define ET_RX_RING1_POS 0x2068
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#define ET_RX_RING1_POS_INDEX 0x000003FF
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#define ET_RX_RING1_POS_WRAP 0x00000400
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#define ET_RX_RING1_MINCNT 0x2070
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#define ET_TXMAC_CTRL 0x3000
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#define ET_TXMAC_CTRL_ENABLE 0x00000001
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#define ET_TXMAC_CTRL_FC_DISABLE 0x00000008
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#define ET_TXMAC_FLOWCTRL 0x3010
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#define ET_RXMAC_CTRL 0x4000
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#define ET_RXMAC_CTRL_ENABLE 0x00000001
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#define ET_RXMAC_CTRL_NO_PKTFILT 0x00000004
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#define ET_RXMAC_CTRL_WOL_DISABLE 0x00000008
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#define ET_WOL_CRC 0x4004
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#define ET_WOL_SA_LO 0x4010
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#define ET_WOL_SA_HI 0x4014
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#define ET_WOL_MASK 0x4018
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#define ET_UCAST_FILTADDR1 0x4068
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#define ET_UCAST_FILTADDR2 0x406c
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#define ET_UCAST_FILTADDR3 0x4070
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#define ET_MULTI_HASH 0x4074
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#define ET_PKTFILT 0x4084
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#define ET_PKTFILT_BCAST 0x00000001
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#define ET_PKTFILT_MCAST 0x00000002
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#define ET_PKTFILT_UCAST 0x00000004
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#define ET_PKTFILT_FRAG 0x00000008
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#define ET_PKTFILT_MINLEN_MASK 0x007F0000
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#define ET_PKTFILT_MINLEN_SHIFT 16
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#define ET_RXMAC_MC_SEGSZ 0x4088
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#define ET_RXMAC_MC_SEGSZ_ENABLE 0x00000001
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#define ET_RXMAC_MC_SEGSZ_FC 0x00000002
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#define ET_RXMAC_MC_SEGSZ_MAX_MASK 0x000003FC
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#define ET_RXMAC_SEGSZ(segsz) ((segsz) / ET_MEM_UNIT)
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#define ET_RXMAC_CUT_THRU_FRMLEN 8074
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#define ET_RXMAC_MC_WATERMARK 0x408c
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#define ET_RXMAC_SPACE_AVL 0x4094
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#define ET_RXMAC_MGT 0x4098
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#define ET_RXMAC_MGT_PASS_ECRC 0x00000010
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#define ET_RXMAC_MGT_PASS_ELEN 0x00000020
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#define ET_RXMAC_MGT_PASS_ETRUNC 0x00010000
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#define ET_RXMAC_MGT_CHECK_PKT 0x00020000
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#define ET_MAC_CFG1 0x5000
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#define ET_MAC_CFG1_TXEN 0x00000001
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#define ET_MAC_CFG1_SYNC_TXEN 0x00000002
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#define ET_MAC_CFG1_RXEN 0x00000004
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#define ET_MAC_CFG1_SYNC_RXEN 0x00000008
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#define ET_MAC_CFG1_TXFLOW 0x00000010
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#define ET_MAC_CFG1_RXFLOW 0x00000020
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#define ET_MAC_CFG1_LOOPBACK 0x00000100
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#define ET_MAC_CFG1_RST_TXFUNC 0x00010000
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#define ET_MAC_CFG1_RST_RXFUNC 0x00020000
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#define ET_MAC_CFG1_RST_TXMC 0x00040000
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#define ET_MAC_CFG1_RST_RXMC 0x00080000
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#define ET_MAC_CFG1_SIM_RST 0x40000000
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#define ET_MAC_CFG1_SOFT_RST 0x80000000
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#define ET_MAC_CFG2 0x5004
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#define ET_MAC_CFG2_FDX 0x00000001
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#define ET_MAC_CFG2_CRC 0x00000002
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#define ET_MAC_CFG2_PADCRC 0x00000004
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#define ET_MAC_CFG2_LENCHK 0x00000010
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#define ET_MAC_CFG2_BIGFRM 0x00000020
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#define ET_MAC_CFG2_MODE_MII 0x00000100
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#define ET_MAC_CFG2_MODE_GMII 0x00000200
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#define ET_MAC_CFG2_PREAMBLE_LEN_MASK 0x0000F000
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#define ET_MAC_CFG2_PREAMBLE_LEN_SHIFT 12
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#define ET_IPG 0x5008
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#define ET_IPG_B2B_MASK 0x0000007F
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#define ET_IPG_MINIFG_MASK 0x0000FF00
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#define ET_IPG_NONB2B_2_MASK 0x007F0000
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#define ET_IPG_NONB2B_1_MASK 0x7F000000
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#define ET_IPG_B2B_SHIFT 0
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#define ET_IPG_MINIFG_SHIFT 8
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#define ET_IPG_NONB2B_2_SHIFT 16
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#define ET_IPG_NONB2B_1_SHIFT 24
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#define ET_MAC_HDX 0x500c
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#define ET_MAC_HDX_COLLWIN_MASK 0x000003FF
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#define ET_MAC_HDX_REXMIT_MAX_MASK 0x0000F000
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#define ET_MAC_HDX_EXC_DEFER 0x00010000
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#define ET_MAC_HDX_NOBACKOFF 0x00020000
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#define ET_MAC_HDX_BP_NOBACKOFF 0x00040000
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#define ET_MAC_HDX_ALT_BEB 0x00080000
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#define ET_MAC_HDX_ALT_BEB_TRUNC_MASK 0x00F00000
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#define ET_MAC_HDX_COLLWIN_SHIFT 0
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#define ET_MAC_HDX_REXMIT_MAX_SHIFT 12
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#define ET_MAC_HDX_ALT_BEB_TRUNC_SHIFT 20
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#define ET_MAX_FRMLEN 0x5010
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#define ET_MII_CFG 0x5020
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#define ET_MII_CFG_CLKRST 0x00000007
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#define ET_MII_CFG_PREAMBLE_SUP 0x00000010
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#define ET_MII_CFG_SCAN_AUTOINC 0x00000020
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#define ET_MII_CFG_RST 0x80000000
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#define ET_MII_CMD 0x5024
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#define ET_MII_CMD_READ 0x00000001
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#define ET_MII_ADDR 0x5028
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#define ET_MII_ADDR_REG_MASK 0x0000001F
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#define ET_MII_ADDR_PHY_MASK 0x00001F00
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#define ET_MII_ADDR_REG_SHIFT 0
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#define ET_MII_ADDR_PHY_SHIFT 8
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#define ET_MII_CTRL 0x502c
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#define ET_MII_CTRL_VALUE_MASK 0x0000FFFF
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#define ET_MII_CTRL_VALUE_SHIFT 0
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#define ET_MII_STAT 0x5030
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#define ET_MII_STAT_VALUE_MASK 0x0000FFFF
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#define ET_MII_IND 0x5034
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#define ET_MII_IND_BUSY 0x00000001
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#define ET_MII_IND_INVALID 0x00000004
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#define ET_MAC_CTRL 0x5038
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#define ET_MAC_CTRL_MODE_MII 0x01000000
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#define ET_MAC_CTRL_LHDX 0x02000000
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#define ET_MAC_CTRL_GHDX 0x04000000
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#define ET_MAC_ADDR1 0x5040
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#define ET_MAC_ADDR2 0x5044
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#define ET_MMC_CTRL 0x7000
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#define ET_MMC_CTRL_ENABLE 0x00000001
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#define ET_MMC_CTRL_ARB_DISABLE 0x00000002
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#define ET_MMC_CTRL_RXMAC_DISABLE 0x00000004
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#define ET_MMC_CTRL_TXMAC_DISABLE 0x00000008
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#define ET_MMC_CTRL_TXDMA_DISABLE 0x00000010
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#define ET_MMC_CTRL_RXDMA_DISABLE 0x00000020
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#define ET_MMC_CTRL_FORCE_CE 0x00000040
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/*
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* Interrupts
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*/
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#define ET_INTR_TXEOF 0x00000008
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#define ET_INTR_TXDMA_ERROR 0x00000010
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#define ET_INTR_RXEOF 0x00000020
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#define ET_INTR_RXRING0_LOW 0x00000040
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#define ET_INTR_RXRING1_LOW 0x00000080
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#define ET_INTR_RXSTAT_LOW 0x00000100
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#define ET_INTR_RXDMA_ERROR 0x00000200
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#define ET_INTR_TIMER 0x00004000
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#define ET_INTR_WOL 0x00008000
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#define ET_INTR_PHY 0x00010000
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#define ET_INTR_TXMAC 0x00020000
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#define ET_INTR_RXMAC 0x00040000
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#define ET_INTR_MAC_STATS 0x00080000
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#define ET_INTR_SLAVE_TO 0x00100000
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#define ET_INTRS (ET_INTR_TXEOF | \
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ET_INTR_RXEOF | \
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ET_INTR_TIMER)
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/*
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* RX ring position uses same layout
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*/
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#define ET_RX_RING_POS_INDEX_MASK 0x000003FF
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#define ET_RX_RING_POS_WRAP 0x00000400
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/*
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* PCI IDs
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*/
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#define PCI_VENDOR_LUCENT 0x11c1
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#define PCI_PRODUCT_LUCENT_ET1310 0xed00 /* ET1310 10/100/1000M Ethernet */
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#define PCI_PRODUCT_LUCENT_ET1310_FAST 0xed01 /* ET1310 10/100M Ethernet */
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#endif /* !_IF_ETREG_H */
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