Wojciech Macek d32802f0c3 PowerNV: fix compilation on non-NV platforms ... Submitted by: Wojciech Macek <wma@semihalf.com> Obtained from: Semihalf Sponsored by: IBM, QCM Technologies		2018-01-31 06:42:01 +00:00
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aim_machdep.c	Install the SLB miss trap-handling code in the SLB-based MMU driver set up,	2018-01-15 16:08:34 +00:00
locore32.S	Use the cookie now set by loader to determine whether the value passed to	2017-11-26 03:53:20 +00:00
locore64.S	Make sure the first instruction of the low-memory spinloop is in the	2017-12-31 05:38:19 +00:00
locore.S	Add a kdb show command to print arbitrary SPRs on PowerPC	2016-08-13 18:46:49 +00:00
mmu_oea64.c	Remove hard-coded trap-handling logic involving the segmented memory model	2018-01-29 04:33:41 +00:00
mmu_oea64.h	sys/powerpc: further adoption of SPDX licensing ID tags.	2017-11-27 15:09:59 +00:00
mmu_oea.c	Remove hard-coded trap-handling logic involving the segmented memory model	2018-01-29 04:33:41 +00:00
moea64_if.m
moea64_native.c	sys/powerpc: further adoption of SPDX licensing ID tags.	2017-11-27 15:09:59 +00:00
mp_cpudep.c	PowerNV: fix compilation on non-NV platforms	2018-01-31 06:42:01 +00:00
slb.c	Document places we assume that physical memory is direct-mapped at zero by	2018-01-13 23:14:53 +00:00
trap_subr32.S	Use the explicit expanded form of cmp.	2017-01-18 03:42:21 +00:00
trap_subr64.S	On AIM systems without a software-managed SLB, such as POWER9 systems using	2018-01-19 22:19:50 +00:00