384 lines
12 KiB
C
384 lines
12 KiB
C
/*-
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* Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/ata.h>
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#include <sys/bus.h>
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#include <sys/endian.h>
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#include <sys/malloc.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sema.h>
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#include <sys/taskqueue.h>
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#include <vm/uma.h>
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#include <machine/stdarg.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <dev/ata/ata-all.h>
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#include <dev/ata/ata-pci.h>
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#include <ata_if.h>
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/* local prototypes */
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static int ata_serverworks_chipinit(device_t dev);
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static int ata_serverworks_ch_attach(device_t dev);
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static int ata_serverworks_ch_detach(device_t dev);
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static void ata_serverworks_tf_read(struct ata_request *request);
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static void ata_serverworks_tf_write(struct ata_request *request);
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static int ata_serverworks_setmode(device_t dev, int target, int mode);
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static void ata_serverworks_sata_reset(device_t dev);
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static int ata_serverworks_status(device_t dev);
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/* misc defines */
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#define SWKS_33 0
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#define SWKS_66 1
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#define SWKS_100 2
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#define SWKS_MIO 3
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/*
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* ServerWorks chipset support functions
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*/
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static int
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ata_serverworks_probe(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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static const struct ata_chip_id ids[] =
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{{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" },
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{ ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" },
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{ ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" },
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{ ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" },
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{ ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" },
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{ ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" },
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{ ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
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{ ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" },
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{ ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" },
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{ ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" },
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{ ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" },
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{ 0, 0, 0, 0, 0, 0}};
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if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID)
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return ENXIO;
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if (!(ctlr->chip = ata_match_chip(dev, ids)))
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return ENXIO;
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ata_set_desc(dev);
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ctlr->chipinit = ata_serverworks_chipinit;
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return (BUS_PROBE_LOW_PRIORITY);
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}
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static int
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ata_serverworks_status(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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/*
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* Check if this interrupt belongs to our channel.
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*/
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if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit)))
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return (0);
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/*
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* We need to do a 4-byte read on the status reg before the values
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* will report correctly
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*/
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ATA_IDX_INL(ch,ATA_STATUS);
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return ata_pci_status(dev);
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}
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static int
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ata_serverworks_chipinit(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(dev);
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if (ata_setup_interrupt(dev, ata_generic_intr))
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return ENXIO;
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if (ctlr->chip->cfg1 == SWKS_MIO) {
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ctlr->r_type2 = SYS_RES_MEMORY;
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ctlr->r_rid2 = PCIR_BAR(5);
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if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
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&ctlr->r_rid2, RF_ACTIVE)))
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return ENXIO;
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ctlr->channels = ctlr->chip->cfg2;
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ctlr->ch_attach = ata_serverworks_ch_attach;
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ctlr->ch_detach = ata_serverworks_ch_detach;
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ctlr->setmode = ata_sata_setmode;
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ctlr->getrev = ata_sata_getrev;
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ctlr->reset = ata_serverworks_sata_reset;
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return 0;
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}
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else if (ctlr->chip->cfg1 == SWKS_33) {
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device_t *children;
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int nchildren, i;
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/* locate the ISA part in the southbridge and enable UDMA33 */
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if (!device_get_children(device_get_parent(dev), &children,&nchildren)){
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for (i = 0; i < nchildren; i++) {
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if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) {
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pci_write_config(children[i], 0x64,
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(pci_read_config(children[i], 0x64, 4) &
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~0x00002000) | 0x00004000, 4);
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break;
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}
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}
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free(children, M_TEMP);
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}
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}
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else {
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pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) |
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((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1);
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}
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ctlr->setmode = ata_serverworks_setmode;
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return 0;
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}
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static int
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ata_serverworks_ch_attach(device_t dev)
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{
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struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
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struct ata_channel *ch = device_get_softc(dev);
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int ch_offset;
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int i;
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ch_offset = ch->unit * 0x100;
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for (i = ATA_DATA; i < ATA_MAX_RES; i++)
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ch->r_io[i].res = ctlr->r_res2;
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/* setup ATA registers */
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ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
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ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04;
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ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
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ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
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ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
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ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
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ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
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ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c;
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ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20;
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ata_default_registers(dev);
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/* setup DMA registers */
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ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30;
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ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32;
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ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34;
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/* setup SATA registers */
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ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40;
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ch->r_io[ATA_SERROR].offset = ch_offset + 0x44;
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ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48;
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ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE;
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ata_pci_hw(dev);
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ch->hw.tf_read = ata_serverworks_tf_read;
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ch->hw.tf_write = ata_serverworks_tf_write;
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if (ctlr->chip->chipid == ATA_K2) {
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/*
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* Set SICR registers to turn off waiting for a status message
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* before sending FIS. Values obtained from the Darwin driver.
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*/
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ATA_OUTL(ctlr->r_res2, ch_offset + 0x80,
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ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000);
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ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0);
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/*
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* Some controllers have a bug where they will send the command
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* to the drive before seeing a DMA start, and then can begin
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* receiving data before the DMA start arrives. The controller
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* will then become confused and either corrupt the data or crash.
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* Remedy this by starting DMA before sending the drive command.
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*/
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ch->flags |= ATA_DMA_BEFORE_CMD;
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/*
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* The status register must be read as a long to fill the other
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* registers.
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*/
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ch->hw.status = ata_serverworks_status;
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ch->flags |= ATA_STATUS_IS_LONG;
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}
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/* chip does not reliably do 64K DMA transfers */
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ch->dma.max_iosize = 64 * DEV_BSIZE;
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ata_pci_dmainit(dev);
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return 0;
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}
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static int
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ata_serverworks_ch_detach(device_t dev)
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{
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ata_pci_dmafini(dev);
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return (0);
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}
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static void
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ata_serverworks_tf_read(struct ata_request *request)
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{
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struct ata_channel *ch = device_get_softc(request->parent);
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if (request->flags & ATA_R_48BIT) {
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u_int16_t temp;
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request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT);
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temp = ATA_IDX_INW(ch, ATA_SECTOR);
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request->u.ata.lba = (u_int64_t)(temp & 0x00ff) |
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((u_int64_t)(temp & 0xff00) << 24);
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temp = ATA_IDX_INW(ch, ATA_CYL_LSB);
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request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) |
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((u_int64_t)(temp & 0xff00) << 32);
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temp = ATA_IDX_INW(ch, ATA_CYL_MSB);
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request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) |
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((u_int64_t)(temp & 0xff00) << 40);
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}
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else {
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request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff;
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request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) |
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((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) |
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((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) |
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((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24);
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}
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}
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static void
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ata_serverworks_tf_write(struct ata_request *request)
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{
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struct ata_channel *ch = device_get_softc(request->parent);
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if (request->flags & ATA_R_48BIT) {
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ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
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ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
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ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
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(request->u.ata.lba & 0x00ff));
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ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
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((request->u.ata.lba >> 8) & 0x00ff));
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ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
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((request->u.ata.lba >> 16) & 0x00ff));
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ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
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}
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else {
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ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
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ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
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ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba);
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ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
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ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
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ATA_IDX_OUTW(ch, ATA_DRIVE,
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ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
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((request->u.ata.lba >> 24) & 0x0f));
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}
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}
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static int
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ata_serverworks_setmode(device_t dev, int target, int mode)
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{
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device_t parent = device_get_parent(dev);
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struct ata_pci_controller *ctlr = device_get_softc(parent);
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struct ata_channel *ch = device_get_softc(dev);
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int devno = (ch->unit << 1) + target;
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int offset = (devno ^ 0x01) << 3;
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int piomode;
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static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 };
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static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 };
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mode = min(mode, ctlr->chip->max_dma);
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if (mode >= ATA_UDMA0) {
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/* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */
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pci_write_config(parent, 0x56,
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(pci_read_config(parent, 0x56, 2) &
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~(0xf << (devno << 2))) |
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((mode & ATA_MODE_MASK) << (devno << 2)), 2);
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pci_write_config(parent, 0x54,
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pci_read_config(parent, 0x54, 1) |
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(0x01 << devno), 1);
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pci_write_config(parent, 0x44,
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(pci_read_config(parent, 0x44, 4) &
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~(0xff << offset)) |
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(dmatimings[2] << offset), 4);
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piomode = ATA_PIO4;
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} else if (mode >= ATA_WDMA0) {
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/* Disable UDMA, set WDMA mode and timings, calculate PIO. */
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pci_write_config(parent, 0x54,
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pci_read_config(parent, 0x54, 1) &
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~(0x01 << devno), 1);
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pci_write_config(parent, 0x44,
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(pci_read_config(parent, 0x44, 4) &
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~(0xff << offset)) |
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(dmatimings[mode & ATA_MODE_MASK] << offset), 4);
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piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
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(mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
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} else {
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/* Disable UDMA, set requested PIO. */
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pci_write_config(parent, 0x54,
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pci_read_config(parent, 0x54, 1) &
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~(0x01 << devno), 1);
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piomode = mode;
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}
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/* Set PIO mode and timings, calculated above. */
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if (ctlr->chip->cfg1 != SWKS_33) {
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pci_write_config(parent, 0x4a,
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(pci_read_config(parent, 0x4a, 2) &
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~(0xf << (devno << 2))) |
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((piomode - ATA_PIO0) << (devno<<2)),2);
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}
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pci_write_config(parent, 0x40,
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(pci_read_config(parent, 0x40, 4) &
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~(0xff << offset)) |
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(piotimings[ata_mode2idx(piomode)] << offset), 4);
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return (mode);
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}
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static void
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ata_serverworks_sata_reset(device_t dev)
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{
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struct ata_channel *ch = device_get_softc(dev);
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if (ata_sata_phy_reset(dev, -1, 0))
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ata_generic_reset(dev);
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else
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ch->devices = 0;
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}
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ATA_DECLARE_DRIVER(ata_serverworks);
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