2edabad8a4
* Support for sam9 "EMAC" controller.
* Support for rmii interface to phy.
at91.c & at91sam9.c:
* Eliminate separate at91sam9.c file.
* Add new devices to at91sam9_devs table.
at91_machdep.c & at at91sam9_machdep.c:
* Automatic chip type determination.
* Remove compile time chip dependencies.
* Eliminate separate at91sam9_machdep.c file.
at91_pmc.c:
* Corrected support for all of the sam926? and sam9g20 chips.
* Remove compile time chip dependencies.
My apologies to Greg for taking so long to take care of it.
58 lines
1.6 KiB
ArmAsm
58 lines
1.6 KiB
ArmAsm
#include <machine/asm.h>
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#include <arm/at91/at91_rstreg.h>
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#include <arm/at91/at91sam9g20reg.h>
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__FBSDID("$FreeBSD$");
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#define SDRAM_TR (AT91SAM9G20_BASE + \
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AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_TR)
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#define SDRAM_LPR (AT91SAM9G20_BASE + \
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AT91SAM9G20_SDRAMC_BASE + AT91SAM9G20_SDRAMC_LPR)
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#define RSTC_RCR (AT91SAM9G20_BASE + \
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AT91SAM9G20_RSTC_BASE + RST_CR)
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/*
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* From AT91SAM9G20 Datasheet errata 44:3.5:
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*
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* When User Reset occurs durring SDRAM read acces, eh SDRAM clock is turned
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* off while data are ready to be read on the data bus. The SDRAM maintains
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* the data until the clock restarts.
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*
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* If the User reset is programed to assert a general reset, the data
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* If the User reset is programed to assert a general reset, the data
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* maintained by the SDRAM leads to a data bus conflict and adversly affects
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* the boot memories connected to the EBI:
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* + NAND Flash boot functionality, if the system boots out of internal ROM.
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* + NOR Flash boot, if the system boots on an external memory connected to
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* the EBI CS0.
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*
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* Assembly code is mandatory for the following sequnce as ARM
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* instructions need to be piplined.
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*
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*/
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ENTRY(cpu_reset_sam9g20)
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/* Disable IRQs */
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mrs r0, cpsr
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orr r0, r0, #0x80
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msr cpsr_c, r0
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/* Change Refresh to block all data access */
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ldr r0, =SDRAM_TR
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ldr r1, =1
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str r1, [r0]
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/* Prepare power down command */
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ldr r0, =SDRAM_LPR
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ldr r1, =2
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/* Prepare proc_reset and periph reset */
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ldr r2, =RSTC_RCR
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ldr r3, =0xA5000005
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/* perform power down command */
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str r1, [r0]
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/* Perfom proc_reset and periph reset (in the ARM pipeline) */
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str r3, [r2]
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