2edabad8a4
* Support for sam9 "EMAC" controller.
* Support for rmii interface to phy.
at91.c & at91sam9.c:
* Eliminate separate at91sam9.c file.
* Add new devices to at91sam9_devs table.
at91_machdep.c & at at91sam9_machdep.c:
* Automatic chip type determination.
* Remove compile time chip dependencies.
* Eliminate separate at91sam9_machdep.c file.
at91_pmc.c:
* Corrected support for all of the sam926? and sam9g20 chips.
* Remove compile time chip dependencies.
My apologies to Greg for taking so long to take care of it.
60 lines
2.4 KiB
C
60 lines
2.4 KiB
C
/*-
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* Copyright (c) 2009 Greg Ansley. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef ARM_AT91_AT91RSTREG_H
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#define ARM_AT91_AT91RSTREG_H
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#define RST_CR 0x0 /* Control Register */
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#define RST_SR 0x4 /* Status Register */
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#define RST_MR 0x8 /* Mode Register */
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/* RST_CR */
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#define RST_CR_PROCRST (1<<0)
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#define RST_CR_PERRST (1<<2)
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#define RST_CR_EXTRST (1<<3)
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#define RST_CR_KEY (0xa5<<24)
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/* RST_SR */
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#define RST_SR_SRCMP (1<<17) /* Software Reset in progress */
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#define RST_SR_NRSTL (1<<16) /* NRST pin level at MCK */
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#define RST_SR_URSTS (1<<0) /* NRST pin has been active */
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#define RST_SR_RST_POW (0<<8) /* General (Power On) reset */
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#define RST_SR_RST_WAKE (1<<8) /* Wake-up reset */
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#define RST_SR_RST_WDT (2<<8) /* Watchdog reset */
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#define RST_SR_RST_SOFT (3<<8) /* Software reset */
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#define RST_SR_RST_USR (4<<8) /* User (External) reset */
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#define RST_SR_RST_MASK (7<<8) /* User (External) reset */
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/* RST_MR */
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#define RST_MR_URSTEN (1<<0) /* User reset enable */
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#define RST_MR_URSIEN (1<<4) /* User interrupt enable */
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#define RST_MR_ERSTL(x) ((x)<<8) /* External reset length */
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#define RST_MR_KEY (0xa5<<24)
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#endif /* ARM_AT91_AT91RSTREG_H */
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