223 lines
8.8 KiB
Groff
223 lines
8.8 KiB
Groff
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.\" ========================================================================
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.\"
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.IX Title "OPENSSL_ia32cap 3"
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.TH OPENSSL_ia32cap 3 "2017-05-25" "1.0.2l" "OpenSSL"
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.\" For nroff, turn off justification. Always turn off hyphenation; it makes
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.\" way too many mistakes in technical documents.
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.if n .ad l
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.nh
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.SH "NAME"
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OPENSSL_ia32cap, OPENSSL_ia32cap_loc \- the IA\-32 processor capabilities vector
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.SH "SYNOPSIS"
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.IX Header "SYNOPSIS"
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.Vb 2
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\& unsigned long *OPENSSL_ia32cap_loc(void);
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\& #define OPENSSL_ia32cap ((OPENSSL_ia32cap_loc())[0])
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.Ve
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.SH "DESCRIPTION"
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.IX Header "DESCRIPTION"
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Value returned by \fIOPENSSL_ia32cap_loc()\fR is address of a variable
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containing \s-1IA\-32\s0 processor capabilities bit vector as it appears in
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\&\s-1EDX:ECX\s0 register pair after executing \s-1CPUID\s0 instruction with EAX=1
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input value (see Intel Application Note #241618). Naturally it's
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meaningful on x86 and x86_64 platforms only. The variable is normally
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set up automatically upon toolkit initialization, but can be
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manipulated afterwards to modify crypto library behaviour. For the
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moment of this writing following bits are significant:
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.IP "bit #4 denoting presence of Time-Stamp Counter." 4
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.IX Item "bit #4 denoting presence of Time-Stamp Counter."
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.PD 0
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.IP "bit #19 denoting availability of \s-1CLFLUSH\s0 instruction;" 4
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.IX Item "bit #19 denoting availability of CLFLUSH instruction;"
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.IP "bit #20, reserved by Intel, is used to choose among \s-1RC4\s0 code paths;" 4
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.IX Item "bit #20, reserved by Intel, is used to choose among RC4 code paths;"
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.IP "bit #23 denoting \s-1MMX\s0 support;" 4
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.IX Item "bit #23 denoting MMX support;"
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.IP "bit #24, \s-1FXSR\s0 bit, denoting availability of \s-1XMM\s0 registers;" 4
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.IX Item "bit #24, FXSR bit, denoting availability of XMM registers;"
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.IP "bit #25 denoting \s-1SSE\s0 support;" 4
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.IX Item "bit #25 denoting SSE support;"
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.IP "bit #26 denoting \s-1SSE2\s0 support;" 4
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.IX Item "bit #26 denoting SSE2 support;"
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.IP "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;" 4
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.IX Item "bit #28 denoting Hyperthreading, which is used to distinguish cores with shared cache;"
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.IP "bit #30, reserved by Intel, denotes specifically Intel CPUs;" 4
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.IX Item "bit #30, reserved by Intel, denotes specifically Intel CPUs;"
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.IP "bit #33 denoting availability of \s-1PCLMULQDQ\s0 instruction;" 4
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.IX Item "bit #33 denoting availability of PCLMULQDQ instruction;"
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.IP "bit #41 denoting \s-1SSSE3,\s0 Supplemental \s-1SSE3,\s0 support;" 4
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.IX Item "bit #41 denoting SSSE3, Supplemental SSE3, support;"
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.IP "bit #43 denoting \s-1AMD XOP\s0 support (forced to zero on non-AMD CPUs);" 4
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.IX Item "bit #43 denoting AMD XOP support (forced to zero on non-AMD CPUs);"
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.IP "bit #57 denoting AES-NI instruction set extension;" 4
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.IX Item "bit #57 denoting AES-NI instruction set extension;"
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.IP "bit #59, \s-1OSXSAVE\s0 bit, denoting availability of \s-1YMM\s0 registers;" 4
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.IX Item "bit #59, OSXSAVE bit, denoting availability of YMM registers;"
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.IP "bit #60 denoting \s-1AVX\s0 extension;" 4
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.IX Item "bit #60 denoting AVX extension;"
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.IP "bit #62 denoting availability of \s-1RDRAND\s0 instruction;" 4
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.IX Item "bit #62 denoting availability of RDRAND instruction;"
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.PD
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.PP
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For example, clearing bit #26 at run-time disables high-performance
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\&\s-1SSE2\s0 code present in the crypto library, while clearing bit #24
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disables \s-1SSE2\s0 code operating on 128\-bit \s-1XMM\s0 register bank. You might
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have to do the latter if target OpenSSL application is executed on \s-1SSE2\s0
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capable \s-1CPU,\s0 but under control of \s-1OS\s0 that does not enable \s-1XMM\s0
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registers. Even though you can manipulate the value programmatically,
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you most likely will find it more appropriate to set up an environment
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variable with the same name prior starting target application, e.g. on
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Intel P4 processor 'env OPENSSL_ia32cap=0x16980010 apps/openssl', or
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better yet 'env OPENSSL_ia32cap=~0x1000000 apps/openssl' to achieve same
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effect without modifying the application source code. Alternatively you
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can reconfigure the toolkit with no\-sse2 option and recompile.
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.PP
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Less intuitive is clearing bit #28. The truth is that it's not copied
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from \s-1CPUID\s0 output verbatim, but is adjusted to reflect whether or not
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the data cache is actually shared between logical cores. This in turn
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affects the decision on whether or not expensive countermeasures
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against cache-timing attacks are applied, most notably in \s-1AES\s0 assembler
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module.
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.PP
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The vector is further extended with \s-1EBX\s0 value returned by \s-1CPUID\s0 with
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EAX=7 and ECX=0 as input. Following bits are significant:
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.IP "bit #64+3 denoting availability of \s-1BMI1\s0 instructions, e.g. \s-1ANDN\s0;" 4
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.IX Item "bit #64+3 denoting availability of BMI1 instructions, e.g. ANDN;"
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.PD 0
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.IP "bit #64+5 denoting availability of \s-1AVX2\s0 instructions;" 4
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.IX Item "bit #64+5 denoting availability of AVX2 instructions;"
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.IP "bit #64+8 denoting availability of \s-1BMI2\s0 instructions, e.g. \s-1MUXL\s0 and \s-1RORX\s0;" 4
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.IX Item "bit #64+8 denoting availability of BMI2 instructions, e.g. MUXL and RORX;"
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.IP "bit #64+18 denoting availability of \s-1RDSEED\s0 instruction;" 4
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.IX Item "bit #64+18 denoting availability of RDSEED instruction;"
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.IP "bit #64+19 denoting availability of \s-1ADCX\s0 and \s-1ADOX\s0 instructions;" 4
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.IX Item "bit #64+19 denoting availability of ADCX and ADOX instructions;"
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